Not recommended for new designs

Please use 93LC76C or 93LC86C.

93C76/86
8K/16K 5.0V Microwire Serial EEPROM
Features: Package Types
Single 5.0V supply
PDIP Package
Low-power CMOS technology
- 1 mA active current typical
ORG pin selectable memory configuration CS 1 8 VCC

93C76/86
1024 x 8- or 512 x 16-bit organization (93C76) 7
CLK 2 PE
2048 x 8- or 1024 x 16-bit organization (93C86)
DI 3 6 ORG
Self-timed erase and write cycles
DO 4 5 VSS
(including auto-erase)
Automatic ERAL before WRAL
Power on/off data protection circuitry
SOIC Package
Industry standard 3-wire serial I/O
Device status signal during erase/write cycles
1 8

93C76/86
Sequential read function CS VCC
1,000,000 erase/write cycles ensured CLK 2 7 PE
Data retention > 200 years DI 3 6 ORG
DO 4 5 VSS
8-pin PDIP/SOIC package
Temperature ranges supported
- Commercial (C): 0C to +70C
- Industrial (I): -40C to +85C Block Diagram
- Automotive (E) -40C to +125C
VCC VSS
Description:
The Microchip Technology Inc. 93C76/86 are 8K and
Memory Address
16K low voltage serial Electrically Erasable PROMs. Array Decoder
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
nonvolatile memory applications. These devices also Address
Counter
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93C76/86 is available in standard 8-pin PDIP and
8-pin surface mount SOIC packages. Data Output
Register Buffer
DO

DI

Mode
PE Decode
CS Logic

Clock
CLK
Generator

1996-2012 Microchip Technology Inc. DS21132F-page 1

93C76/86
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings()

VCC .............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to Vcc + 1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied ................................................................................................-40C to +125C
Soldering temperature of leads (10 seconds) .......................................................................................................+300C
ESD protection on all pins ..........................................................................................................................................4 kV

NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

1.1 AC Test Conditions

AC Waveform:
VLO = 2.0V
VHI = Vcc - 0.2V (Note 1)
VHI = 4.0V for (Note 2)

Timing Measurement Reference Level

Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC 4.0V
2: For VCC > 4.0V

DS21132F-page 2 1996-2012 Microchip Technology Inc.

 93C76/86
TABLE 1-1: DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = +4.5V to +5.5V
DC CHARACTERISTICS Commercial (C): TA = 0C to -40C
Industrial (I): TA = -40C to +85C
Automotive (E): TA = -40C to +125C
Parameter Symbol Min. Max. Units Conditions
High-level input voltage VIH1 2.0 VCC +1 V
Low-level input voltage VIL1 -0.3 0.8 V
Low-level output voltage VOL1 0.4 V IOL = 2.1 mA; VCC = 4.5V
VOL2 0.2 V IOL =100 A; VCC = 4.5V
High-level output voltage VOH1 2.4 V IOH = -400 A; VCC = 4.5V
VOH2 VCC-0.2 V IOH = -100 A; VCC = 4.5V.
Input leakage current ILI -10 10 A VIN = 0.1V to VCC
Output leakage current ILO -10 10 A VOUT = 0.1V to VCC
Pin capacitance CINT 7 pF (Note 1)
(all inputs/outputs) TA = +25C, FCLK = 1 MHz
Operating current ICC write 3 mA FCLK = 2 MHz; VCC = 5.5V
ICC read 1.5 mA FCLK = 2 MHz; VCC = 5.5V
Standby current ICCS 100 A CLK = CS = 0V; VCC = 5.5V
DI = PE = VSS
ORG = VSS or VCC
Note 1: This parameter is periodically sampled and not 100% tested.

TABLE 1-2: AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = +4.5V to +5.5V
AC CHARACTERISTICS Commercial (C): TA = 0C to -40C
Industrial (I): TA = -40C to +85C
Automotive (E): TA = -40C to +125C
Parameter Symbol Min. Max. Units Conditions
Clock frequency FCLK 2 MHz Vcc 4.5V
Clock high time TCKH 300 ns
Clock low time TCKL 200 ns
Chip select setup time TCSS 50 ns Relative to CLK
Chip select hold time TCSH 0 ns
Chip select low time TCSL 250 ns Relative to CLK
Data input setup time TDIS 100 ns Relative to CLK
Data input hold time TDIH 100 ns Relative to CLK
Data output delay time TPD 400 ns CL = 100 pF
Data output disable time TCZ 100 ns (Note 1)
Status valid time TSV 500 ns CL = 100 pF
Program cycle time TWC 10 ms Erase/Write mode (Note 2)
TEC 15 ms ERAL mode
TWL 30 ms WRAL mode
Endurance 1M cycles 25C, VCC = 5.0V, Block mode
(Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: Typical program cycle is 4 ms per word.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained from Microchips web site
at www.microchip.com.

1996-2012 Microchip Technology Inc. DS21132F-page 3

93C76/86
TABLE 1-3: INSTRUCTION SET FOR 93C76: ORG=1 (X16 ORGANIZATION)
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 29
EWEN 1 00 1 1 X X X X X X X X High-Z 13
ERASE 1 11 X A8 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY) 13
ERAL 1 00 1 0 X X X X X X X X (RDY/BSY) 13
WRITE 1 01 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29
WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29
EWDS 1 00 0 0 X X X X X X X X High-Z 13

TABLE 1-4: INSTRUCTION SET FOR 93C76: ORG=0 (X8 ORGANIZATION)

Req. CLK
Instruction SB Opcode Address Data In Data Out
Cycles
READ 1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 22
EWEN 1 00 1 1 X X X X X X X X X High-Z 14
ERASE 1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY) 14
ERAL 1 00 1 0 X X X X X X X X X (RDY/BSY) 14
WRITE 1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22
WRAL 1 00 0 1 X X X X X X X X X D7 - D0 (RDY/BSY) 22
EWDS 1 00 0 0 X X X X X X X X X High-Z 14

TABLE 1-5: INSTRUCTION SET FOR 93C86: ORG=1 (X16 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 29
EWEN 1 00 1 1 X X X X X X X X High-Z 13
ERASE 1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY) 13
ERAL 1 00 1 0 X X X X X X X X (RDY/BSY) 13
WRITE 1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29
WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29
EWDS 1 00 0 0 X X X X X X X X High-Z 13

TABLE 1-6: INSTRUCTION SET FOR 93C86: ORG=0 (X8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
READ 1 10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 22
EWEN 1 00 1 1 X X X X X X X X X High-Z 14
ERASE 1 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY) 14
ERAL 1 00 1 0 X X X X X X X X X (RDY/BSY) 14
WRITE 1 01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22
WRAL 1 00 0 1 X X X X X X X X X D7 - D0 (RDY/BSY) 22
EWDS 1 00 0 0 X X X X X X X X X High-Z 14

DS21132F-page 4 1996-2012 Microchip Technology Inc.

 93C76/86
2.0 PRINCIPLES OF OPERATION 2.3 Erase/Write Enable and Disable
(EWEN, EWDS)
When the ORG pin is connected to VCC, the x16 orga-
nization is selected. When it is connected to ground, The 93C76/86 powers up in the Erase/Write Disable
the x8 organization is selected. Instructions, addresses (EWDS) state. All programming modes must be
and write data are clocked into the DI pin on the rising preceded by an Erase/Write Enable (EWEN) instruction.
edge of the clock (CLK). The DO pin is normally held in Once the EWEN instruction is executed, programming
a high-Z state except when reading data from the remains enabled until an EWDS instruction is executed
device, or when checking the Ready/Busy status or VCC is removed from the device. To protect against
during a programming operation. The Ready/Busy accidental data disturb, the EWDS instruction can be
status can be verified during an erase/write operation used to disable all erase/write functions and should
by polling the DO pin; DO low indicates that program- follow all programming operations. Execution of a READ
ming is still in progress, while DO high indicates the instruction is independent of both the EWEN and EWDS
device is ready. The DO will enter the high-impedance instructions.
state on the falling edge of the CS.
2.4 Data Protection
2.1 Start Condition
During power-up, all programming modes of operation
The Start bit is detected by the device if CS and DI are are inhibited until VCC has reached a level greater than
both high with respect to the positive edge of CLK for 1.4V. During power-down, the source data protection
the first time. circuitry acts to inhibit all programming modes when
Before a Start condition is detected, CS, CLK and DI VCC has fallen below 1.4V.
may change in any combination (except to that of a The EWEN and EWDS commands give additional
Start condition), without resulting in any device opera- protection against accidentally programming during
tion (Read, Write, Erase, EWEN, EWDS, ERAL and normal operation.
WRAL). As soon as CS is high, the device is no longer
After power-up, the device is automatically in the
in the Standby mode.
EWDS mode. Therefore, an EWEN instruction must be
An instruction following a Start condition will only be performed before any ERASE or WRITE instruction can
executed if the required amount of opcode, address be executed.
and data bits for any particular instruction are clocked
in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new Start condition is
detected.

2.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a bus conflict to occur during the dummy zero
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.

1996-2012 Microchip Technology Inc. DS21132F-page 5

93C76/86
3.0 DEVICE OPERATION 3.4 Erase All (ERAL)
The ERAL instruction will erase the entire memory array
3.1 Read to the logical 1 state. The ERAL cycle is identical to
The READ instruction outputs the serial data of the the erase cycle except for the different opcode. The
addressed memory location on the DO pin. A dummy ERAL cycle is completely self-timed and commences
zero bit precedes the 16-bit (x16 organization) or 8-bit on the rising edge of the last address bit (A0). Note that
(x8 organization) output string. The output data bits will the Least Significant 8 or 9 address bits are "dont care"
toggle on the rising edge of the CLK and are stable bits, depending on selection of x16 or x8 mode. Clock-
after the specified time delay (TPD). Sequential read is ing of the CLK pin is not necessary after the device has
possible when CS is held high and clock transitions entered the self clocking mode. The ERAL instruction is
continue. The memory address pointer will automati- ensured at Vcc = +4.5V to +5.5V.
cally increment and output data sequentially. The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
3.2 Erase displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
The ERASE instruction forces all data bits of the place the device in Standby mode and cause the DO
specified address to the logical 1 state. The self-timed pin to enter the high-impedance state. DO at logical 0
programming cycle is initiated on the rising edge of indicates that programming is still in progress. DO at
CLK as the last address bit (A0) is clocked in. At this logical 1 indicates that the entire device has been
point, the CLK, CS and DI inputs become dont cares. erased and is ready for another instruction.
The DO pin indicates the Ready/Busy status of the The ERAL cycle takes 15 ms maximum (8 ms typical).
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is 3.5 Write All (WRAL)
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO The WRAL instruction will write the entire memory array
pin to enter the high-impedance state. DO at logical 0 with the data specified in the command. The WRAL
indicates that programming is still in progress. DO at cycle is completely self-timed and commences on the
logical 1 indicates that the register at the specified rising edge of the last address bit (A0). Note that the
address has been erased and the device is ready for Least Significant 8 or 9 address bits are dont cares,
another instruction. depending on selection of x16 or x8 mode. Clocking of
The erase cycle takes 3 ms per word (typical). the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
3.3 Write Therefore, the WRAL instruction does not require an
The WRITE instruction is followed by 16 bits (or by 8 ERAL instruction but the chip must be in the EWEN
bits) of data to be written into the specified address. status. The WRAL instruction is ensured at Vcc = +4.5V
The self-timed programming cycle is initiated on the to +5.5V.
rising edge of CLK as the last data bit (D0) is clocked The DO pin indicates the Ready/Busy status of the
in. At this point, the CLK, CS and DI inputs become device if the CS is high. The Ready/Busy status will be
dont cares. displayed on the DO pin until the next Start bit is
The DO pin indicates the Ready/Busy status of the received as long as CS is high. Bringing the CS low will
device if the CS is high. The Ready/Busy status will be place the device in Standby mode and cause the DO
displayed on the DO pin until the next Start bit is pin to enter the high-impedance state. DO at logical 0
received as long as CS is high. Bringing the CS low will indicates that programming is still in progress. DO at
place the device in Standby mode and cause the DO logical 1 indicates that the entire device has been
pin to enter the high-impedance state. DO at logical 0 written and is ready for another instruction.
indicates that programming is still in progress. DO at The WRAL cycle takes 30 ms maximum (16 ms
logical 1 indicates that the register at the specified typical).
address has been written and the device is ready for
another instruction.
The write cycle takes 3 ms per word (typical).

DS21132F-page 6 1996-2012 Microchip Technology Inc.

 93C76/86
FIGURE 3-1: SYNCHRONOUS DATA TIMING
VIH
CS TCSS TCKH TCKL
VIL
VIH TCSH
CLK
VIL TDIH
TDIS
VIH
DI
VIL
TPD TCZ
VOH TPD
DO
(Read) VOL TCZ
TSV
VOH
DO
(Program) VOL Status Valid

The memory automatically cycles to the next register.

FIGURE 3-2: READ

TCSL
CS

CLK

DI 1 1 0 AN ... A0

High-impedance ... ...

DO 0 DN D0 DN D0

FIGURE 3-3: EWEN

EWEN TCSL
CS

CLK

DI 1 0 0 1 1 x ... x

ORG = VCC, 8 XS
ORG = VSS, 9 XS

1996-2012 Microchip Technology Inc. DS21132F-page 7

93C76/86
FIGURE 3-4: EWDS

TCSL
CS

CLK

DI 1 0 0 0 0 x ... x

ORG = VCC, 8 Xs
ORG = VSS, 9 XS

FIGURE 3-5: WRITE

CS Standby

CLK

DI 1 0 1 AN ... A0 DN ... D0
TCZ
High-impedance Busy Ready
DO

TWC

FIGURE 3-6: WRAL

Standby
CS

CLK

DI 1 0 0 0 1 x ... x DN ... D0
TCZ
High-impedance Busy
DO Ready

ORG = VCC, 8 Xs TWL

ORG = VSS, 9 Xs Ensure at Vcc = +4.5V to +5.5V.

DS21132F-page 8 1996-2012 Microchip Technology Inc.

 93C76/86
FIGURE 3-7: ERASE

CS Standby

CLK

DI 1 1 1 AN ... ... A0

TCZ
High-impedance
DO Busy Ready

TWC

FIGURE 3-8: ERAL

CS Standby

CLK

DI 1 0 0 1 0 x ... x
TCZ
High-impedance
DO Busy Ready

TEC
ORG = VCC, 8 Xs
ORG = VSS, 9 Xs Ensure at VCC = +4.5V to +5.5V.

1996-2012 Microchip Technology Inc. DS21132F-page 9

93C76/86
4.0 PIN DESCRIPTIONS After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
TABLE 4-1: PIN FUNCTION TABLE
required to clock in all opcode, address, and data bits
Name Function before an instruction is executed (see Table 1-3
CS Chip Select through Table 1-6 for more details). CLK and DI then
become don't care inputs waiting for a new Start
CLK Serial Data Clock condition to be detected.
DI Serial Data Input
DO Serial Data Output Note: CS must go low between consecutive
VSS Ground instructions, except when performing a
ORG Memory Configuration sequential read (Refer to Section 3.1
Read for more detail on sequential
PE Program Enable reads).
VCC Power Supply
4.3 Data In (DI)
4.1 Chip Select (CS)
Data In is used to clock in a Start bit, opcode, address
A high level selects the device. A low level deselects and data synchronously with the CLK input.
the device and forces it into Standby mode. However, a
programming cycle which is already initiated will be 4.4 Data Out (DO)
completed, regardless of the CS input signal. If CS is
brought low during a program cycle, the device will go Data Out is used in the Read mode to output data
into Standby mode as soon as the programming cycle synchronously with the CLK input (TPD after the
is completed. positive edge of CLK).

CS must be low for 250 ns minimum (TCSL) between This pin also provides Ready/Busy status information
consecutive instructions. If CS is low, the internal during erase and write cycles. Ready/Busy status
control logic is held in a RESET status. information is available when CS is high. It will be
displayed until the next Start bit occurs as long as CS
stays high.
4.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi- 4.5 Organization (ORG)
cation between a master device and the 93C76/86.
Opcode, address and data bits are clocked in on the When ORG is connected to VCC, the x16 memory
positive edge of CLK. Data bits are also clocked out on organization is selected. When ORG is tied to VSS, the
the positive edge of CLK. x8 memory organization is selected. There is an
internal pull-up resistor on the ORG pin that will select
CLK can be stopped anywhere in the transmission x16 organization when left unconnected.
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
4.6 Program Enable (PE)
freedom in preparing opcode, address and data. This pin allows the user to enable or disable the ability
CLK is a don't care if CS is low (device deselected). If to write data to the memory array. If the PE pin is
CS is high, but Start condition has not been detected, floated or tied to VCC, the device can be programmed.
any number of clock cycles can be received by the If the PE pin is tied to VSS, programming will be
device without changing its status (i.e., waiting for Start inhibited. There is an internal pull-up on this device that
condition). enables programming if this pin is left floating.
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.

DS21132F-page 10 1996-2012 Microchip Technology Inc.

 93C76/86
5.0 PACKAGING INFORMATION

5.1 Package Marking Information

8-Lead PDIP Example

XXXXXXXX 93C76
XXXXXNNN 017
YYWW 0410

8-Lead SOIC (.150) Example

XXXXXXXX 93C86
XXXXYYWW /SN0410
NNN 017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

1996-2012 Microchip Technology Inc. DS21132F-page 11

93C76/86
8-Lead Plastic Dual In-line (P) 300 mil Body (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging

E1

n 1

A A2

L
c
A1

B1
p
eB B

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top 5 10 15 5 10 15
Mold Draft Angle Bottom 5 10 15 5 10 15
* Controlling Parameter
Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

DS21132F-page 12 1996-2012 Microchip Technology Inc.

 93C76/86
8-Lead Plastic Small Outline (SN) Narrow, 150 mil Body (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging

E1

D
2

B n 1

h
45

c
A A2

L A1

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .050 1.27
Overall Height A .053 .061 .069 1.35 1.55 1.75
Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55
Standoff A1 .004 .007 .010 0.10 0.18 0.25
Overall Width E .228 .237 .244 5.79 6.02 6.20
Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99
Overall Length D .189 .193 .197 4.80 4.90 5.00
Chamfer Distance h .010 .015 .020 0.25 0.38 0.51
Foot Length L .019 .025 .030 0.48 0.62 0.76
Foot Angle 0 4 8 0 4 8
Lead Thickness c .008 .009 .010 0.20 0.23 0.25
Lead Width B .013 .017 .020 0.33 0.42 0.51
Mold Draft Angle Top 0 12 15 0 12 15
Mold Draft Angle Bottom 0 12 15 0 12 15
* Controlling Parameter
Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

1996-2012 Microchip Technology Inc. DS21132F-page 13

93C76/86
APPENDIX A: REVISION HISTORY
Revision E
Added note to page 1 header (Not recommended for
new designs).
Added Section 5.0: Package Marking Information.
Added On-line Support page.
Updated document format.
Revision F
Added a note to each package outline drawing.

DS21132F-page 14 1996-2012 Microchip Technology Inc.

 93C76/86
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To register, access the Microchip web site at
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registration instructions.

1996-2012 Microchip Technology Inc. DS21132F-page 15

93C76/86
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Device: 93C76/86 Literature Number: DS21132F

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

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6. Is there any incorrect or misleading information (what and where)?

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DS21132F-page 16 1996-2012 Microchip Technology Inc.

 93C76/86
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX

Device Temperature Package Pattern

Range

Device 93C76/86: Microwire Serial EEPROM

93C76T/86T: Microwire Serial EEPROM (Tape and Reel)

Temperature Range Blank = 0C to +70C

I = -40C to +85C
E = -40C to +125C

Package P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

1996-2012 Microchip Technology Inc. DS21132F-page 17

93C76/86
NOTES:

DS21132F-page 18 1996-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyers risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
1996-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620767412

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

1996-2012 Microchip Technology Inc. DS21132F-page 19

 Worldwide Sales and Service
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10/26/12
Fax: 86-756-3210049

DS21132F-page 20 1996-2012 Microchip Technology Inc.