24C32A

32K 5.0V I2C Serial EEPROM

FEATURES PACKAGE TYPES

• Voltage operating range: 4.5V to 5.5V PDIP
- Maximum write current 3 mA at 5.5V
- Standby current 1 µA typical at 5.0V A0 1 8 Vcc
• 2-wire serial interface bus, I2C compatible
• 100 kHz and 400 kHz compatibility

24C32A
A1 2 7 WP
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry A2 3 6 SCL
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
Vss 4 5 SDA
• 32-byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
SOIC
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the
same bus for up to 256K bits total memory
A0 1 8 Vcc
• Electrostatic discharge protection > 4000V
• Data retention > 200 years

24C32A
A1 2 7 WP
• 8-pin PDIP and SOIC packages
• Temperature ranges
A2 3 6 SCL
- Commercial (C): 0˚C to 70˚C
- Industrial (I): -40˚C to +85˚C
- Automotive (E): -40˚C to +125˚C Vss 4 5 SDA

DESCRIPTION
The Microchip Technology Inc. 24C32A is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM. It has been BLOCK DIAGRAM
developed for advanced, low power applications such
as personal communications or data acquisition. The A0..A2
WP WP
HV GENERATOR
24C32A also has a page-write capability of up to 32
bytes of data. The 24C32A is capable of both random
and sequential reads up to the 32K boundary. Func-
I/O MEMORY
tional address lines allow up to eight 24C32A devices CONTROL CONTROL XDEC
EEPROM
ARRAY
on the same bus, for up to 256K bits address space. LOGIC LOGIC
Advanced CMOS technology and broad voltage range PAGE LATCHES
make this device ideal for low-power/low-voltage, non-
volatile code and data applications. The 24C32A is I/O
SCL
available in the standard 8-pin plastic DIP and both 150 YDEC
mil and 200 mil SOIC packaging.
SDA

VCC
VSS SENSE AMP
R/W CONTROL

I2C is a trademark of Philips Corporation.

 1996 Microchip Technology Inc. Preliminary DS21163B-page 1

This document was created with FrameMaker 4 0 4

24C32A
1.0 ELECTRICAL TABLE 1-1: PIN FUNCTION TABLE
CHARACTERISTICS Name Function
1.1 Maximum Ratings* A0..A2 User Configurable Chip Selects
VSS Ground
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V SDA Serial Address/Data I/O
Storage temperature ..................................... -65˚C to +150˚C SCL Serial Clock
Ambient temp. with power applied ................ -65˚C to +125˚C WP Write Protect Input
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins ..................................................≥ 4 kV VCC +4.5V to 5.5V Power Supply
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

Vcc = +4.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
Automotive(E): Tamb = -40°C to +125°C
Parameter Symbol Min Typ Max Units Conditions
A0, A1, A2, SCL , SDA and WP
pins:
High level input voltage VIH .7 VCC — V
Low level input voltage VIL — .3 Vcc V
Hysteresis of Schmitt Trigger VHYS .05 — V (Note)
inputs VCC
Low level output voltage VOL — .40 V IOL = 3.0 mA
Input leakage current ILI -10 10 µA VIN = .1V to VCC
Output leakage current ILO -10 10 µA VOUT = .1V to VCC
Pin capacitance CIN, COUT — 10 pF VCC = 5.0V (Note)
(all inputs/outputs) Tamb = 25˚C, Fc = 1 MHz
Operating current ICC Write — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 0.5 mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS — 1 5 µA SCL = SDA = VCC = 5.5V
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS

SCL
THD:STA
TSU:STA TSU:STO
SDA

START STOP

DS21163B-page 2 Preliminary  1996 Microchip Technology Inc.

 24C32A
TABLE 1-3: AC CHARACTERISTICS

Vcc = 4.5-5.5
Parameter Symbol Units Remarks
Min Max
Clock frequency FCLK — 100 kHz
Clock high time THIGH 4000 — ns
Clock low time TLOW 4700 — ns
SDA and SCL rise time TR — 1000 ns (Note 1)
SDA and SCL fall time TF — 300 ns (Note 1)
START condition hold time THD:STA 4000 — ns After this period the first clock
pulse is generated
START condition setup time TSU:STA 4700 — ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0 — ns
Data input setup time TSU:DAT 250 — ns
STOP condition setup time TSU:STO 4000 — ns
Output valid from clock TAA — 3500 ns (Note 2)
Bus free time TBUF 4700 — ns Time the bus must be free before
a new transmission can start
Output fall time from VIH min to TOF — 250 ns (Note 1), CB ≤ 100 pF
VIL max
Input filter spike suppression TSP — 50 ns (Note 3)
(SDA and SCL pins)
Write cycle time TWR — 5 ms
Endurance — 1M — cycles 25°C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TF TR
THIGH
TLOW

SCL
TSU:STA
THD:DAT TSU:DAT TSU:STO
THD:STA
SDA
IN TSP

TAA THD:STA
TAA TBUF

SDA
OUT

 1996 Microchip Technology Inc. Preliminary DS21163B-page 3

24C32A
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24C32A supports a Bi-directional 2-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a START condition, the data line is stable for the
onto the bus is defined as transmitter, and a device duration of the HIGH period of the clock signal.
receiving data as receiver. The bus must be controlled
The data on the line must be changed during the LOW
by a master device which generates the Serial Clock
period of the clock signal. There is one clock pulse per
(SCL), controls the bus access, and generates the
bit of data.
START and STOP conditions, while the 24C32A works
as slave. Both master and slave can operate as trans- Each data transfer is initiated with a START condition
mitter or receiver but the master device determines and terminated with a STOP condition. The number of
which mode is activated. the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined: 3.5 Acknowledge
• Data transfer may be initiated only when the bus is Each receiving device, when addressed, is obliged to
not busy. generate an acknowledge signal after the reception of
• During data transfer, the data line must remain each byte. The master device must generate an extra
stable whenever the clock line is HIGH. Changes clock pulse which is associated with this acknowledge
in the data line while the clock line is HIGH will be bit.
interpreted as a START or STOP condition.
Note: The 24C32A does not generate any
Accordingly, the following bus conditions have been acknowledge bits if an internal program-
defined (Figure 3-1). ming cycle is in progress.

3.1 Bus not Busy (A) A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
Both data and clock lines remain HIGH. that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
3.2 Start Data Transfer (B) setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
A HIGH to LOW transition of the SDA line while the slave by NOT generating an acknowledge bit on the last
clock (SCL) is HIGH determines a START condition. All byte that has been clocked out of the slave. In this case,
commands must be preceded by a START condition. the slave (24C32A) will leave the data line HIGH to
enable the master to generate the STOP condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

DS21163B-page 4 Preliminary  1996 Microchip Technology Inc.

 24C32A
3.6 Device Addressing Following the start condition, the 24C32A monitors the
SDA bus checking the device type identifier being
A control byte is the first byte received following the transmitted. Upon receiving a 1010 code and appropri-
start condition from the master device. The control byte ate device select bits, the slave device outputs an
consists of a 4-bit control code; for the 24C32A this is acknowledge signal on the SDA line. Depending on the
set as 1010 binary for read and write (R/W) operations. state of the R/W bit, the 24C32A will select a read or
The next three bits of the control byte are the device write operation.
select bits (A2, A1, A0). They are used by the master
device to select which of the eight devices are to be Control
Operation Device Select R/W
accessed. These bits are in effect the three most signif- Code
icant bits of the word address. The last bit of the control Read 1010 Device Address 1
byte defines the operation to be performed. When set
Write 1010 Device Address 0
to a one a read operation is selected, and when set to
a zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 3-3). Because only A11...A0 are used, the
upper four address bits must be zeros. The most signif-
icant bit of the most significant byte of the address is
transferred first.
FIGURE 3-2: CONTROL BYTE
ALLOCATION

START READ/WRITE

SLAVE ADDRESS R/W A

1 0 1 0 A2 A1 A0

FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS

CONTROL BYTE ADDRESS BYTE 1 ADDRESS BYTE 0

A A A A A A A A A
1 0 1 0 2 1 0 R/W 0 0 0 0 11 10 9 8 7 • • • • • • 0

SLAVE DEVICE
ADDRESS SELECT
BUS

 1996 Microchip Technology Inc. Preliminary DS21163B-page 5

24C32A
4.0 WRITE OPERATION 4.2 Page Write

4.1 Byte Write The write control byte, word address and the first data
byte are transmitted to the 24C32A in the same way as
Following the start condition from the master, the con- in a byte write. But instead of generating a stop condi-
trol code (four bits), the device select (three bits), and tion, the master transmits up to 32 bytes which are tem-
the R/W bit which is a logic low are clocked onto the bus porarily stored in the on-chip page buffer and will be
by the master transmitter. This indicates to the written into memory after the master has transmitted a
addressed slave receiver that a byte with a word stop condition. After receipt of each word, the five lower
address will follow after it has generated an acknowl- address pointer bits are internally incremented by one.
edge bit during the ninth clock cycle. Therefore, the next If the master should transmit more than 32 bytes prior
byte transmitted by the master is the high-order byte of to generating the stop condition, the address counter
the word address and will be written into the address will roll over and the previously received data will be
pointer of the 24C32A. The next byte is the least signif- overwritten. As with the byte write operation, once the
icant address byte. After receiving another acknowl- stop condition is received, an internal write cycle will
edge signal from the 24C32A the master device will begin. (Figure 4-2).
transmit the data word to be written into the addressed
memory location.
The 24C32A acknowledges again and the master gen-
erates a stop condition. This initiates the internal write
cycle, and during this time the 24C32A will not generate
acknowledge signals (Figure 4-1).

FIGURE 4-1: BYTE WRITE

S
BUS ACTIVITY T S
A CONTROL ADDRESS ADDRESS T
MASTER LOW BYTE DATA
R BYTE HIGH BYTE O
T P
SDA LINE 0 0 0 0

A A A A
BUS ACTIVITY C C C C
K K K K

FIGURE 4-2: PAGE WRITE

S
BUS ACTIVITY T S
MASTER A CONTROL ADDRESS ADDRESS T
R BYTE HIGH BYTE LOW BYTE O
T DATA BYTE 0 DATA BYTE 31 P
SDA LINE 0 0 0 0

A A A A
BUS ACTIVITY C C C C
K K K K

DS21163B-page 6 Preliminary  1996 Microchip Technology Inc.

 24C32A
5.0 ACKNOWLEDGE POLLING 6.0 READ OPERATION
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic types
throughput). Once the stop condition for a write com- of read operations: current address read, random read,
mand has been issued from the master, the device ini- and sequential read.
tiates the internally timed write cycle. Acknowledge
Polling (ACK) can be initiated immediately. This 6.1 Current Address Read
involves the master sending a start condition followed
The 24C32A contains an address counter that main-
by the control byte for a write command (R/W = 0). If the
tains the address of the last word accessed, internally
device is still busy with the write cycle, then NO ACK
incremented by one. Therefore, if the previous access
will be returned. If the cycle is complete, then the device
(either a read or write operation) was to address n (n is
will return the ACK and the master can then proceed
any legal address), the next current address read oper-
with the next read or write command. See Figure 5-1 for
ation would access data from address n + 1. Upon
flow diagram.
receipt of the slave address with R/W bit set to one, the
FIGURE 5-1: ACKNOWLEDGE POLLING 24C32A issues an acknowledge and transmits the eight
FLOW bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
Send 24C32A discontinues transmission (Figure 6-1).
Write Command
6.2 Random Read
Random read operations allow the master to access
Send Stop
Condition to any memory location in a random manner. To perform
Initiate Write Cycle this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C32A as part of a write operation (R/W bit set to
zero). After the word address is sent, the master gener-
Send Start
ates a start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal address pointer is set. Then the master issues the
Send Control Byte control byte again but with the R/W bit set to a one. The
with R/W = 0 24C32A will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24C32A to discontinue transmission
Did Device NO
Acknowledge (Figure 6-2).
(ACK = 0)?
YES

Next
Operation

FIGURE 6-1: CURRENT ADDRESS READ

S
BUS ACTIVITY T S
MASTER A T
R CONTROL BYTE DATA BYTE O
T P

SDA LINE S P

A N
BUS ACTIVITY C O
K
A
C
K

 1996 Microchip Technology Inc. Preliminary DS21163B-page 7

24C32A
6.3 Contiguous Addressing Across 6.4 Sequential Read
Multiple Devices
Sequential reads are initiated in the same way as a ran-
The device select bits A2, A1, A0 can be used to dom read except that after the 24C32A transmits the
expand the contiguous address space for up to 256K first data byte, the master issues an acknowledge as
bits by adding up to eight 24C32A's on the same bus. opposed to the stop condition used in a random read.
In this case, software can use A0 of the control byte as This acknowledge directs the 24C32A to transmit the
address bit A12, A1 as address bit A13, and A2 as next sequentially addressed 8-bit word (Figure 6-3).
address bit A14. Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.
To provide sequential reads the 24C32A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 0FFF to address
000 if the master acknowledges the byte received from
the array address 0FFF.

FIGURE 6-2: RANDOM READ

S S
T T S
BUS ACTIVITY A CONTROL ADDRESS ADDRESS A CONTROL DATA T
MASTER R BYTE HIGH BYTE LOW BYTE R BYTE BYTE O
T T P
SDA LINE 0 0 0 0

A A A A N
BUS ACTIVITY C C C C O
K K K K
A
C
K

FIGURE 6-3: SEQUENTIAL READ

S
BUS ACTIVITY T
MASTER CONTROL DATA n DATA n + 1 DATA n + 2 DATA n + x O
BYTE P

SDA LINE
A A A A N
C C C C O
BUS ACTIVITY K K K K
A
C
K

DS21163B-page 8 Preliminary  1996 Microchip Technology Inc.

 24C32A
7.0 PIN DESCRIPTIONS 8.0 NOISE PROTECTION
The SCL and SDA inputs have filter circuits which sup-
7.1 A0, A1, A2 Chip Address Inputs
press noise spikes to ensure proper device operation
The A0..A2 inputs are used by the 24C32A for multiple even on a noisy bus. All I/O lines incorporate Schmitt
device operation and conform to the 2-wire bus stan- triggers for 400 kHz (Fast Mode) compatibility.
dard. The levels applied to these pins define the 9.0 POWER MANAGEMENT
address block occupied by the device in the address
map. A particular device is selected by transmitting the This design incorporates a power standby mode when
corresponding bits (A2, A1, A0) in the control byte the device is not in use and automatically powers off
(Figure 3-3). after the normal termination of any operation when a
stop bit is received and all internal functions are com-
7.2 SDA Serial Address/Data Input/Output plete. This includes any error conditions, i.e., not receiv-
ing an acknowledge or stop condition per the two-wire
This is a Bi-directional pin used to transfer addresses bus specification. The device also incorporates VDD
and data into and data out of the device. It is an open monitor circuitry to prevent inadvertent writes (data cor-
drain terminal, therefore the SDA bus requires a pullup ruption) during low-voltage conditions. The VDD monitor
resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400 circuitry is powered off when the device is in standby
kHz) mode in order to further reduce power consumption.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.

7.3 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

7.4 WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-FFF).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.

 1996 Microchip Technology Inc. Preliminary DS21163B-page 9

24C32A
NOTES:

DS21163B-page 10 Preliminary  1996 Microchip Technology Inc.

24C32A
24C32A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C32A - /P
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body, EIAJ standard)
SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature Blank = 0°C to +70°C

Range: I = -40°C to +85°C
E = -40°C to +125°C

Device: 24C32A 32K I2C Serial EEPROM (100 kHz, 400 kHz)
24C32AT 32K I2C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. Preliminary DS21163B-page 11

 WORLDWIDE SALES & SERVICE
AMERICAS ASIA/PACIFIC EUROPE
Corporate Office China United Kingdom
Microchip Technology Inc. Microchip Technology Arizona Microchip Technology Ltd.
2355 West Chandler Blvd. Unit 406 of Shanghai Golden Bridge Bldg. Unit 6, The Courtyard
Chandler, AZ 85224-6199 2077 Yan’an Road West, Hongiao District Meadow Bank, Furlong Road
Tel: 602 786-7200 Fax: 602 786-7277 Shanghai, Peoples Republic of China Bourne End, Buckinghamshire SL8 5AJ
Technical Support: 602 786-7627 Tel: 86 21 6275 5700 Tel: 44 1628 850303 Fax: 44 1628 850178
Web: http://www.microchip.com Fax: 011 86 21 6275 5060 France
Atlanta Hong Kong Arizona Microchip Technology SARL
Microchip Technology Inc. Microchip Technology Zone Industrielle de la Bonde
500 Sugar Mill Road, Suite 200B RM 3801B, Tower Two 2 Rue du Buisson aux Fraises
Atlanta, GA 30350 Metroplaza 91300 Massy - France
Tel: 770 640-0034 Fax: 770 640-0307 223 Hing Fong Road Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Boston Kwai Fong, N.T. Hong Kong Germany
Microchip Technology Inc. Tel: 852 2 401 1200 Fax: 852 2 401 3431 Arizona Microchip Technology GmbH
5 Mount Royal Avenue India Gustav-Heinemann-Ring 125
Marlborough, MA 01752 Microchip Technology D-81739 Muenchen, Germany
Tel: 508 480-9990 Fax: 508 480-8575 No. 6, Legacy, Convent Road Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Chicago Bangalore 560 025 India Italy
Microchip Technology Inc. Tel: 91 80 526 3148 Fax: 91 80 559 9840 Arizona Microchip Technology SRL
333 Pierce Road, Suite 180 Korea Centro Direzionale Colleone Pas Taurus 1
Itasca, IL 60143 Microchip Technology Viale Colleoni 1
Tel: 708 285-0071 Fax: 708 285-0075 168-1, Youngbo Bldg. 3 Floor 20041 Agrate Brianza
Dallas Samsung-Dong, Kangnam-Ku, Milan Italy
Microchip Technology Inc. Seoul, Korea Tel: 39 39 6899939 Fax: 39 39 689 9883
14651 Dallas Parkway, Suite 816 Tel: 82 2 554 7200 Fax: 82 2 558 5934
JAPAN
Dallas, TX 75240-8809 Singapore
Microchip Technology Intl. Inc.
Tel: 972 991-7177 Fax: 972 991-8588 Microchip Technology
Benex S-1 6F
Dayton 200 Middle Road
3-18-20, Shin Yokohama
Microchip Technology Inc. #10-03 Prime Centre
Kohoku-Ku, Yokohama
Suite 150 Singapore 188980
Kanagawa 222 Japan
Two Prestige Place Tel: 65 334 8870 Fax: 65 334 8850
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Miamisburg, OH 45342 Taiwan, R.O.C
Tel: 513 291-1654 Fax: 513 291-9175 Microchip Technology 9/3/96
Los Angeles 10F-1C 207
Microchip Technology Inc. Tung Hua North Road
18201 Von Karman, Suite 1090 Taipei, Taiwan, ROC
Irvine, CA 92612 Tel: 886 2 717 7175 Fax: 886 2 545 0139
Tel: 714 263-1888 Fax: 714 263-1338
New York
Microchip Technmgy Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253

All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21163B-page 12 Preliminary  1996 Microchip Technology Inc.