24C01SC/02SC

1K/2K 5.0V I2C Serial EEPROMs for Smart Cards

FEATURES DIE LAYOUT

• ISO Standard 7816 pad locations VSS
• Low power CMOS technology
- 1 mA active current typical
VCC
- 10 µA standby current typical at 5.5V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8) SDA
• Two-wire serial interface bus, I2C compatible
• 100 kHz and 400 kHz compatibility DC
SCL
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write BLOCK DIAGRAM
• ESD protection > 4 kV
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years HV GENERATOR

• Available for extended temperature ranges

- Commercial (C): 0°C to +70°C I/O MEMORY EEPROM
CONTROL CONTROL ARRAY
XDEC
DESCRIPTION LOGIC LOGIC
PAGE LATCHES
The Microchip Technology Inc. 24C01SC and
24C02SC are 1K-bit and 2K-bit Electrically Erasable SDA SCL
PROMs with bondpad positions optimized for smart YDEC

card applications. The devices are organized as a sin-

gle block of 128 x 8-bit or 256 x 8-bit memory with a VCC SENSE AMP
two-wire serial interface. The 24C01SC and 24C02SC VSS R/W CONTROL

also have page-write capability for up to 8 bytes of data.

I2C is a trademark of Philips Corporation.

 1996 Microchip Technology Inc. Preliminary DS21170A-page 1

This document was created with FrameMaker 4 0 4

24C01SC/02SC
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PAD FUNCTION TABLE
Maximum Ratings*
Name Function
VCC ........................................................................ 7.0V
All inputs and outputs w.r.t. VSS...... -0.6V to VCC +1.0V VSS Ground
Storage temperature ...........................-65˚C to +150˚C SDA Serial Address/Data I/O
Ambient temp. with power applied.......-65˚C to +125˚C SCL Serial Clock
ESD protection on all pads .....................................≥ 4 kV
VCC +4.5V to 5.5V Power Supply
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat- DC Don’t connect
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

VCC = +4.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pads:

High level input voltage VIH .7 VCC — —
Low level input voltage VIL — .3 VCC V
Hysteresis of Schmidt trigger inputs VHYS .05 VCC — V (Note)
Low level output voltage VOL — .40 V IOL = 3.0 mA, VCC = 4.5V
Input leakage current (SCL) ILI -10 10 µA VIN = .1V to 5.5V
Output leakage current (SDA) ILO -10 10 µA VOUT = .1V to 5.5V
Pin capacitance (all inputs/outputs) CIN, — 10 pF VCC = 5.0V (Note 1)
COUT Tamb = 25˚C, FCLK = 1 MHz
Operating current ICC Write — 3 mA VCC = 5.5V
ICC Read — 1 mA Vcc = 5.5V, SCL = 400 KHz
Standby current ICCS — 100 µA VCC = 5.5V, SDA = SCL = VCC
Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL
THD:STA
TSU:STA TSU:STO

SDA

START STOP

DS21170A-page 2 Preliminary  1996 Microchip Technology Inc.

 24C01SC/02SC
TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Min. Max. Units Remarks

Clock frequency FCLK — 400 kHz

Clock high time THIGH 600 — ns
Clock low time TLOW 1300 — ns
SDA and SCL rise time TR — 300 ns (Note 1)
SDA and SCL fall time TF — 300 ns (Note 1)
START condition hold time THD:STA 600 — ns After this period the first clock
pulse is generated
START condition setup time TSU:STA 600 — ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 100 — ns
STOP condition setup time TSU:STO 600 — ns
Output valid from clock TAA — 900 ns (Note 2)
Bus free time TBUF 1300 — ns Time the bus must be free
before a new transmission can
start
Output fall time from VIH TOF 20 +0.1 250 ns (Note 1), CB ≤ 100 pF
minimum to VIL maximum CB
Input filter spike suppression TSP — 50 ns (Note 3)
(SDA and SCL pins)
Write cycle time TWR — 10 ms Byte or Page mode
Endurance — 10 6 — cycles 25°C, Vcc = 5V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TF TR
THIGH
TLOW

SCL
TSU:STA
THD:DAT TSU:DAT TSU:STO
THD:STA
SDA
IN TSP

TAA THD:STA
TAA TBUF

SDA
OUT

 1996 Microchip Technology Inc. Preliminary DS21170A-page 3

24C01SC/02SC
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24C01SC/02SC supports a bi-directional two-wire The state of the data line represents valid data when,
bus and data transmission protocol. A device that after a START condition, the data line is stable for the
sends data onto the bus is defined as transmitter, and duration of the HIGH period of the clock signal.
a device receiving data as receiver. The bus has to be
The data on the line must be changed during the LOW
controlled by a master device which generates the
period of the clock signal. There is one clock pulse per
serial clock (SCL), controls the bus access, and gener-
bit of data.
ates the START and STOP conditions, while the
24C01SC/02SC works as slave. Both master and slave Each data transfer is initiated with a START condition
can operate as transmitter or receiver, but the master and terminated with a STOP condition. The number of
device determines which mode is activated. the data bytes transferred between the START and
STOP conditions is determined by the master device
3.0 BUS CHARACTERISTICS and is theoretically unlimited, although only the last 16
The following bus protocol has been defined: will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
• Data transfer may be initiated only when the bus is
out fashion.
not busy.
• During data transfer, the data line must remain 3.5 Acknowledge
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be Each receiving device, when addressed, is obliged to
interpreted as a START or STOP condition. generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
Accordingly, the following bus conditions have been
pulse which is associated with this acknowledge bit.
defined (Figure 3-1).
Note: The 24C01SC/02SC does not generate
3.1 Bus not Busy (A) any acknowledge bits if an internal pro-
gramming cycle is in progress.
Both data and clock lines remain HIGH.
The device that acknowledges has to pull down the
3.2 Start Data Transfer (B) SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
A HIGH to LOW transition of the SDA line while the period of the acknowledge related clock pulse. Of
clock (SCL) is HIGH determines a START condition. All course, setup and hold times must be taken into
commands must be preceded by a START condition. account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
3.3 Stop Data Transfer (C)
byte that has been clocked out of the slave. In this case,
A LOW to HIGH transition of the SDA line while the the slave must leave the data line HIGH to enable the
clock (SCL) is HIGH determines a STOP condition. All master to generate the STOP condition.
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A ) (B) (D) (D) (C) (A)
SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

DS21170A-page 4 Preliminary  1996 Microchip Technology Inc.

 24C01SC/02SC
4.0 BUS CHARACTERISTICS 5.0 WRITE OPERATION
4.1 Slave Address 5.1 Byte Write
After generating a START condition, the bus master Following the start signal from the master, the device
transmits the slave address consisting of a 4-bit device code (4 bits), the don't care bits (3 bits), and the R/W
code (1010) for the 24C01SC/02SC, followed by three bit, which is a logic low, is placed onto the bus by the
don't care bits. master transmitter. This indicates to the addressed
The eighth bit of slave address determines if the master slave receiver that a byte with a word address will follow
device wants to read or write to the 24C01SC/02SC after it has generated an acknowledge bit during the
(Figure 4-1). ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
The 24C01SC/02SC monitors the bus for its corre- into the address pointer of the 24C01SC/02SC. After
sponding slave address all the time. It generates an receiving another acknowledge signal from the
acknowledge bit if the slave address was true, and it is 24C01SC/02SC, the master device will transmit the
not in a programming mode. data word to be written into the addressed memory
location. The 24C01SC/02SC acknowledges again and
Control Chip the master generates a stop condition. This initiates the
Operation R/W
Code Select internal write cycle, and during this time the
Read 1010 XXX 1 24C01SC/02SC will not generate acknowledge signals
Write 1010 XXX 0 (Figure 5-1).

FIGURE 4-1: CONTROL BYTE 5.2 Page Write

ALLOCATION The write control byte, word address, and the first data
START READ/WRITE byte are transmitted to the 24C01SC/02SC in the same
way as in a byte write. But instead of generating a stop
condition, the master transmits up to eight data bytes to
SLAVE ADDRESS R/W A the 24C01SC/02SC, which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi-
tion. After the receipt of each word, the three lower
1 0 1 0 X X X order address pointer bits are internally incremented by
one. The higher order five bits of the word address
X = Don’t care remains constant. If the master should transmit more
than eight words prior to generating the stop condition,
the address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 5-2).

FIGURE 5-1: BYTE WRITE

S
BUS ACTIVITY T CONTROL WORD S
MASTER A BYTE ADDRESS DATA T
R O
T P

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

FIGURE 5-2: PAGE WRITE

BUS ACTIVITY S
T CONTROL S
MASTER A WORD
BYTE ADDRESS (n) T
R DATA n DATAn + 1 DATAn + 7 O
T P
SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

 1996 Microchip Technology Inc. Preliminary DS21170A-page 5

24C01SC/02SC
6.0 ACKNOWLEDGE POLLING 7.0 READ OPERATION
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic types
throughput). Once the stop condition for a write com- of read operations: current address read, random read,
mand has been issued from the master, the device ini- and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send- 7.1 Current Address Read
ing a start condition followed by the control byte for a
The 24C01SC/02SC contains an address counter that
write command (R/W = 0). If the device is still busy with
maintains the address of the last word accessed, inter-
the write cycle, then NO ACK will be returned. If the
nally incremented by one. Therefore, if the previous
cycle is complete, then the device will return the ACK,
access (either a read or write operation) was to address
and the master can then proceed with the next read or
n, the next current address read operation would
write command. See Figure 6-1 for flow diagram.
access data from address n + 1. Upon receipt of the
FIGURE 6-1: ACKNOWLEDGE POLLING slave address with R/W bit set to one, the
FLOW 24C01SC/02SC issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
Send 24C01SC/02SC discontinues transmission
Write Command (Figure 8-2).

7.2 Random Read

Send Stop
Random read operations allow the master to access
Condition to
Initiate Write Cycle any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01SC/02SC as part of a write operation. After the
Send Start word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then, the master issues the control byte
Send Control Byte again but with the R/W bit set to a one. The
with R/W = 0 24C01SC/02SC will then issue an acknowledge and
transmits the 8-bit data word. The master will not
acknowledge the transfer but does generate a stop con-
dition and the 24C01SC/02SC discontinues transmis-
Did Device NO
Acknowledge sion (Figure 8-3).
(ACK = 0)?
7.3 Sequential Read
YES
Sequential reads are initiated in the same way as a ran-
Next dom read except that after the 24C01SC/02SC trans-
Operation mits the first data byte, the master issues an
acknowledge as opposed to a stop condition in a ran-
dom read. This directs the 24C01SC/02SC to transmit
the next sequentially addressed 8-bit word (Figure 9-1).
To provide sequential reads the 24C01SC/02SC con-
tains an internal address pointer which is incremented
by one at the completion of each operation. This
address pointer allows the entire memory contents to
be serially read during one operation.

DS21170A-page 6 Preliminary  1996 Microchip Technology Inc.

 24C01SC/02SC
7.4 Noise Protection
The 24C01SC/02SC employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

S
BUS ACTIVITY T S
A CONTROL T
MASTER R BYTE DATA n O
T P

SDA LINE
S P

BUS ACTIVITY A N
C O
K
A
C
K

FIGURE 7-2: RANDOM READ

S S
T T S
BUS ACTIVITY A CONTROL WORD A CONTROL T
MASTER R BYTE ADDRESS (n) R BYTE DATA n O
T T P

SDA LINE S S P
A A A N
BUS ACTIVITY C C C O
K K K
A
C
K

FIGURE 7-3: SEQUENTIAL READ

S
A A A T
BUS ACTIVITY CONTROL C C C O
MASTER BYTE K K K P
SDA LINE P
A N
BUS ACTIVITY C DATA n DATA n + 1 DATA n + 2 DATA n + X O
K
A
C
K

 1996 Microchip Technology Inc. Preliminary DS21170A-page 7

24C01SC/02SC
8.0 PAD DESCRIPTIONS 9.0 DIE CHARACTERISTICS
Figure 9-1 shows the die layout of the 24C01SC/02SC,
8.1 SDA Serial Address/Data Input/Output
including bondpad positions. Table 9-1 shows the
This is a bi-directional pad used to transfer addresses actual coordinates of the bondpad midpoints with
and data into and data out of the device. It is an open respect to the center of the die.
drain terminal, therefore the SDA bus requires a pull-up
FIGURE 9-1: DIE LAYOUT
resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400
kHz). DIP
For normal data transfer SDA is allowed to change only VSS
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions. VCC

8.2 SCL Serial Clock

SDA
This input is used to synchronize the data transfer from
and to the device. DC
SCL
8.3 DC Don’t Connect
TABLE 9-1: BONDPAD COORDINATES
This pad is used for test purposes and should not be
bonded out. It will be pulled to VSS through an internal Pad Midpoint, Pad Midpoint,
resistor. Pad Name
X dir. Y dir.
VSS -495.000 749.130
SDA -605.875 -271.875
SCL 479.875 -746.625
VCC 605.875 -261.375
Note 1: Dimensions are in microns.
2: Center of die is at the 0,0 point.

DS21170A-page 8 Preliminary  1996 Microchip Technology Inc.

 24C01SC/02SC
NOTES:

 1996 Microchip Technology Inc. Preliminary DS21170A-page 9

24C01SC/02SC
NOTES:

DS21170A-page 10 Preliminary  1996 Microchip Technology Inc.

24C01SC/02SC
24C01SC/02SC Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C01SC/02SC — /S XX
Die Thickness Blank = 11 mils
08 = 8 mils
Other die thicknesses available, please
consult factory.

Package: S = Die in Wafer Pak

W = Wafer
WF = Sawed Wafer on Frame

Temperature Blank = 0°C to +70°C

Range:

Device: 24C01SC 1K 12C ISO Smart Card die

24C02SC 2K 12C ISO Smart Card die

 1996 Microchip Technology Inc. Preliminary DS21170A-page 11

 WORLDWIDE SALES & SERVICE
AMERICAS AMERICAS (continued) EUROPE
Corporate Office New York United Kingdom
Microchip Technology Inc. Microchip Technology Inc. Arizona Microchip Technology Ltd.
2355 West Chandler Blvd. 150 Motor Parkway, Suite 416 Unit 6, The Courtyard
Chandler, AZ 85224-6199 Hauppauge, NY 11788 Meadow Bank, Furlong Road
Tel: 602 786-7200 Fax: 602 786-7277 Tel: 516 273-5305 Fax: 516 273-5335 Bourne End, Buckinghamshire SL8 5AJ
Technical Support: 602 786-7627 San Jose Tel: 44 1 628 850303 Fax: 44 1 628 850178
Web: http://www.microchip.com/ Microchip Technology Inc.
France
2107 North First Street, Suite 590
Atlanta Arizona Microchip Technology SARL
San Jose, CA 95131
Microchip Technology Inc. Tel: 408 436-7950 Fax: 408 436-7955 Zone Industrielle de la Bonde
500 Sugar Mill Road, Suite 200B 2 Rue du Buisson aux Fraises
Atlanta, GA 30350 Toronto 91300 Massy - France
Tel: 770 640-0034 Fax: 770 640-0307 Microchip Technology Inc. Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
5925 Airport Road, Suite 200
Boston Mississauga, Ontario L4V 1W1, Canada Germany
Microchip Technology Inc. Tel: 905 405-6279 Fax: 905 405-6253 Arizona Microchip Technology GmbH
5 Mount Royal Avenue Gustav-Heinemann-Ring 125
Marlborough, MA 01752 ASIA/PACIFIC D-81739 Muenchen, Germany
Tel: 508 480-9990 Fax: 508 480-8575 Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Hong Kong
Chicago Italy
Microchip Technology
Microchip Technology Inc. Rm 3801B, Tower Two Arizona Microchip Technology SRL
333 Pierce Road, Suite 180 Metroplaza, Centro Direzionale Colleoni
Itasca, IL 60143 223 Hing Fong Road, Palazzo Taurus 1 V. Le Colleoni 1
Tel: 708 285-0071 Fax: 708 285-0075 Kwai Fong, N.T., Hong Kong 20041, Agrate Brianza, Milan Italy
Dallas Tel: 852 2 401 1200 Fax: 852 2 401 3431 Tel: 39 39 689 9939 Fax: 39 39 689 9883
Microchip Technology Inc. Korea
14651 Dallas Parkway, Suite 816
JAPAN
Microchip Technology Microchip Technology Intl. Inc.
Dallas, TX 75240-8809 168-1, Youngbo Bldg. 3 Floor
Tel: 214 991-7177 Fax: 214 991-8588 Benex S-1 6F
Samsung-Dong, Kangnam-Ku, 3-18-20, Shin Yokohama
Dayton Seoul, Korea Kohoku-Ku, Yokohama
Microchip Technology Inc. Tel: 82 2 554 7200 Fax: 82 2 558 5934 Kanagawa 222 Japan
Suite 150 Singapore Tel: 81 45 471 6166 Fax: 81 45 471 6122
Two Prestige Place Microchip Technology
Miamisburg, OH 45342 200 Middle Road 5/10/96
Tel: 513 291-1654 Fax: 513 291-9175 #10-03 Prime Centre
Los Angeles Singapore 188980
Microchip Technology Inc. Tel: 65 334 8870 Fax: 65 334 8850
18201 Von Karman, Suite 1090
Taiwan
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338 Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139

All rights reserved.  1996, Microchip Technology Incorporated, USA. 5/96

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21170A-page 12 Preliminary  1996 Microchip Technology Inc.