MICROPROCESSOR

IBB20204
LECTURE 2
Learning outcomes:
At the end of the lecture, students should be able to:

1. Identify the macro & micro architecture of

microprocessor.
2. Understand how the microprocessor and its
memory and input/output subsystems operate
from a software point of view.
3. Examine the software architecture of the 8086
microprocessor.
 Introduction
 Before we go to the MICROARCHITECTURE of the
microprocessor, let us see in general the architecture of the
microprocessor itself.
 Recall: Microprocessor is connected EXTERNALLY with the
memory & I/O ports by a system Bus.
 Architecture of Microprocessor
 Microprocessor consists of ALU, Register Array & Control.
 Architecture of Microprocessor
 ALU – Arithmetic Logic Unit

 A combinational network that performs arithmetic and logical

operations on the data.
 Ex: Addition, subtraction, shift, rotate
 Ex: XOR, OR, AND, NOT
 Architecture of Microprocessor
 Register

 A register is just like a memory location - it stores data (bits).

 It is typically composed of an array of flip-flops. A 1-bit
register can store 1 bit, and a 32-bit register can hold 32 bits,
etc.
 Because they are part of the CPU itself, access to them is
extremely fast - values stored in registers don’t need to be
fetched, they are right there.
 Registers are used to store temporary data that the CPU
needs, for example the operands and result of a calculation, or
the address in external memory where data can be found.
 Architecture of Microprocessor
 Register = Memory?  NO!

 Even though the same operations can be done using RAM,

registers in a microprocessor are utilized in order to boost
performance. Registers, although adding cost and complexity,
are very much faster than RAM. Its a balance between
performance and cost.
 Register plays a major role in CPU operations. Microprocessor
picks up data from one of the registers for doing arithmetic or
logical operation. Once the operation is over, it stores the
result in a register. Data are usually loaded from memory to
register. Similarly the resultant data will be loaded from
registers to memory.
 Architecture of Microprocessor
 There are 2 types of register for 8086:
1. General purpose data registers
2. Special purpose registers

 Physically, one register is much the same as another, but in

most CPUs, they are organised for specific purposes, and are
given special names so that a programmer who writes code
for the CPU directly (in assembler, for example, or a compiler
writer) can refer to them.
 Architecture of Microprocessor
1. General purpose data registers:
1.1 Ax-Accumulator register
1.2 Bx-Base Address register
1.3 Cx-Count register
1.4 Dx-Data register
2. Special purpose registers:
2.1 Pointer registers ( instruction pointer-IP, stack pointer-SP,
base pointer-BP)
2.2 Segment Registers ( code segment-CS, stack segment-SS, data
segment-DS, extra segment-ES)
2.3 Index registers (source index-SI, destination index-DI)
2.4 Flag or status registers:
a) Control flags-CR (directional flag, interrupt flag, track flag)
b) Status flags-SR (over flow flag, sign flag, zero flag, auxiliary
flag, parity flag, carry flag and future flag)
 Architecture of Microprocessor
 Control unit

 A control unit (CU) handles all processor control signals. It

directs all input and output flow, fetches code for instructions
from microprograms and directs other units and models by
providing control and timing signals. A CU component is
considered the processor brain because it issues orders to just
about everything and ensures correct instruction execution.
 Functions:
1. To generate control/timing signals
2. To control the decoding/execution of instructions
 Micro architecture of the 8088 and 8086
Microprocessors
 The micro architecture of a processor is its internal architecture - that is,
the circuit building blocks that implement the software and hardware
architectures of the 8088/8086 microprocessors.
 Due to the need for additional features and higher performance, the
micro architecture of a microprocessor family evolves over time.
 Each new generation of processors (the 8088/8086, 80286, 80386,
80486 and Pentium processors) represents significant changes in the
micro architecture of the 8086
 The micro architectures of 8088 and 8086 microprocessors are similar.
They both employ parallel processing – that is they both are implemented
with several simultaneously operating processing unit.
 Micro architecture of the 8088 and 8086
Microprocessors
 They contain two processing units:
 the bus interface unit (BIU) and
 the execution unit (EU).

 Figure below illustrates the internal architecture of 8088 and 8086

microprocessors.

 Data transfer takes place over the system bus. System bus includes an
16-bit bidirectional data bus for the 8086 (8 bits for the 8088), a 20-bit
address bus, and the signals need to control transfers over the bus.
Micro architecture of the 8088 and 8086
Microprocessors
 Figure below shows the architecture of the two processing units – BIU
& EU.
 Each unit has dedicated functions and both operate at the same time.
 Bus Interface Unit
• The BIU connects the microprocessor to external devices.

• Components in BIU:
1) Segment Register
2) Instruction Pointer
3) Address Generation Adder
4) Bus Control Logic
5) Instruction Queue

• BIU performs following operations:

1) Instruction fetching
2) Reading and writing data of data operands for memory
3) Inputting/outputting data for input/output peripherals.
4) And other functions related to instruction and data acquisition.
 Bus Interface Unit
 The BIU uses a mechanism known as an instruction queue to implement
pipelined architecture.
 This queue permits the 8086 to pre-fetch up to 6 bytes (4 bytes for
8088) of instruction code.
 Figure below shows the bus interface unit of the 8088/8086 in more
detail.
 Execution Unit
 The execution unit (EU) is responsible for decoding and executing
instructions.

 The EU performs the arithmetic, logic, and shift operations required

by an instruction.

 The EU consists of:

1) arithmetic logic unit (ALU),
2) status and control flags,
3) general-purpose registers, and
4) temporary-operand registers
 Execution Unit
• The figure shows the execution unit
of the 8088/8086 in more detail.
• The EU accesses instructions from
the output end of the instruction
queue and data from the general-
purpose registers or memory.
• It reads one instruction byte after the
other from the output of the queue,
decodes them, generates data
addresses if necessary, passes them to
the BIU and requests it to perform
the read or write operations to
memory or I/O, and performs the
operation specified by the
instruction.
 Execution Unit
 The ALU performs the arithmetic, logic and shift operations required
by an instruction.

 During execution of the instruction, the EU may test the status and
control flags, and updates these flags based on the results of executing
the instruction.

 If the queue is empty, the EU waits for the nest instruction byte to be
fetched and shifted to the top of the queue.
 PIPELINE ARCHITECTURE
 Based on the following internal architecture:
 The EU receives instruction codes and data from the BIU.
 Then it decodes and executes these instructions, and stores
the results in the general registers/memory or status flags.
 By passing the data back to the BIU, data can also be stored in
a memory location or written to an output device.
 The organization of the processor into a separate BIU and EU
allows the fetch and execute cycles to be done in
parallel.
 PIPELINE ARCHITECTURE
 Recall: BIU uses a mechanism known as an instruction queue to
implement pipelined architecture.

 The BIU is programmed to fetch a new instruction whenever the

instruction queue has room for two additional bytes.

 The instruction queue mechanism allows pipelined architecture

so that the EU can execute instructions at the same time when
the BIU fetch next instruction instead of waiting (idle) for the
BIU to fetch a new instruction.
 FETCH-EXECUTE CYCLE
 The processor executes instructions one-by-one according to the
sequence found in memory.
 Everything is controlled by, what else, the control unit in the
processor.
 To execute an instruction, the processor must fetch it from the
memory.
 The complete steps that the processor takes to execute one
instruction is known as the instruction cycle or fetch-execute cycle.
The instruction is fetched from
memory; decoded within the 8086;
operands are read from memory or
internal registers; the operation
specified by the instruction is
performed on the data; and results are
written back to either memory or an
internal register.
 INSTRUCTION CYCLE
 On program start:
0) Load the program counter (PC) with the address of the first
instruction.
 Fetch phase:
1) Read the instruction and put it into the instruction register (IR).
2) Control unit then decodes the instruction, updates the PC
for the next instruction.
 Execute phase:
3) Find the data required by the instruction.
4) Perform the required operation.
5) Store the results.
6) Repeat from Step 1.
 INSTRUCTION SEQUENCING
 Example: An instruction to add the contents (4 and 5) of two
registers/locations (A and B) and place the result in third
register (C).
 Before you do anything, make sure to set PC to point to the 1st
instruction in the sequence.
 INSTRUCTION SEQUENCING
 Next sequence:
 INSTRUCTION SEQUENCING
 Next sequence:
 INSTRUCTION SEQUENCING
 Next sequence:
 SOFTWARE MODEL OF 8086
 Purpose of developing software model?

 To help the programmer in understanding the operation of the

microprocessor system from a software perspective, example:
1. To know the purpose, its functions, operating capabilities,
limitations, etc.
2. To know how external memory and I/O peripherals are
organized.
3. To know how information is arranged in registers,
memory, and I/O.
4. To know how I/O are addressed to obtain instructions
and data.
 SOFTWARE MODEL OF 8086
 Software architecture of the 8088/86 microprocessor
Independent Memory

Internal Register

I/O Address Space

 SOFTWARE MODEL OF 8086
 From the architecture, we notice that:
 It includes 13 16-bit internal registers:
 1 Instruction Pointer (IP)
 4 accumulator data registers (AX, BX, CX, DX)
 2 pointer registers (BP, SP)
 2 index registers (SI, DI)
 4 segment registers (CS, DS, SS, ES)
 In addition 1 status register (SR) – with nine of its bits
implemented as status and control flags.
 It implements independent memory where the memory address space
is 1Mbyte (0000016 – FFFFF16)
 It also consists a separate I/O address space of 64Kbytes (000016 –
FFFF16) in length.
 INTERNAL REGISTERS
 There are 13 of 16-bit internal registers
MEMORY ADDRESS SPACE & DATA ORGANIZATION
 How information such as numbers, characters, and instructions is
stored in memory?
 The 8088/86 supports 1Mbyte of external memory.
 This memory space is organized as individual bytes of data stored
at consecutive addresses over the address range 0000016 – FFFFF16

• Figure shows the memory address

space of the 8088/86
microprocessor.
• Memory in 8088/86 is actually
organized as 8-bit bytes.
• It can also access any 2 consecutive
bytes as a word of data.
MEMORY ADDRESS SPACE & DATA ORGANIZATION
 Recall: Byte = 8-bit and Word = 16-bit = 2 consecutive bytes.
 Figure below shows how a word of data is stored in memory.
 The storage location at the lower address, 0072416 contains the
value 000000102 = 0216.
 The contents of the next-higher-addressed storage location,
0072516 are 010101012 = 5516.
 These two bytes represent the word of 01010101000000102=550216.
MEMORY ADDRESS SPACE & DATA ORGANIZATION
 Words of data can be stored at what are called even-addressed or odd-
addressed word boundaries.
 The LSByte of the address determines the type of word boundary.

 If LSB is 0  word is at even-addressed boundary.

LSB=0
 If LSB is 1  word is at odd-addressed boundary.

 Example:The LSByte of the word 01010101000000102=550216 is

Least significant byte
located at the address of 0072416. Expressing this
address in binary gives 0072416 = 000000000111001001002.

 Therefore the word 550216 is stored at even-addressed boundary.

MEMORY ADDRESS SPACE & DATA ORGANIZATION

 A word of data stored at an even-addressed boundary, such as

0000016, 0000216, 0000416 is said to be an aligned word.

 All aligned words are located at an address that is multiple of 2.

 A word of data stored at an odd-addressed boundary, such as

0000116, 0000316, 0000516 is said called a misaligned word.

 As for example just now, the word 550216 is an aligned word.

MEMORY ADDRESS SPACE & DATA ORGANIZATION
 Example: What is the data word shown in figure below? Express
the result in hexadecimal form. Is it stored at an even- or odd-
addressed word boundary? Is it an aligned or misaligned word of
data?
MEMORY ADDRESS SPACE & DATA ORGANIZATION
 Solution:

 The MSByte of the word is stored at address 0072C16 and it equals to

111111012 = FD16 = FDH.

 The LSByte of the word is stored at address 0072B16 and it equals to

101010102 = AA16 = AAH.

 The two bytes give the word of 11111101101010102 = FDAA16

 Expressing the address of the LSByte in binary form:

 0072BH = 0072B16 = 000000000111001010112.

 LSB is 1, therefore the word is stored at an odd-addresses word

boundary in memory.
 It is a misaligned word of data.
 MEMORY ADDRESS SPACE
 Recall: 8088/86 microprocessor has a 1MByte memory address
space  not all this memory is active at one time!

• Main memory management in

8086 use segment concept.
• The 1MBytes of memory are
partitioned into 64KByte
segments.
• A segment represents an
independently addressable unit of
memory consisting of 64K
consecutive byte-wide storage
locations.
SEGMENT REGISTERS & MEMORY SEGMENTATION
 Each segment is assigned a base address that identifies its starting
point-that is, its lowest address byte-storage location.

 Only four segments can be active at a time:

 The code segment (CS)
 The stack segment (SS)
 The data segment (DS)
 The extra segment (ES)

 The following table shows the usage of segment in memory.

Segment Usage
Code (CS) Space to store instruction codes
Data (DS) Space to store program data
Stack (SS) Space to store temporary information
Extra (ES) Space to store program data
SEGMENT REGISTERS & MEMORY SEGMENTATION
 The active segments of memory are identified by the value of
addresses held in four internal segment registers-CS, SS,DS, and ES.
 The values held in these registers are referred to as the current-segment
register values; for example, the value in CS points to the first word-
wide storage location in the current code segment.
SEGMENT REGISTERS & MEMORY SEGMENTATION

• Figure shows the memory

segmentation.
• Each segments are identified
with letters A, B, C, and D.
• Ex: Data segment register (DS)
contain the value B.
• Therefore, the 2nd segment of
memory from the top, labelled
B, acts as the current data-
storage segment. (Refer to table
usage of each segment register
on slide 38)
 INPUT/OUTPUT ADDRESS SPACE
 The 8086 has a separate memory address space and I/O address
space.
 The I/O address space is the place where I/O interfaces, such as
printer and terminal ports, are implemented.
 The I/O address range is from 000016 to FFFF16.
 This represents 64KByte addresses.
 INPUT/OUTPUT ADDRESS SPACE
 The I/O addresses are only 16-bit long.
 Each of these addresses corresponds to one byte-wide I/O port.

 Part of the map from address 000016 thru 00FF16 is referred to

as page 0.
 Certain I/O instructions can only perform operations to I/O
devices located in this part (page 0).
 While other I/O instructions can be performed to I/O devices
located anywhere in the I/O address space.
 I/O data transfers can be byte-wide or word-wide.

 Note that the eight locations from address 00F816 through

00FF16 are specified as reserved by Intel Corp. and should not be
used.
 REVIEW QUESTIONS
1) Name the two internal processing units of the 8088/86.
2) What are the length of the 8086’s address bus and data bus?
3) List the elements of the execution unit (EU).
4) What must an assembly-language programmer know about the
registers within the 8088/86 microprocessor?
5) How large is the 8088/86’s memory address space?
6) What is the highest address in the 8088/86’s memory address space?
The lowest address?
7) The contents of the memory location B000016 are FF16 and those at
B000116 are 0016. What is the data word stored at address B0000? Is
the word aligned or misaligned?
8) Show how the word ABCD16 is stored in memory address space
starting at address 0A00216. Is the word aligned or misaligned?
 REVIEW QUESTIONS
9) How large is memory segment in the 8088/86 microprocessor?
10) Provide an overview of the fetch and the execution of an instruction
by the 8086.
11) List out the general purpose data registers of the 8086.
12) What do SI and DI stand for?
13) For the 8086 microprocessor, are the I/O and memory address
spaces common or separate?
14) What name is given to the part of the I/O address space from
000016 through 00FF16?
 ANSWER
1) Bus Interface Unit & Execution Unit
2) Address bus-20 bits, Data bus-16 bits
3) General purpose registers, temporary operand registers, ALU
& status and control flags.
4) Its purpose, function, operating capabilities and limitations.
5) 1 Mbytes = 1,048,576
6) FFFFF16 and 0000016
7) 00FF16  Aligned word
8) Address Contents
0A003H CDH
0A004H ABH Aligned word
 ANSWER
9) 64Kbytes
10) The instruction is fetched from memory; decoded within the
8086; operands are read from memory or internal registers;
the operation specified by the instruction is performed on the
data; and results are written back to either memory or an
internal register.
11) Accumulator register (AX), Base register (BX), Count Register
(CX), Data Register (DX)
12) Source Index register, Destination Index register
13) Separate
14) Page 0
Thank You