11AA02UID

2K UNI/O® Serial EEPROM with Unique 32-Bit Serial Number

DEVICE SELECTION TABLE

Density Page Size Temp. Unique ID
Part Number VCC Range Packages
(bits) (Bytes) Ranges Length
11AA02UID 2K 1.8-5.5V 16 I SN, TT 32-Bit

Features: Description:
• Preprogrammed 32-Bit Serial Number: The Microchip Technology Inc. 11AA02UID device is a
- Unique across all UID-family EEPROMs 2 Kbit Serial Electrically Erasable PROM with a
- Scalable to 48-bit, 64-bit, 128-bit, 256-bit, preprogrammed, 32-bit unique ID. The device is
and other lengths organized in blocks of x8-bit memory and support the
patented* single I/O UNI/O® serial bus. By using
• Single I/O, UNI/O® Serial Interface Bus
Manchester encoding techniques, the clock and data
• Low-Power CMOS Technology: are combined into a single, serial bit stream (SCIO),
- 1 mA active current, typical where the clock signal is extracted by the receiver to
- 1 µA standby current (max.) correctly decode the timing and value of each bit.
• 256 x 8 Bit Organization Low-voltage design permits operation down to 1.8V,
• Schmitt Trigger Inputs for Noise Suppression with standby and active currents of only 1 uA and 1 mA,
• Output Slope Control to Eliminate Ground Bounce respectively.
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz The 11AA02UID is available in standard 8-lead SOIC
Clock Frequency and 3-lead SOT-23 packages.
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes Package Types (not to scale)
• STATUS Register for Added Control: SOIC
SOT23
- Write enable latch bit (TT) (SN)
- Write-In-Progress bit
2 VCC NC 1 8 VCC
• Block Write Protection: NC 2 7 NC
VSS 3
- Protect none, 1/4, 1/2 or all of array NC 3 6 NC
1 SCIO VSS 4 SCIO
• Built-in Write Protection: 5
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability: Pin Function Table
- Endurance: 1,000,000 erase/write cycles Name Function
- Data retention: > 200 years
SCIO Serial Clock, Data Input/Output
- ESD protection: > 4,000V
VSS Ground
• 3-Lead SOT-23 and 8-Lead SOIC Packages
VCC Supply Voltage
• RoHS Compliant
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C

* Microchip’s UNI/O® Bus products are covered by the following patents issued in the U.S.A.: 7,376,020 and 7,788,430.

 2013 Microchip Technology Inc. DS20005206A-page 1

11AA02UID
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
SCIO w.r.t. VSS .................................................................................................................................... -0.6V to VCC+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias .................................................................................................................-40°C to 85°C
ESD protection on all pins ..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

Electrical Characteristics:
DC CHARACTERISTICS Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
D1 VIH High-level Input 0.7*VCC VCC+1 V
Voltage
D2 VIL Low-level Input -0.3 0.3*VCC V VCC2.5V
Voltage -0.3 0.2*VCC V VCC < 2.5V
D3 VHYS Hysteresis of Schmitt 0.05*Vcc — V VCC2.5V (Note 1)
Trigger inputs (SCIO)
D4 VOH High-level Output VCC -0.5 — V IOH = -300 A, VCC = 5.5V
Voltage VCC -0.5 — V IOH = -200 A, Vcc = 2.5V
D5 VOL Low-level Output — 0.4 V IOI = 300 A, VCC = 5.5V
Voltage — 0.4 V IOI = 200 A, Vcc = 2.5V
D6 IO Output Current Limit — ±4 mA VCC = 5.5V (Note 1)
(Note 2) — ±3 mA Vcc = 2.5V (Note 1)
D7 ILI Input Leakage — ±1 A VIN = VSS or VCC
Current (SCIO)
D8 CINT Internal Capacitance — 7 pF TA = 25°C, FCLK = 1 MHz,
(all inputs and VCC = 5.0V (Note 1)
outputs)
D9 ICC Read Read Operating — 3 mA VCC=5.5V, FBUS=100 kHz, CB=100 pF
Current — 1 mA VCC=2.5V, FBUS=100 kHz, CB=100 pF
D10 ICC Write Write Operating — 5 mA VCC = 5.5V
Current — 3 mA VCC = 2.5V
D11 Iccs Standby Current — 1 A VCC = 5.5V, TA = 85°C
D12 ICCI Idle Mode Current — 50 A VCC = 5.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: The SCIO output driver impedance will vary to ensure IO is not exceeded.

DS20005206A-page 2  2013 Microchip Technology Inc.

 11AA02UID

TABLE 1-2: AC CHARACTERISTICS

Electrical Characteristics:
AC CHARACTERISTICS Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
1 FBUS Serial Bus Frequency 10 100 kHz —
2 TE Bit Period 10 100 µs —
3 TIJIT Input Edge Jitter — ±0.06 UI (Note 3)
Tolerance
4 FDRIFT Serial Bus Frequency — ±0.50 % per byte —
Drift Rate Tolerance
5 FDEV Serial Bus Frequency — ±5 % per —
Drift Limit command
6 TOJIT Output Edge Jitter — ±0.25 UI (Note 3)
7 TR SCIO Input Rise Time — 100 ns —
(Note 1)
8 TF SCIO Input Fall Time — 100 ns —
(Note 1)
9 TSTBY Standby Pulse Time 600 — µs —
10 TSS Start Header Setup Time 10 — µs —
11 THDR Start Header Low Pulse 5 — µs —
Time
12 TSP Input Filter Spike — 50 ns (Note 1)
Suppression (SCIO)
13 TWC Write Cycle Time — 5 ms Write, WRSR commands
(byte or page) — 10 ms ERAL, SETAL commands
14 — Endurance (per page) 1M — cycles 25°C, VCC = 5.5V (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at
www.microchip.com.
3: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.

TABLE 1-3: AC TEST CONDITIONS

AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
CL = 100 pF
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC

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11AA02UID
FIGURE 1-1: BUS TIMING – START HEADER

10 11 2

SCIO

Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit

FIGURE 1-2: BUS TIMING – DATA

2 7 8

12
SCIO

Data ‘0’ Data ‘1’ Data ‘1’ Data ‘0’

FIGURE 1-3: BUS TIMING – STANDBY PULSE

9
SCIO

Standby
Mode

FIGURE 1-4: BUS TIMING – JITTER

2 2
3 3 6 6 6 6

Ideal Edge Ideal Edge Ideal Edge Ideal Edge

from Master from Master from Slave from Slave

DS20005206A-page 4  2013 Microchip Technology Inc.

 11AA02UID
2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 11AA02UID family of serial EEPROMs support
the UNI/O® protocol. They can be interfaced with
microcontrollers, including Microchip’s PIC® microcon-
trollers, ASICs, or any other device with an available
discrete I/O line that can be configured properly to
match the UNI/O protocol.
The 11AA02UID devices contain an 8-bit instruction
register. The devices are accessed via the SCIO pin.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a
master device which determines the clock period, con-
trols the bus access and initiates all operations, while
the 11AA02UID works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is active.

FIGURE 2-1: BLOCK DIAGRAM

STATUS
HV Generator
Register

EEPROM
I/O Control Memory X
Control Array
Logic
Logic Dec

Page Latches
Current-
Limited
Slope
Control
Y Decoder
SCIO

Sense Amp.
VCC R/W Control
VSS

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11AA02UID
3.0 BUS CHARACTERISTICS If a command is terminated in any manner other than a
NoMAK/SAK combination, then the master must
3.1 Standby Pulse perform a standby pulse before beginning a new
command, regardless of which device is to be selected.
When the master has control of SCIO, a standby pulse
can be generated by holding SCIO high for TSTBY. At Note: After a POR/BOR event occurs, a low-to-
this time, the 11AA02UID will reset and return to high transition on SCIO must be gener-
Standby mode. Subsequently, a high-to-low transition ated before proceeding with communica-
on SCIO (the first low pulse of the header) will return tion, including a standby pulse.
the device to the active state. An example of two consecutive commands is shown in
Once a command is terminated satisfactorily (i.e., via Figure 3-1. Note that the device address is the same
a NoMAK/SAK combination during the Acknowledge for both commands, indicating that the same device is
sequence), performing a standby pulse is not required being selected both times.
to begin a new command as long as the device to be A standby pulse cannot be generated while the slave
selected is the same device selected during the previ- has control of SCIO. In this situation, the master must
ous command. However, a period of TSS must be wait for the slave to finish transmitting and to release
observed after the end of the command and before the SCIO before the pulse can be generated.
beginning of the start header. After TSS, the start
header (including THDR low pulse) can be transmitted If, at any point during a command an error is detected
in order to begin the new command. by the master, a standby pulse should be generated
and the command should be performed again.

FIGURE 3-1: CONSECUTIVE COMMANDS EXAMPLE

NoSAK
MAK

MAK
SAK
Standby Pulse(1) Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
NoMAK

NoSAK
SAK

MAK

MAK
SAK
TSS

Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0

Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.

3.2 Start Data Transfer When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
All operations must be preceded by a start header. The TSS must be observed after the end of the command
start header consists of holding SCIO low for a period and before the beginning of the start header.
of THDR, followed by transmitting an 8-bit ‘01010101’
code. This code is used to synchronize the slave’s Figure 3-2 shows the waveform for the start header,
internal clock period with the master’s clock period, so including the required Acknowledge sequence at the
accurate timing is very important. end of the byte.

FIGURE 3-2: START HEADER

SCIO

TSS THDR Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK NoSAK

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 11AA02UID
3.3 Acknowledge FIGURE 3-4: ACKNOWLEDGE BITS
An Acknowledge routine occurs after each byte is MAK (‘1’) SAK (‘1’)
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
master, and the second bit is transmitted by the slave.
Note: A MAK must always be transmitted
NoMAK (‘0’) NoSAK(1)
following the start header.
The Master Acknowledge, or MAK, is signified by trans-
mitting a ‘1’, and informs the slave that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a Note 1: A NoSAK is defined as any sequence that is not a
‘0’, and is used to end the current operation (and initiate valid SAK.
the write cycle for write operations).
Note: When a NoMAK is used to end a WRITE 3.4 Device Addressing
or WRSR instruction, the write cycle is not
A device address byte is the first byte received from the
initiated if no bytes of data have been
master device following the start header. The device
received.
address byte consists of a 4-bit family code, for the
The slave Acknowledge, or SAK, is also signified by 11AA02UID this is set as ‘1010’. The last four bits of
transmitting a ‘1’, and confirms proper communication. the device address byte are the device code, which is
However, unlike the NoMAK, the NoSAK is signified by hardwired to ‘0000’.
the lack of a middle edge during the bit period.
FIGURE 3-5: DEVICE ADDRESS BYTE
Note: In order to guard against bus contention, a
ALLOCATION
NoSAK will occur after the start header.
A NoSAK will occur for the following events: SLAVE ADDRESS MAK SAK
• Following the start header
• Following the device address, if no slave on the
bus matches the transmitted address 1 0 1 0 0 0 0 0
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL, and ERAL during a write cycle.
• If the slave becomes out of sync with the master
3.5 Bus Conflict Protection
• If a command is terminated prematurely by using To help guard against high current conditions arising
a NoMAK, with the exception of immediately after from bus conflicts, the 11AA02UID features a current-
the device address. limited output driver. The IOL and IOH specifications
See Figure 3.3 and Figure 3-4 for details. describe the maximum current that can be sunk or
sourced, respectively, by the SCIO pin. The
If a NoSAK is received from the slave after any byte 11AA02UID will vary the output driver impedance to
(except the start header), an error has occurred. The ensure that the maximum current level is not exceeded.
master should then perform a standby pulse and begin
the desired command again.

FIGURE 3-3: ACKNOWLEDGE

ROUTINE
Master Slave

MAK SAK

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11AA02UID
3.6 Device Standby There are two variables which can cause the
11AA02UID to lose synchronization. The first is
The 11AA02UID features a low-power Standby mode frequency drift, defined as a change in the bit period,
during which the device is waiting to begin a new TE. The second is edge jitter, which is a single occur-
command. A high-to-low transition on SCIO will exit rence change in the position of an edge within a bit
Low-Power mode and prepare the device for receiving period, while the bit period itself remains constant.
the start header.
Standby mode will be entered upon the following 3.8.1 FREQUENCY DRIFT
conditions: Within a system, there is a possibility that frequencies
• A NoMAK followed by a SAK (i.e., valid termina- can drift due to changes in voltage, temperature, etc.
tion of a command) The re-synchronization circuitry provides some toler-
• Reception of a standby pulse ance for such frequency drift. The tolerance range is
specified by two parameters, FDRIFT and FDEV. FDRIFT
Note: In the case of the WRITE, WRSR, SETAL, specifies the maximum tolerable change in bus fre-
or ERAL commands, the write cycle is quency per byte. FDEV specifies the overall limit in fre-
initiated upon receipt of the NoMAK, quency deviation within an operation (i.e., from the end
assuming all other write requirements of the start header until communication is terminated
have been met. for that operation). The start header at the beginning of
the next operation will reset the re-synchronization
3.7 Device Idle circuitry and allow for another FDEV amount of
frequency drift.
The 11AA02UID features an Idle mode during which
all serial data is ignored until a standby pulse occurs. 3.8.2 EDGE JITTER
Idle mode will be entered upon the following condi-
Ensuring that edge transitions from the master always
tions:
occur exactly in the middle or end of the bit period is not
• Invalid device address always possible. Therefore, the re-synchronization
• Invalid command byte, including Read, CRRD, circuitry is designed to provide some tolerance for edge
Write, WRSR, SETAL and ERAL during a write jitter.
cycle. The 11AA02UID adjusts its phase every MAK bit, so
• Missed edge transition TIJIT specifies the maximum allowable peak-to-peak
• Reception of a MAK following a WREN, WRDI, jitter relative to the previous MAK bit. Since the position
SETAL, or ERAL command byte of the previous MAK bit would be difficult to measure by
• Reception of a MAK following the data byte of a the master, the minimum and maximum jitter values for
WRSR command a system should be considered the worst-case. These
values will be based on the execution time for different
An invalid start header will indirectly cause the device
branch paths in software, jitter due to thermal noise,
to enter Idle mode. Whether or not the start header is
etc.
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the The difference between the minimum and maximum
master. If the slave is not synchronized with the values, as a percentage of the bit period, should be cal-
master, an edge transition will be missed, thus causing culated and then compared against TIJIT to determine
the device to enter Idle mode. jitter compliance.
Note: Because the 11AA02UID only re-synchro-
3.8 Synchronization nizes during the MAK bit, the overall ability
to remain synchronized depends on a
At the beginning of every command, the 11AA02UID
combination of frequency drift and edge
utilizes the start header to determine the master’s bus
jitter (i.e., if the MAK bit edge is experienc-
clock period. This period is then used as a reference for
ing the maximum allowable edge jitter,
all subsequent communication within that command.
then there is no room for frequency drift).
The 11AA02UID features re-synchronization circuitry Conversely, if the frequency has drifted to
which will monitor the position of the middle data edge the maximum amount tolerable within a
during each MAK bit and subsequently adjust the inter- byte, then no edge jitter can be present.
nal time reference in order to remain synchronized with
the master.

DS20005206A-page 8  2013 Microchip Technology Inc.

 11AA02UID
4.0 DEVICE COMMANDS
After the device address byte, a command byte must
be sent by the master to indicate the type of operation
to be performed. The code for each instruction is listed
in Table 4-1.

TABLE 4-1: INSTRUCTION SET

Instruction Name Instruction Code Hex Code Description
READ 0000 0011 0x03 Read data from memory array beginning at specified address
CRRD 0000 0110 0x06 Read data from current location in memory array
WRITE 0110 1100 0x6C Write data to memory array beginning at specified address
WREN 1001 0110 0x96 Set the write enable latch (enable write operations)
WRDI 1001 0001 0x91 Reset the write enable latch (disable write operations)
RDSR 0000 0101 0x05 Read STATUS register
WRSR 0110 1110 0x6E Write STATUS register
ERAL 0110 1101 0x6D Write ‘0x00’ to entire array
SETAL 0110 0111 0x67 Write ‘0xFF’ to entire array

4.1 Read Instruction To provide sequential reads in this manner, the

11AA02UID contains an internal Address Pointer which
The Read command allows the master to access any is incremented by one after the transmission of each
memory location in a random manner. After the READ byte. This Address Pointer allows the entire memory
instruction has been sent to the slave, the two bytes of contents to be serially read during one operation. When
the Word Address are transmitted, with an Acknowl- the highest address is reached, the Address Pointer
edge sequence being performed after each byte. Then, rolls over to address ‘0x00’ if the master chooses to
the slave sends the first data byte to the master. If more continue the operation by providing a MAK.
data is to be read, the master sends a MAK, indicating
that the slave should output the next data byte. This
continues until the master sends a NoMAK, which ends
the operation.

FIGURE 4-1: READ COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
MAK
SAK
MAK
SAK

MAK
SAK

Command Word Address MSB Word Address LSB

SCIO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1
NoMAK
SAK
MAK
SAK
MAK
SAK

Data Byte 1 Data Byte 2 Data Byte n

SCIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

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11AA02UID
4.2 Current Address Read (CRRD) TABLE 4-2: INTERNAL ADDRESS
Instruction COUNTER
The internal address counter featured on the Command Event Action
11AA02UID maintains the address of the last memory — Power-on Reset Counter is undefined
array location accessed. The CRRD instruction allows
Read or MAK edge Counter is updated
the master to read data back beginning from this
Write following each with newly received
current location. Consequently, no word address is
Address byte value
provided upon issuing this command.
Read, MAK/NoMAK Counter is incre-
Note that, except for the initial word address, the Write, or edge following mented by 1
READ and CRRD instructions are identical, including CRRD each data byte
the ability to continue requesting data through the use
of MAKs in order to sequentially read from the array.
Note: If, following each data byte in a READ,
As with the READ instruction, the CRRD instruction is
WRITE, or CRRD instruction, neither a
terminated by transmitting a NoMAK.
MAK nor a NoMAK edge is received (i.e.,
Table 4-2 lists the events upon which the internal if a standby pulse occurs instead), the
address counter is modified. internal address counter will not be incre-
mented.

Note: During a Write command, once the last

data byte for a page has been loaded, the
internal Address Pointer will rollover to the
beginning of the selected page.

FIGURE 4-2: CRRD COMMAND SEQUENCE NoSAK

MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
MAK
SAK

MAK
SAK

MAK
SAK
Command Data Byte 1 Data Byte 2

SCIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 0
NoMAK
SAK

Data Byte n

SCIO 7 6 5 4 3 2 1 0

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 11AA02UID
4.3 Write Instruction Upon receipt of each word, the four lower-order
Address Pointer bits are internally incremented by one.
Prior to any attempt to write data to the 11AA02UID, the The higher-order bits of the word address remain con-
write enable latch must be set by issuing the WREN stant. If the master should transmit data past the end of
instruction (see Section 4.4 “Write Enable (WREN) the page, the address counter will roll over to the begin-
and Write Disable (WRDI) Instructions”). ning of the page, where further received data will be
Once the write enable latch is set, the user may written.
proceed with issuing a WRITE instruction (including
Note: Page write operations are limited to writ-
the header and device address bytes) followed by the
ing bytes within a single physical page,
MSB and LSB of the Word Address. Once the last
regardless of the number of bytes actu-
Acknowledge sequence has been performed, the
ally being written. Physical page boundar-
master transmits the data byte to be written.
ies start at addresses that are integer
The 11AA02UID features a 16-byte page buffer, mean- multiples of the page size (16 bytes) and
ing that up to 16 bytes can be written at one time. To end at addresses that are integer multi-
utilize this feature, the master can transmit up to 16 ples of the page size minus 1. As an
data bytes to the 11AA02UID, which are temporarily example, the page that begins at address
stored in the page buffer. After each data byte, the 0x30 ends at address 0x3F. If a page
master sends a MAK, indicating whether or not another Write command attempts to write across a
data byte is to follow. A NoMAK indicates that no more physical page boundary, the result is that
data is to follow, and as such will initiate the internal the data wraps around to the beginning of
write cycle. the current page (overwriting data previ-
ously stored there), instead of being writ-
Note: If a NoMAK is generated before any data
ten to the next page as might be expected.
has been provided, or if a standby pulse
It is therefore necessary for the applica-
occurs before the NoMAK is generated,
tion software to prevent page write opera-
the 11AA02UID will be reset, and the write
tions that would attempt to cross a page
cycle will not be initiated.
boundary.

FIGURE 4-3: WRITE COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
MAK
SAK
MAK
SAK

MAK
SAK

Command Word Address MSB Word Address LSB

SCIO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 1 1 0 0
No MAK
SAK
MAK
SAK
MAK
SAK

Data Byte 1 Data Byte 2 Data Byte n

SCIO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Twc

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11AA02UID
4.4 Write Enable (WREN) and Write The following is a list of conditions under which the
Disable (WRDI) Instructions write enable latch will be reset:
• Power-up
The 11AA02UID contains a write enable latch. See
Table 6-1 for the Write-Protect Functionality Matrix. • WRDI instruction successfully executed
This latch must be set before any write operation will be • WRSR instruction successfully executed
completed internally. The WREN instruction will set the • WRITE instruction successfully executed
latch, and the WRDI instruction will reset the latch. • ERAL instruction successfully executed
Note: The WREN and WRDI instructions must be • SETAL instruction successfully executed
terminated with a NoMAK following the
command byte. If a NoMAK is not
received at this point, the command will be
considered invalid, and the device will go
into Idle mode without responding with a
SAK or executing the command.

FIGURE 4-4: WRITE ENABLE COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
NoMAK
SAK

Command

SCIO
1 0 0 1 0 1 1 0

FIGURE 4-5: WRITE DISABLE COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
NoMAK
SAK

Command

SCIO
1 0 0 1 0 0 0 1

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 11AA02UID
4.5 Read Status Register (RDSR) The Block Protection (BP0 and BP1) bits indicate
Instruction which blocks are currently write-protected. These bits
are set by the user through the WRSR instruction.
The RDSR instruction provides access to the STATUS These bits are nonvolatile.
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is Note: If Read Status Register command is
formatted as follows: initiated while the 11AA02UID is currently
executing an internal write cycle on the
7 6 5 4 3 2 1 0 STATUS register, the new Block
X X X X BP1 BP0 WEL WIP Protection bit values will be read during
Note: Bits 4-7 are don’t cares, and will read as ‘0’. the entire command.

The Write-In-Process (WIP) bit indicates whether the The WIP and WEL bits will update dynamically (asyn-
11AA02UID is busy with a write operation. When set to chronous to issuing the RDSR instruction). Further-
a ‘1’, a write is in progress, when set to a ‘0’, no write more, after the STATUS register data is received, the
is in progress. This bit is read-only. master can provide a MAK during the Acknowledge
sequence to request that the data be transmitted again.
The Write Enable Latch (WEL) bit indicates the status
This allows the master to continuously monitor the WIP
of the write enable latch. When set to a ‘1’, the latch
and WEL bits without the need to issue another full
allows writes to the array, when set to a ‘0’, the latch
command.
prohibits writes to the array. This bit is set and cleared
using the WREN and WRDI instructions, respectively. Once the master is finished, it provides a NoMAK to
This bit is read-only for any other instruction. end the operation.
Note: The current drawn for a Read Status
Register command during a write cycle is
a combination of the ICC Read and ICC
Write operating currents.

FIGURE 4-6: READ STATUS REGISTER COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
NoMAK
MAK
SAK

SAK

Command STATUS Register Data

SCIO 3 2 1 0
0 0 0 0 0 1 0 1 0 0 0 0

Note: The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.

 2013 Microchip Technology Inc. DS20005206A-page 13

11AA02UID
4.6 Write Status Register (WRSR) TABLE 4-3: ARRAY PROTECTION
Instruction Array Addresses
BP1 BP0
The WRSR instruction allows the user to select one of Write-Protected
four levels of protection for the array by writing to the 0 0 none
appropriate bits in the STATUS register. The array is
0 1 upper 1/4
divided up into four segments. The user has the ability
(C0h-FFh)
to write-protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as 1 0 upper 1/2
illustrated in Table 4-3. (80h-FFh)

After transmitting the STATUS register data, the master 1 1 all

must transmit a NoMAK during the Acknowledge (00h-FFh)
sequence in order to initiate the internal write cycle.
Note: The WRSR instruction must be terminated
with a NoMAK following the data byte. If a
NoMAK is not received at this point, the
command will be considered invalid, and
the device will go into Idle mode without
responding with a SAK or executing the
command.

FIGURE 4-7: WRITE STATUS REGISTER COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
NoMAK
MAK
SAK

SAK

Command Status Register Data

SCIO 7 6 5 4 3 2 1 0
0 1 1 0 1 1 1 0 Twc

DS20005206A-page 14  2013 Microchip Technology Inc.

 11AA02UID
4.7 Erase All (ERAL) Instruction The ERAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not ‘0’, meaning 1/4, 1/2, or
The ERAL instruction allows the user to write ‘0x00’ to all of the array is protected.
the entire memory array with one command. Note that
the write enable latch (WEL) must first be set by issuing Note: The ERAL instruction must be terminated
the WREN instruction. with a NoMAK following the command
byte. If a NoMAK is not received at this
Once the write enable latch is set, the user may pro-
point, the command will be considered
ceed with issuing a ERAL instruction (including the
invalid, and the device will go into Idle
header and device address bytes). Immediately after
mode without responding with a SAK or
the NoMAK bit has been transmitted by the master, the
executing the command.
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0x00’.

FIGURE 4-8: ERASE ALL COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK
Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
NoMAK
SAK

Command

SCIO
0 1 1 0 1 1 0 1 Twc

4.8 Set All (SETAL) Instruction The SETAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not ‘0’, meaning 1/4, 1/2, or
The SETAL instruction allows the user to write ‘0xFF’ all of the array is protected.
to the entire memory array with one command. Note
that the write enable latch (WEL) must first be set by Note: The SETAL instruction must be termi-
issuing the WREN instruction. nated with a NoMAK following the com-
mand byte. If a NoMAK is not received at
Once the write enable latch is set, the user may pro-
this point, the command will be consid-
ceed with issuing a SETAL instruction (including the
ered invalid, and the device will go into
header and device address bytes). Immediately after
Idle mode without responding with a SAK
the NoMAK bit has been transmitted by the master, the
or executing the command.
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0xFF’.

FIGURE 4-9: SET ALL COMMAND SEQUENCE

NoSAK
MAK

MAK
SAK

Standby Pulse Start Header Device Address

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0
NoMAK
SAK

Command

SCIO
0 1 1 0 0 1 1 1 Twc

 2013 Microchip Technology Inc. DS20005206A-page 15

11AA02UID
5.0 DATA PROTECTION 6.0 POWER-ON STATE
The following protection has been implemented to The 11AA02UID powers on in the following state:
prevent inadvertent writes to the array: • The device is in low-power Shutdown mode,
• The Write Enable Latch (WEL) is reset on power- requiring a low-to-high transition on SCIO to enter
up Idle mode
• A Write Enable (WREN) instruction must be issued • The Write Enable Latch (WEL) is reset
to set the write enable latch • The internal Address Pointer is undefined
• After a write, ERAL, SETAL, or WRSR command, • A low-to-high transition, standby pulse and subse-
the write enable latch is reset quent high-to-low transition on SCIO (the first low
• Commands to access the array or write to the pulse of the header) are required to enter the
STATUS register are ignored during an internal active state
write cycle and programming is not affected

TABLE 6-1: WRITE PROTECT FUNCTIONALITY MATRIX

WEL Protected Blocks Unprotected Blocks Status Register
0 Protected Protected Protected
1 Protected Writable Writable

DS20005206A-page 16  2013 Microchip Technology Inc.

 11AA02UID
7.0 PREPROGRAMMED UNIQUE 7.1 Manufacturer and Device Codes
32-BIT SERIAL NUMBER In addition to the serial number, a manufacturer code is
The 11AA02UID is programmed at the factory with a stored at location 0xFA and a device identifier is stored
unique 32-bit serial number stored in the upper 1/4 of at 0xFB. The manufacturer code is fixed as 0x29. For
the array and write-protected through the STATUS the 11AA02UID, the device identifier is ‘0x11’. The first
register. The remaining 1,536 bits are available for ‘1’ indicates the UNI/O® bus family and the second ‘1’
application use. indicates a 2 Kbit memory density.

Note: The 32-bit serial number is unique across 7.2 Factory-Programmed Write
all Microchip UID-family serial EEPROM
Protection
devices.
In order to help guard against accidental corruption of
FIGURE 7-1: MEMORY ORGANIZATION the serial number, the BP1 and BP0 bits of the STATUS
register are programmed at the factory to ‘0’ and ‘1’,
00h
respectively, as shown in the following table:

Standard 7 6 5 4 3 2 1 0
EEPROM X X X X BP1 BP0 WEL WIP
— — — — 0 1 — —
C0h This protects the upper 1/4 of the array (0xC0 to 0xFF)
Write-Protected
Serial Number Block from write operations. This array block can be utilized
FFh
for writing by clearing the BP bits with a Write Status
Register (WRSR) instruction. Note that if this is
The 4-byte serial number is stored in array locations
performed, care must be taken to prevent overwriting
0xFC through 0xFF, as shown in Figure 7-2.
the serial number.

FIGURE 7-2: SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE

Manufacturer Device
Description 32-bit Serial Number
Code Code

Data 29h 11h 12h 34h 56h 78h

Type Fixed Serialized

Array
Address FAh FBh FCh FDh FEh FFh

7.3 Extending the 32-bit Serial TABLE 7-1: EXTENDED READ EXAMPLES
Number Serial Number
Start Address End Address
For applications that require serial numbers larger than Length
32 bits, additional data bytes can be used to pad the 0xFC 0xFF 32 bits
provided serial number to meet the required length. 0xFA 0xFF 48 bits
Any data byte values can be used for padding as the
32-bit serial number ensures the extended serial 0xF8 0xFF 64 bits
number remains unique. 0xF0 0xFF 128 bits
The padding can be performed in two ways. The first 0xE0 0xFF 256 bits
method is to pad the data in software by combining the
32-bit serial number from the 11AA02UID with fixed
data. The second method is to extend the number of
bytes read from the 11AA02UID to meet the required
length. Table 7-1 shows example address ranges and
their corresponding serial number lengths.

 2013 Microchip Technology Inc. DS20005206A-page 17

11AA02UID
8.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 8-1.

TABLE 8-1: PIN FUNCTION TABLE

Name 3-pin SOT-23 8-pin SOIC Description

SCIO 1 5 Serial Clock, Data Input/Output

VCC 2 8 Supply Voltage
VSS 3 4 Ground
NC — 1,2,3,6,7 No Internal Connection

8.1 Serial Clock, Data Input/Output

(SCIO)
SCIO is a bidirectional pin used to transfer commands
and addresses into, as well as data into and out of, the
device. The serial clock is embedded into the data
stream through Manchester encoding. Each bit is
represented by a signal transition at the middle of the
bit period.

DS20005206A-page 18  2013 Microchip Technology Inc.

 11AA02UID
9.0 PACKAGING INFORMATION

9.1 Package Marking Information

8-Lead SOIC Example:

XXXXXXXT 11A2UIDI
XXXXYYWW SN e3 1328
NNN 1L7

3-Lead SOT-23 Example:

XXXNNN AAB1L7

1st Line Marking Code

Part Number SOT-23 SOIC

I Temp. I Temp.
11AA02UID AABNNN 11A2UIDT

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2013 Microchip Technology Inc. DS20005206A-page 19

11AA02UID

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005206A-page 20  2013 Microchip Technology Inc.

 11AA02UID

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013 Microchip Technology Inc. DS20005206A-page 21

11AA02UID


 


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($)

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!+$

DS20005206A-page 22  2013 Microchip Technology Inc.

 11AA02UID


 


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($)

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!+$

E
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1 2

e1
D

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A A2 φ

A1
L

>" ??3 3

!"
?!" @ @A E
@#!G 
)(" @ H
?%(  7;<
A#"%?%( 1 1;<
A= J   K 11

%%($ $""   7 1
%
)) 1 1 K 1
A= L% 3 1 K N

%%($L% 31 11N 1H 1
A= ?  N  H7


? ? 1H 7 N



  O K 1O
?% $""   K 
?%L% G H K 7
&
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"%31%

#%!
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6%7!! "%
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  3817
;<* ;"!"
 
6=#"
&&
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  & <1;

 2013 Microchip Technology Inc. DS20005206A-page 23

11AA02UID

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005206A-page 24  2013 Microchip Technology Inc.

 11AA02UID
APPENDIX A: REVISION HISTORY

Revision A (05/2013)
Initial release.

 2013 Microchip Technology Inc. DS20005206A-page 25

11AA02UID
NOTES:

DS20005206A-page 26  2013 Microchip Technology Inc.

 11AA02UID
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

 2013 Microchip Technology Inc. DS20005206A-page 27

11AA02UID
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 11AA02UID Literature Number: DS20005206A

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS20005206A-page 28  2013 Microchip Technology Inc.

 11AA02UID
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X X /XX
Examples:
Device Tape & Reel Temperature Package a) 11AA02UIDT-I/TT = 2 Kbit, 1.8V Serial
Range EEPROM with 32-bit serial number, Industrial
temp., Tape & Reel, SOT-23 package
b) 11AA02UID-I/SN = 2 Kbit, 1.8V Serial
EEPROM with 32-bit serial number, Industrial
Device: 11AA02UID = 2 Kbit, 1.8V UNI/O Serial EEPROM with temp., SOIC package
32-bit Serial Number
c) 11AA02UIDT-I/SN = 2 Kbit, 1.8V Serial
EEPROM with 32-bit serial number, Industrial
temp., Tape & Reel, SOIC package
Tape & Reel: T = Tape and Reel
Blank = Tube

Temperature I = -40C to+85C(Industrial)

Range:

Package: SN = 8-lead Plastic SOIC (3.90 mm body)

TT = 3-lead SOT 23 (Tape and Reel only)

 2013 Microchip Technology Inc. DS20005206A-page 29

11AA02UID
NOTES:

DS20005206A-page 30  2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyer’s risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620772287

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
== ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2013 Microchip Technology Inc. DS20005206A-page 31

 Worldwide Sales and Service
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DS20005206A-page 32  2013 Microchip Technology Inc.