N79E352 N79E352R Preliminary A06
N79E352 N79E352R Preliminary A06
N79E352 N79E352R Preliminary A06
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION.......................................................................................................... 4
2. FEATURES ................................................................................................................................. 5
3. PARTS INFORMATION LIST ..................................................................................................... 6
3.1 Lead Free (RoHS) Parts information list ......................................................................... 6
4. PIN CONFIGURATIONS ............................................................................................................. 7
5. PIN DESCRIPTIONS .................................................................................................................. 9
6. FUNCTIONAL DESCRIPTION .................................................................................................. 11
6.1 On-Chip Flash EPROM ................................................................................................. 11
6.2 I/O Ports ........................................................................................................................ 11
6.3 Serial I/O ....................................................................................................................... 11
6.4 Timers ........................................................................................................................... 11
6.5 Interrupts ....................................................................................................................... 11
6.6 Data Pointers ................................................................................................................ 11
6.7 Architecture ................................................................................................................... 11
6.8 Power Management ...................................................................................................... 12
7. MEMORY ORGANIZATION ...................................................................................................... 13
7.1 Program Memory (on-chip Flash) ................................................................................. 13
7.2 Data Memory................................................................................................................. 14
7.3 Scratch-pad RAM and Register Map ............................................................................ 14
8. SPECIAL FUNCTION REGISTERS .......................................................................................... 17
8.1 SFR Location Table ...................................................................................................... 17
8.2 SFR Detail Bit Descriptions ........................................................................................... 21
9. INSTRUCTION .......................................................................................................................... 51
9.1 Instruction Timing.......................................................................................................... 58
9.2 MOVX Instruction .......................................................................................................... 62
9.3 External Data Memory Access Timing .......................................................................... 63
9.4 Wait State Control Signal .............................................................................................. 66
10. POWER MANAGEMENT .......................................................................................................... 67
10.1 Idle Mode ...................................................................................................................... 67
10.2 Economy Mode ............................................................................................................. 67
10.3 Power Down Mode ........................................................................................................ 68
-1-
Preliminary N79E352/N79E352R Data Sheet
-2-
Preliminary N79E352/N79E352R Data Sheet
1. GENERAL DESCRIPTION
The N79E352(R) is an 8-bit Turbo 51 microcontroller which has Flash EPROM programmable
hardware writer. The instruction set of the N79E352(R) is fully compatible with the standard 8052. The
N79E352(R) contains a 8Kbytes of main Flash EPROM; a 256 bytes of RAM; 128 bytes NVM Data
Flash EPROM; three 16-bit timer/counters; 2-channel 8-bit PWM; 1-channel UART and 1 additional
input capture. These peripherals are supported by 11 interrupt sources four-level interrupt capability.
To facilitate programming and verification, the Flash EPROM inside the N79E352(R) allows the
program memory to be programmed and read electronically. Once the code is confirmed, the user can
protect the code for security. N79E352(R) is designed for cost effective applications which can serve
industrial devices, and other low power applications.
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Preliminary N79E352/N79E352R Data Sheet
2. FEATURES
• Fully static design 8-bit Turbo 51 CMOS microcontroller up to 24MHz when VDD=4.5V to 5.5V,
12MHz when VDD=2.7V to 5.5V, and 4MHz when VDD=2.4V to 5.5V.
• 8K bytes of AP Flash EPROM, with external writer programmable mode.
• 256 bytes of on-chip RAM.
• 128 bytes NVM Data Flash EPROM for customer data storage used and 10k writer cycles.
• Instruction-set compatible with MCS-51.
• On-chip configurable RC oscillator: 22.1184MHz/11.0592MHz (selectable by config bit) with ±2%
accuracy, at 5V voltage and 25°C condition. (±2% accuracy is only for N79E352R.)
• Three 16-bit timer/counters.
• One input capture.
• 11 interrupt source with four levels of priority.
• One enhanced full duplex serial port with framing error detection and automatic address
recognition.
• 4 outputs mode and TTL/Schmitt trigger selectable Port.
• Programmable Watchdog Timer with 20KHz internal RC clock can wake-up the power down
mode, and have very low power under 10uA at 5V.
• Two-channel 8-bit PWM.
• One I2C communication port.
• Dual 16-bit Data Pointers.
• Software programmable access cycle to external RAM/peripherals.
• Eight keypads interrupt inputs with sharing the same interrupt source.
• LED drive capability (20mA) on all port pins, total 100mA.
• Low Voltage (3 levels) Detection interrupt and reset.
•
o o
Industrial temperature grade -40 C~85 C.
• Packages:
Lead Free (RoHS) DIP40: N79E352RADG
Lead Free (RoHS) PLCC44: N79E352RAPG
Lead Free (RoHS) PQFP44: N79E352RAFG
Lead Free (RoHS) LQFP48: N79E352RALG
Lead Free (RoHS) DIP40: N79E352ADG
Lead Free (RoHS) PLCC44: N79E352APG
Lead Free (RoHS) PQFP44: N79E352AFG
Lead Free (RoHS) LQFP48: N79E352ALG
-
-6-
Preliminary N79E352/N79E352R Data Sheet
4. PIN CONFIGURATIONS
DIP 40-pin
RST 9 32 P0.7, AD7, KB7
RXD, P3.0 10 31 EA
P5.1,XTAL1 19 22 P2.1, A9
VSS 20 21 P2.0, A8
KB2, AD2, P0.2
T2EX, P1.1
SDA, P1.2
SCL, P1.3
T2, P1.0
VDD
P4.2
6
44
43
42
41
40
RXD, P3.0 11 35 EA
19
20
21
22
23
24
25
26
27
28
P2.0, A8
P2.3, A11
P3.6, WR
P3.7, RD
XTAL2, P5.2
XTAL1, P5.1
VSS
P4.0
P2.2, A10
P2.4, A12
P2.1, A9
P2.6, A14
P2.5, A13
P2.7, A15
P2.6, A14
P2.5, A13
PSEN
PSEN
P4.1
P4.1
ALE
ALE
NC
EA
EA
33
32
31
30
29
28
27
26
25
24
23
36
35
34
33
32
31
30
29
28
27
26
25
KB3, AD3, P0.3 34 22 P2.4, A12
KB3, AD3, P0.3 37 24 NC
KB2, AD2, P0.2 35 21 P2.3, A11 38 23 P2.4, A12
KB2, AD2, P0.2
KB1, AD1, P0.1 36 20 P2.2, A10 39 22 P2.3, A11
KB1, AD1, P0.1
37 19 P2.1, A9 40 21 P2.2, A10
LQFP 44-pin
LQFP 48-pin
VDD 38 18 P2.0, A8 VDD 41 20 P2.1, A9
P4.2 42 19 P2.0, A8
-8-
P4.2 39 17 P4.0
T2, P1.0 40 16 VSS T2, P1.0 43 18 P4.0
XTAL1, P5.1 T2EX, P1.1 44 17 VSS
T2EX, P1.1 41 15
SDA, P1.2 45 16 XTAL1, P5.1
SDA, P1.2 42 14 XTAL2, P5.2
SCL, P1.3 46 15 XTAL2, P5.2
SCL, P1.3 43 13 P3.7, RD
PWM0, P1.4 47 14 P3.7, /RD
PWM0, P1.4 44 12 P3.6, WR
NC 48 13 P3.6, /WR
10
11
1
10
11
12
1
9
RST
P1.6
P1.7
INT0, P3.2
INT1, P3.3
RXD, P3.0
TXD, P3.1
T0, P3.4
T1, P3.5
P4.3
PWM1, P1.5
PWM1, P1.5
RST
P4.3
NC
P1.6
P1.7
P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P3.0
Preliminary N79E352/N79E352R Data Sheet
5. PIN DESCRIPTIONS
SYMBOL Alternate Alternate Type DESCRIPTIONS
Function 1 function 2
EXTERNAL ACCESS ENABLE: This pin forces the
processor to execute out of external ROM. It should
be kept high to access internal ROM. The ROM
EA I address and data will not be present on the bus if
EA pin is high and the program counter is within
internal ROM area. Otherwise they will be present on
the bus.
- 10 -
Preliminary N79E352/N79E352R Data Sheet
6. FUNCTIONAL DESCRIPTION
N79E352(R) architecture consist of a 4T 8051 core controller surrounded by various registers, 8K
bytes Flash EPROM, 256 bytes of RAM, 128 bytes NVM Data Flash EPROM; three timer/counters,
one UART serial port, one I2C serial port, eight keyboard interrupt input, 2-channel PWM with 8-bit
counter and Flash EPROM program by Writer.
6.1 On-Chip Flash EPROM
N79E352(R) includes one 8K bytes of main Flash EPROM for application program which need Writer
to program the Flash EPROM.
6.2 I/O Ports
N79E352(R) has four 8-bit, one 4-bit port and one 2-bit port, with at least 36 I/O pins. All ports (except
port 4) can be used as four outputs mode when it may set by PxM1.y and PxM2.y registers, it has
strong pull-ups and pull-downs, and does not need any external pull-ups. Otherwise it can be used as
general I/O port as open drain circuit. All ports can be used bi-directional and these are as I/O ports.
These ports are not true I/O, but rather are pseudo-I/O ports. This is because these ports have strong
pull-downs and weak pull-ups.
6.3 Serial I/O
N79E352(R) has one UART serial port that is functionally similar to the serial port of the original 8052
family. However the serial port on N79E352(R) can operate in different modes in order to obtain timing
similarity as well. The Serial port has the enhanced features of Automatic Address recognition and
Frame Error detection.
6.4 Timers
The device has total three 16-bit timers; two 16-bit timers that have functions similar to the timers of
the 8052 family, and third timer is capable to function as timer and also provide capture support. When
used as timers, user has a choice to set 12 or 4 clocks per count that emulates the timing of the
original 8052. Each timer’s count value is stored in two SFR locations that can be written or read by
software. There are also some other SFRs associated with the timers that control their mode and
operation.
6.5 Interrupts
The Interrupt structure in N79E352(R) is slightly different from that of the standard 8052. Due to the
presence of additional features and peripherals, the number of interrupt sources and vectors has been
increased.
6.6 Data Pointers
The original 8052 had only one 16-bit Data Pointer (DPL, DPH). In the N79E352(R), there is an
additional 16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which
were unused in the original 8052. In addition there is an added instruction, DEC DPTR (op-code A5H),
which helps in improving programming flexibility for the user.
6.7 Architecture
N79E352(R) is based on the standard 8052 device. It is built around an 8-bit ALU that uses internal
registers for temporary storage and control of the peripheral devices. It can execute the standard 8052
instruction set.
6.7.1 ALU
The ALU is the heart of the N79E352(R). It is responsible for the arithmetic and logical functions. It is
also used in decision making, in case of jump instructions, and is also used in calculating jump
addresses. The user cannot directly use the ALU, but the Instruction Decoder reads the op-code,
decodes it, and sequences the data through the ALU and its associated registers to generate the
required result. The ALU mainly uses the ACC which is a special function register (SFR) on the chip.
Another SFR, namely B register is also used in Multiply and Divide instructions. The ALU generates
several status signals which are stored in the Program Status Word register (PSW).
6.7.2 Accumulator
The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations
in N79E352(R). Since the Accumulator is directly accessible by the CPU, most of the high speed
instructions make use of the ACC as one argument.
6.7.3 B Register
This is an 8-bit register that is used as the second argument in the MUL and DIV instructions. For all
other instructions it can be used simply as a general purpose register.
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Preliminary N79E352/N79E352R Data Sheet
7. MEMORY ORGANIZATION
N79E352(R) separates the memory into two separate sections, the Program Memory and the Data
Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is
used to store data or for memory mapped devices.
(128B NVM,
FFFFH
16bytes/page)
FC7Fh
Page 7
FC70h
FC6Fh
Page 6
FC60h
FC5Fh
Page 5
FC50h
FC7FH 128B FC4Fh
Page 4
NVM FC40h External
Data Memory FC3Fh
Program
(MOVX) Page 3
FC00H FC30h Memory
FC2Fh
Page 2
FC20h
FC1Fh
Page 1
FC10h
FC0Fh
Page 0
FC00h
2000H
NVM Data Flash Area 1FFFH
8K Bytes
On-Chip
CONFIG 1 Code Memory
CONFIG 0
0000H
Program
Memory Space
Figure 7-1: N79E352(R) Memory Map
7.1 Program Memory (on-chip Flash)
The Program Memory on N79E352(R) can be up to 8K bytes long. All instructions are fetched for
execution from this memory area. The MOVC instruction can also access this memory region.
- 14 -
Preliminary N79E352/N79E352R Data Sheet
FFH
Indirect RAM
80H
7FH
Direct RAM
30H
2FH 7F 7E 7D 7C 7B 7A 79 78
2EH 77 76 75 74 73 72 71 70
2DH 6F 6E 6D 6C 6B 6A 69 68
2CH 67 66 65 64 63 62 61 60
2BH 5F 5E 5D 5C 5B 5A 59 58
2AH 57 56 55 54 53 52 51 50
29H 4F 4E 4D 4C 4B 4A 49 48
28H 47 46 45 44 43 42 41 40
27H 3F 3E 3D 3C 3B 3A 39 38
26H 37 36 35 34 33 32 31 30
25H 2F 2E 2D 2C 2B 2A 29 28
24H 27 26 25 24 23 22 21 20
23H 1F 1E 1D 1C 1B 1A 19 18
22H 17 16 15 14 13 12 11 10
21H 0F 0E 0D 0C 0B 0A 09 08
20H 07 06 05 04 03 02 01 00
1FH
Bank 3
18H
17H
Bank 2
10H
0FH
Bank 1
08H
07H
Bank 0
00H
7.3.3 Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP), which
stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the return
address is placed on the stack. There is no restriction as to where the stack can begin in the RAM. By
default however, the Stack Pointer contains 07h at reset. The user can then change this to any value
desired. The SP will point to the last used value. Therefore, the SP will be incremented and then
address saved onto the stack. Conversely, while popping from the stack the contents will be read first,
and then the SP is decreased.
- 16 -
Preliminary N79E352/N79E352R Data Sheet
The N79E352(R) uses Special Function Registers (SFRs) to control and monitor peripherals and their
Modes.
The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of
the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit
without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or
8. The N79E352(R) contains all the SFRs present in the standard 8052. However, some additional
SFRs have been added. In some cases unused bits in the original 8052 have been given new
functions. The list of SFRs is as follows. The table is condensed with eight locations per row. Empty
locations indicate that there are no registers at these addresses. When a bit or register is not
implemented, it will read high.
8.1 SFR Location Table
F8 IP1 FF
F0 B IP1H F7
E8 EIE KBL PORTS P5M1 P5M2 EF
E0 ACC CCL0 CCH0 E7
D8 WDCON PWM0L PWM1L PWMCON1 DF
D0 PSW PWMCON3 D7
C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 NVMCON NVMDAT CF
C0 I2CON I2ADDR ROMMAP PMR STATUS NVMADDR TA C7
B8 IP0 SADEN I2DATA I2STATUS I2CLK I2TIMER BF
B0 P3 P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 IP0H B7
A8 IE SADDR AF
A0 P2 KBI AUXR1 CAPCON0 CAPCON1 P4 A7
98 SCON SBUF P3M1 P3M2 9F
90 P1 P5 97
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 8F
80 P0 SP DPL DPH DPL1 DPH1 DPS PCON 87
Note: The SFRs in the column with dark borders are bit-addressable.
Table 8- 1: Special Function Register Location Table
IP1H INTERRUPT HIGH PRIORITY 1 F7H PCAPH PBOH - PWDIH - - PKBH PI2H 00x0 xx00B
B B REGISTER F0H B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 0000 0000B
PORTS PORT SHMITT REGISTER ECH - - P5S - P3S P2S P1S P0S xx0x 0000B
KBL KEYBOARD LEVEL REGISTER E9H KBL.7 KBL.6 KBL.5 KBL.4 KBL.3 KBL.2 KBL.1 KBL.0 0000 0000B
EIE INTERRUPT ENABLE 1 E8H ECPTF EBO - EWDI - - EKB EI2 00x0 xx00B
CCH0 INPUT CAPTURE 0 HIGH E5H CCH0.7 CCH0.6 CCH0.5 CCH0.4 CCH0.3 CCH0.2 CCH0.1 CCH0.0 0000 0000B
CCL0 INPUT CAPTURE 0 LOW E4H CCL0.7 CCL0.6 CCL0.5 CCL0.4 CCL0.3 CCL0.2 CCL0.1 CCL0.0 0000 0000B
ACC ACCUMULATOR E0H ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 0000 0000B
PWM1L PWM 1 LOW BITS REGISTER DBH PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0 0000 0000B
PWM0L PWM 0 LOW BITS REGISTER DAH PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0 0000 0000B
WDCON WATCH-DOG CONTROL D8H WDRUN POR - - WDIF WTRF EWRST WDCLR POR:
X1xx 0000B
External reset:
Xxxx 0xx0B
Watchdog reset:
Xxxx 01x0B
PWMCON3 PWM CONTROL REGISTER 3 D7H - - PWM1OE PWM0OE PCLK.1 PCLK.0 FP1 FP0 Xx00 0000B
NVMDATA NVM DATA CFH NVMDATA.7 NVMDATA.6 NVMDATA.5 NVMDATA.4 NVMDATA. NVMDATA. NVMDATA. NVMDATA. 0000 0000B
3 2 1 0
TH2 TIMER 2 MSB CDH TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0 0000 0000B
TL2 TIMER 2 LSB CCH TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0 0000 0000B
RCAP2H TIMER 2 RELOAD MSB CBH RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0 0000 0000B
RCAP2L TIMER 2 RELOAD LSB CAH RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0 0000 0000B
T2MOD TIMER 2 MODE C9H - - - ICEN0 T2CR 1 T2OE DCEN Xxx0 0100B
T2CON TIMER 2 CONTROL C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL 0000 0000B
TA TIMED ACCESS PROTECTION C7H TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0 0000 0000B
NVMADDR NVM LOW BYTE ADDRESS C6H NVMADDR.7 NVMADDR.6 NVMADDR.5 NVMADDR.4 NVMADDR. NVMADDR. NVMADDR. NVMADDR. 0000 0000B
3 2 1 0
PMR POWER MANAGEMENT C4H CD1 CD0 SWB - - ALE-OFF - - 010x xxxxB
REGISTER
I2ADDR I2C ADDRESS1 C1H ADDR.7 ADDR.6 ADDR.5 ADDR.4 ADDR.3 ADDR.2 ADDR.1 GC xxxxxxx0B
- 18 -
Preliminary N79E352/N79E352R Data Sheet
I2CLK I2C CLOCK RATE BEH I2CLK.7 I2CLK.6 I2CLK.5 I2CLK.4 I2CLK.3 I2CLK.2 I2CLK.1 I2CLK.0 0000 0000B
I2STATUS I2C STATUS BDH I2STATUS.7 I2STATUS.6 I2STATUS.5 I2STATUS.4 I2STATUS. I2STATUS. I2STATUS. I2STATUS. 1111 1000B
3 2 1 0
I2DAT I2C DATA BCH I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0 xxxxxxxxB
SADEN SLAVE ADDRESS MASK B9H SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0 00000000B
IP0 INTERRUPT PRIORITY B8H - - PT2 PS PT1 PX1 PT0 PX0 Xx00 0000B
IP0H INTERRUPT HIGH PRIORITY B7H - - PT2H PSH PT1H PX1H PT0H PX0H Xx00 0000B
P2M2 PORT 2 OUTPUT MODE 2 B6H P2M2.7 P2M2.6 P2M2.5 P2M2.4 P2M2.3 P2M2.2 P2M2.1 P2M2.0 CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
P2M1 PORT 2 OUTPUT MODE 1 B5H P2M1.7 P2M1.6 P2M1.5 P2M1.4 P2M1.3 P2M1.2 P2M1.1 P2M1.0 CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
P1M2 PORT 1 OUTPUT MODE 2 B4H P1M2.7 P1M2.6 P1M2.5 P1M2.4 P1M2.3 P1M2.2 P1M2.1 P1M2.0 CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
P1M1 PORT 1 OUTPUT MODE 1 B3H P1M1.7 P1M1.6 P1M1.5 P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0 CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
P0M2 PORT 0 OUTPUT MODE 2 B2H P0M2.7 P0M2.6 P0M2.5 P0M2.4 P0M2.3 P0M2.2 P0M2.1 P0M2.0 1111 1111B
P0M1 PORT 0 OUTPUT MODE 1 B1H P0M1.7 P0M1.6 P0M1.5 P0M1.4 P0M1.3 P0M1.2 P0M1.1 P0M1.0 1111 1111B
P3 PORT3 B0H P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 1111 1111B
SADDR SLAVE ADDRESS A9H SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0 0000 0000B
IE INTERRUPT ENABLE A8H EA - ET2 ES ET1 EX1 ET0 EX0 0x00 0000B
AUXR1 AUX FUNCTION REGISTER 1 A2H KBF BOD BOI LPBOV SRST BOV1 BOV0 BOS 0000 0000B
KBI KEYBOARD INTERRUPT A1H KBI.7 KBI.6 KBI.5 KBI.4 KBI.3 KBI.2 KBI.1 KBI.0 0000 0000B
P2 PORT 2 A0H P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 1111 1111B
P3M2 PORT 3 OUTPUT MODE 2 9FH P3M2.7 P3M2.6 P3M2.5 P3M2.4 P3M2.3 P3M2.2 P3M2.1 P3M2.0 CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
SBUF SERIAL BUFFER 99H SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Xxxx xxxxB
SCON SERIAL CONTROL 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 0000 0000B
- - - - - - XTAL1 XTAL2
- - - - - - - CLKOUT
P1 PORT 1 90H P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 1111 1111B
CKCON CLOCK CONTROL 8EH WD1 WD0 T2M T1M T0M MD2 MD1 MD0 0000 0001B
TH1 TIMER HIGH 1 8DH TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 0000 0000B
TH0 TIMER HIGH 0 8CH TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 0000 0000B
TL1 TIMER LOW 1 8BH TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 0000 0000B
TL0 TIMER LOW 0 8AH TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 0000 0000B
TMOD TIMER MODE 89H GATE C/T M1 M0 GATE C/T M1 M0 0000 0000B
TCON TIMER CONTROL 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0000 0000B
PCON POWER CONTROL 87H SM0D SMOD0 BOF - GF1 GF0 PD IDL 001x 0000B
DPH1 DATA POINTER HIGH 1 85H DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 0000 0000B
DPL1 DATA POINTER LOW 1 84H DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 0000 0000B
DPH DATA POINTER HIGH 83H DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 0000 0000B
DPL DATA POINTER LOW 82H DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 0000 0000B
SP STACK POINTER 81H SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 0000 0111B
P0 PORT 0 80H P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 1111 1111B
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Preliminary N79E352/N79E352R Data Sheet
PORT 0
Bit: 7 6 5 4 3 2 1 0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
STACK POINTER
Bit: 7 6 5 4 3 2 1 0
SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
0 DPS This bit is used to select either the DPL,DPH pair or the DPL1,DPH1 pair as the
active Data Pointer. When set to 1, DPL1, DPH1 will be selected, otherwise DPL,
DPH will be selected.
POWER CONTROL
Bit: 7 6 5 4 3 2 1 0
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Preliminary N79E352/N79E352R Data Sheet
TIMER CONTROL
Bit: 7 6 5 4 3 2 1 0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
INT0 . This bit is cleared by hardware when the service routine is vectored to
only if the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level
0 IT0
triggered external inputs.
TIMER 0 LSB
Bit: 7 6 5 4 3 2 1 0
TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
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Preliminary N79E352/N79E352R Data Sheet
TIMER 1 LSB
Bit: 7 6 5 4 3 2 1 0
TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
TIMER 0 MSB
Bit: 7 6 5 4 3 2 1 0
TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
TIMER 1 MSB
Bit: 7 6 5 4 3 2 1 0
TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
CLOCK CONTROL
Bit: 7 6 5 4 3 2 1 0
WD1 WD0 T2M T1M T0M MD2 MD1 MD0
Stretch MOVX select bits: These three bits are used to select the stretch value
for the MOVX instruction. Using a variable MOVX length enables the user to
access slower external memory devices or peripherals without the need for
external circuits. The RD or WR strobe will be stretched by the selected
interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2
machine cycles regardless of the stretch setting. By default, the stretch has value
of 1. If the user needs faster accessing, then a stretch value of 0 should be
selected.
2~0 MD2~0 MD2 MD1 MD0 Stretch value MOVX duration
0 0 0 0 2 machine cycles
0 0 1 1 3 machine cycles (Default)
0 1 0 2 4 machine cycles
0 1 1 3 5 machine cycles
1 0 0 4 6 machine cycles
1 0 1 5 7 machine cycles
1 1 0 6 8 machine cycles
1 1 1 7 9 machine cycles
PORT 1
Bit: 7 6 5 4 3 2 1 0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
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Preliminary N79E352/N79E352R Data Sheet
PORT 5
Bit: 7 6 5 4 3 2 1 0
P5.0/
P5.1/
- - - - - - XTAL2/
XTAL1
CLKOUT
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Preliminary N79E352/N79E352R Data Sheet
PORT 2
Bit: 7 6 5 4 3 2 1 0
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
KEYBOARD INTERRUPT
Bit: 7 6 5 4 3 2 1 0
KBI.7 KBI.6 KBI.5 KBI.4 KBI.3 KBI.2 KBI.1 KBI.0
7 KBF 1: When any pin of port 0 that is enabled for the Keyboard Interrupt function
triggers (trigger level is depending on SFR KBL configuration). Must be cleared by
software.
Brown Out Disable:
0: Enable Brownout Detect function.
6 BOD 1: Disable Brownout Detect function and save power.
BOD is initialized at all resets with the inverse value of bit CBOD in config0.3 bit.
User is able to re-configure this bit after reset.
Brown Out Interrupt:
0: Disable Brownout Detect Interrupt function.
5 BOI
1: This prevents brownout detection from causing a chip reset and allows the
Brownout Detect function to be used as an interrupt.
Low Power Brown Out Detect control:
0: When BOD is enable, the Brown Out detect is always turned on by normal run
or Power Down mode.
4 LPBOV
1: When BOD is enable, the 1/16 time will be turned on Brown Out detect circuit
by Power Down mode. When uC is entry Power Down mode, the BOD will enable
internal RC OSC (20KHz).
Software reset:
1: Reset the chip as if a hardware reset occurred.
3 SRST
SRST require Timed Access procedure to write. The remaining bits have
unrestricted write accesses. Please refer TA register description.
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Preliminary N79E352/N79E352R Data Sheet
2-1 - Reserved.
0 CPTF0 External input capture 0 interrupt flag. It can be cleared by software.
PORT 4
Bit: 7 6 5 4 3 2 1 0
- - - - P4.3 P4.2 P4.1 P4.0
INTERRUPT ENABLE
Bit: 7 6 5 4 3 2 1 0
EA - ET2 ES ET1 EX1 ET0 EX0
SLAVE ADDRESS
Bit: 7 6 5 4 3 2 1 0
SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
PORT 3
Bit: 7 6 5 4 3 2 1 0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
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Preliminary N79E352/N79E352R Data Sheet
P3.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT NAME FUNCTION
7 P3.7 /RD or I/O pin by alternative.
6 P3.6 /WR or I/O pin by alternative.
5 P3.5 T1 or I/O pin by alternative.
4 P3.4 T0 or I/O pin by alternative.
3 P3.3 /INT1 or I/O pin by alternative.
2 P3.2 /INT0 or I/O pin by alternative.
1 P3.1 TxD or I/O pin by alternative.
0 P3.0 RxD or I/O pin by alternative.
INTERRUPT PRIORITY 0
Bit: 7 6 5 4 3 2 1 0
- - PT2 PS PT1 PX1 PT0 PX0
- 34 -
Preliminary N79E352/N79E352R Data Sheet
- 36 -
Preliminary N79E352/N79E352R Data Sheet
be generated.
1: The STA bit is set to enter a master mode. The I2C hardware checks the
status of I2C bus and generates a START condition if the bus is free. If bus is
not free, then I2C waits for a STOP condition and generates a START
condition after a delay. If STA is set while I2C is already in a master mode
and one or more bytes are transmitted or received, I2C transmits a repeated
START condition. STA may be set any time. STA may also be set when I2C
interface is an addressed slave mode.
The bit STO bit is set while I2C is in a master mode. A STOP condition is
transmitted to the I2C bus. When the STOP condition is detected on the bus,
the I2C hardware clears the STO flag. In a slave mode, the STO flag may be
set to recover from a bus error condition. In this case, no STOP condition is
transmitted to the I2C bus. However, the I2C hardware behaves as if a STOP
4 STO
condition has been received and it switches to the not addressable slave
receiver mode. The STO flag is automatically cleared by hardware. If the STA
and STO bits are both set, then a STOP condition is transmitted to the I2C bus
if I2C is in a master mode (in a slave mode, I2C generates an internal STOP
condition which is not transmitted). I2C then transmits a START condition.
0: When the SI flag is reset, no serial interrupt is requested, and there is no
stretching on the serial clock on the SCL line.
1: When a new I2C bus state is present in the I2STATUS register, the SI flag is
set by hardware, and, if the EA and ES bits (in IE register) are both set, a
3 SI serial interrupt is requested when SI is set. The only state that does not
cause SI to be set is state F8H, which indicates that no relevant state
information is available. When SI is set, the low period of the serial clock on
the SCL line is stretched, and the serial transfer is suspended. A high level on
the SCL line is unaffected by the serial interrupt flag. SI must be cleared by
software.
Assert Acknowledge Flag:
0: A not acknowledge (high level to SDA) will be returned during the
acknowledge clock pulse on SCL when: 1) A data has been received while
I2C is in the master receiver mode. 2) A data byte has been received while
I2C is in the addressed slave receiver mode.
2 AA
1: An acknowledge (low level to SDA) will be returned during the acknowledge
clock pulse on the SCL line when: 1) The own slave address has been
received. 2) A data byte has been received while I2C is in the master receiver
mode. 3) A data byte has been received while I2C is in the addressed slave
receiver mode. 4) The General Call address has been received while the
general call bit (GC) in I2ADDR is set.
1~0 - Reserved.
ROMMAP
Bit: 7 6 5 4 3 2 1 0
WS 1 - - - 1 1 0
Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The
7 WS device will sample the wait state control signal WAIT via P4.0 during MOVX
instruction. This bit is time access protected.
6~0 - Reserved.
TA REG C7H
ROMMAP REG C2H
CKCON REG 8EH
MOV TA,#AAH
MOV TA,#55H
ORL ROMMAP,#10000000B ; Set WS bit to enable wait signal.
POWER MANAGEMENT REGISTER
Bit: 7 6 5 4 3 2 1 0
CD1 CD0 SWB - - ALE-OFF - -
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Preliminary N79E352/N79E352R Data Sheet
Clock Divide Control. These bit selects the number of clocks required to
generate one machine cycle. There are three modes including divide by 4, 64 or
1024. Switching between modes must first go back devide by 4 mode. For
instance, to go from 64 to 1024 clocks/machine cycle the device must first go
from 64 to 4 clocks/machine cycle, and then from 4 to 1024 clocks/machine
cycle.
7~6 CD1~0
CD1, CD0 Clocks/machine Cycle
0 X 4
1 0 64
1 1 1024
Switchback Enable. Setting this bit allows an enabled external interrupt or serial
port/I2C activity to force the CD1, CD0 to divide by 4 state (0,X). The device will
switch modes at the start of the jump to interrupt service routine while an
5 SWB external interrupt is enabled and actually recognized by microcontroller. While a
serial port/I2C reception, the switchback occurs at the start of the instruction
following the falling edge of the start bit. Note: Changing SWB bit is ignored
during serial port/I2C activities.
4~3 - Reserved.
This bit disables the expression of the ALE signal on the device pin during all on-
board program and data memory accesses. External memory accesses will
2 ALE-0FF automatically enable ALE independent of ALE-OFF.
0 = ALE expression is enable.
1 = ALE expression is disable.
1~0 - Reserved.
STATUS
Bit: 7 6 5 4 3 2 1 0
- - - - - - SPTA0 SPRA0
TIMED ACCESS
Bit: 7 6 5 4 3 2 1 0
TA.7 TA.6 TA.5 TA.4 TA.3 TA.2 TA.1 TA.0
TIMER 2 CONTROL
Bit: 7 6 5 4 3 2 1 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C / T2 CP / RL2
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Preliminary N79E352/N79E352R Data Sheet
Transmit Clock Flag: This bit determines the serial port time-base when
transmitting data in modes 1 and 3. If it is set to 0, the timer 1 overflow is used
4 TCLK
to generate the baud rate clock otherwise timer 2 overflow is used. Setting this
bit forces timer 2 in baud rate generator mode.
Timer 2 External Enable. This bit enables the capture/reload function on the
T2EX pin if Timer 2 is not generating baud clocks for the serial port. If this bit is
3 EXEN2
0, then the T2EX pin will be ignored, otherwise a negative transition detected on
the T2EX pin will result in capture or reload.
Timer 2 Run Control:
2 TR2 This bit enables/disables the operation of timer 2. Halting this will preserve the
current count in TH2, TL2.
Counter/Timer Select. This bit determines whether timer 2 will function as a timer
or a counter. Independent of this bit, the timer will run at 2 clocks per tick when
1 C / T2 used in baud rate generator mode. If it is set to 0, then timer 2 operates as a
timer at a speed depending on T2M bit (CKCON.5), otherwise it will count
negative edges on T2 pin.
Compare/Reload Select:
This bit determines whether the capture or reload function will be used for timer
2. If either RCLK or TCLK is set, this bit will be ignored and the timer will function
0 CP / RL2 in an auto-reload mode following each overflow. If the bit is 0 then auto-reload
will occur when timer 2 overflows or a falling edge is detected on T2EX pin if
EXEN2 = 1. If this bit is 1, then timer 2 captures will occur when a falling edge is
detected on T2EX pin if EXEN2 = 1.
TIMER 2 MODE CONTROL
Bit: 7 6 5 4 3 2 1 0
- - - ICEN0 T2CR 1 T2OE DCEN
7 6 5 4 3 2 1 0
7-0 RCAP2L This register is used to capture the TL2 value when a timer 2 is configured in
capture mode.RCAP2L is also used as the LSB of a 16-bit reload value when
timer 2 is configured in auto-reload mode.
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Preliminary N79E352/N79E352R Data Sheet
7-0 RCAP2H This register is used to capture the TH2 value when a timer 2 is configured in
capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when
timer 2 is configured in auto-reload mode.
TIMER 2 LSB
Bit: 7 6 5 4 3 2 1 0
TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
TIMER 2 MSB
Bit: 7 6 5 4 3 2 1 0
TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
NVM CONTROL
Bit: 7 6 5 4 3 2 1 0
EER EWR EnNVM - - - - -
1: Set this bit to write NVM bytes and program counter will halt at this instruction.
After write is finished, program counter will kept next instruction then
executed.
5 EnNVM To enable read NVM data memory area.
0: To disable the MOVX instruction to read NVM data memory.
1: To enable the MOVX instruction to read NVM data memory, the External RAM
or AUX-RAM will be disabled.
4-0 - Reserved
NVM DATA
Bit: 7 6 5 4 3 2 1 0
NVMDAT. NVMDAT. NVMDAT. NVMDAT. NVMDAT NVMDAT. NVMDAT. NVMDAT.
7 6 5 4 3 2 1 0
- 44 -
Preliminary N79E352/N79E352R Data Sheet
WATCHDOG CONTROL
Bit: 7 6 5 4 3 2 1 0
WDRUN POR - - WDIF WTRF EWRST WDCLR
- 46 -
Preliminary N79E352/N79E352R Data Sheet
ACCUMULATOR
Bit: 7 6 5 4 3 2 1 0
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
- 48 -
Preliminary N79E352/N79E352R Data Sheet
B REGISTER
Bit: 7 6 5 4 3 2 1 0
INTERRUPT PRIORITY 1
Bit: 7 6 5 4 3 2 1 0
PCAP PBO - PWDI - - PKB PI2
- 50 -
Preliminary N79E352/N79E352R Data Sheet
9. INSTRUCTION
The N79E352(R) executes all the instructions of the standard 8052 family. The operation of these
instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of
these instructions is different. The reason for this is two fold. Firstly, in the N79E352(R), each machine
cycle consists of 4 clock periods, while in the standard 8052 it consists of 12 clock periods. Also, in the
N79E352(R) there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard
8052 there can be two fetches per machine cycle, which works out to 6 clocks per fetch.
The advantage the N79E352(R) has is that since there is only one fetch per machine cycle, the number
of machine cycles in most cases is equal to the number of operands that the instruction has. In case of
jumps and calls there will be an additional cycle that will be needed to calculate the new address. But
overall the N79E352(R) reduces the number of dummy fetches and wasted cycles, thereby improving
efficiency as compared to the standard 8052.
Table 9-1: Instructions that affect Flag settings
Auxiliary Auxiliary
Instruction Carry Overflow Instruction Carry Overflow
Carry Carry
ADD X X X CLR C 0
ADDC X X X CPL C X
SUBB X X X ANL C, bit X
MUL 0 X ANL C, bit X
DIV 0 X ORL C, bit X
DA A X ORL C, bit X
RRC A X MOV C, bit X
RLC A X CJNE X
SETB C 1
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Preliminary N79E352/N79E352R Data Sheet
- 54 -
Preliminary N79E352/N79E352R Data Sheet
- 56 -
Preliminary N79E352/N79E352R Data Sheet
- 58 -
Preliminary N79E352/N79E352R Data Sheet
The instruction timing for the N79E352(R) is an important aspect, especially for those users who wish
to use software instructions to generate timing delays. Also, it provides the user with an insight into the
timing differences between the N79E352(R) and the standard 8052. In the N79E352(R) each machine
cycle is four clock periods long. Each clock period is designated a state. Thus each machine cycle is
made up of four states, C1, C2 C3 and C4, in that order. Due to the reduced time for each instruction
execution, both the clock edges are used for internal timing. Hence it is important that the duty cycle of
the clock be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the
N79E352(R) does one op-code fetch per machine cycle. Therefore, in most of the instructions, the
number of machine cycles needed to execute the instruction is equal to the number of bytes in the
instruction. Of the 256 available op-codes, 128 of them are single cycle instructions. Thus more than
half of all op-codes in the N79E352(R) are executed in just four clock periods. Most of the two-cycle
instructions are those that have two byte instruction codes. However there are some instructions that
have only one byte instructions, yet they are two cycle instructions. One instruction which is of
importance is the MOVX instruction. In the standard 8052, the MOVX instruction is always two machine
cycles long. However in the N79E352(R), the user has a facility to stretch the duration of this instruction
from 2 machine cycles to 9 machine cycles. The RD and WR strobe lines are also proportionately
elongated. This gives the user flexibility in accessing both fast and slow peripherals without the use of
external circuitry and with minimum software overhead. The rest of the instructions are either three,
four or five machine cycle instructions. Note that in the N79E352(R), based on the number of machine
cycles, there are five different types, while in the standard 8052 there are only three. However, in the
N79E352(R) each machine cycle is made of only 4 clock periods compared to the 12 clock periods for
the standard 8052. Therefore, even though the number of categories has increased, each instruction is
at least 1.5 to 3 times faster than the standard 8052 in terms of clock periods.
Single Cycle
C1 C2 C3 C4
CLK
ALE
PSEN
A7-0 Data_ in D7-0
AD7-0
Address A15-8
PORT 2
ALE
PSEN
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
- 60 -
Preliminary N79E352/N79E352R Data Sheet
CLK
ALE
PSEN
Instruction Fetch Operand Fetch Operand Fetch Operand Fetch Operand Fetch
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
AD7-0 A7-0 OP-CODE A7-0 OPERAND A7-0 OPERAND A7-0 OPERAND A7-0 OPERAND
PORT 2 Address A15-8 Address A15-8 Address A15-8 Address A15-8 Address A15-8
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Preliminary N79E352/N79E352R Data Sheet
We can see that in the first program the standard 8052 takes 15720 cycles, while the N79E352(R)
takes only 5240 cycles for the same code. In the second program, written for the N79E352(R),
program execution requires only 3048 clock cycles. If the size of the block is increased then the saving
is even greater.
9.3 External Data Memory Access Timing
The timing for the MOVX instruction is another feature of the N79E352(R). In the standard 8052, the
MOVX instruction has a fixed execution time of 2 machine cycles. However in the N79E352(R), the
duration of the access can be varied by the user.
The instruction starts off as a normal op-code fetch of 4 clocks. In the next machine cycle, the
N79E352(R) puts out the address of the external Data Memory and the actual access occurs here. The
user can change the duration of this access time by setting the STRETCH value. The Clock Control
SFR (CKCON) has three bits that control the stretch value. These three bits are M2-0 (bits 2-0 of
CKCON). These three bits give the user 8 different access time options. The stretch can be varied
from 0 to 7, resulting in MOVX instructions that last from 2 to 9 machine cycles in length. Note that the
stretching of the instruction only results in the elongation of the MOVX instruction, as if the state of the
CPU was held for the desired period. There is no effect on any other instruction or its timing. By
Publication Release Date: Jul, 29, 2009
- 63 - Revision A06
Preliminary N79E352/N79E352R Data Sheet
default, the Stretch value is set at 1, giving a MOVX instruction of 3 machine cycles. If desired by the
user the stretch value can be set to 0 to give the fastest MOVX instruction of only 2 machine cycles.
Table 9-3: Data Memory Cycle Stretch Values
Machine RD or WR RD or WR
M2 M1 M0 strobe width strobe width
Cycles
in Clocks @ 20 MHz
0 0 0 2 2 100 nS
0 0 1 3 (default) 4 200 nS
0 1 0 4 8 400 nS
0 1 1 5 12 600 nS
1 0 0 6 16 800 nS
1 0 1 7 20 1000 nS
1 1 0 8 24 1200 nS
1 1 1 9 28 1400 nS
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
WR
A0-A7 A0-A7 D0-D7 D0-D7
PORT 0 D0-D7 A0-A7 A0-A7 D0-D7
- 64 -
Preliminary N79E352/N79E352R Data Sheet
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
WR
A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7
PORT 0
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
WR
A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7
PORT 0
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Preliminary N79E352/N79E352R Data Sheet
reducing of operating speed is restricted. In order to solve these dilemmas, the N79E352(R) offers a
switchback feature which allows the CPU back to clock/4 mode immediately when triggered by serial
operation (uart and I2C) or external interrupts. The switchback feature is enabled by setting the SWB
bit (PMR.5). A serial port/I2C reception/transmission or qualified external interrupt which is enabled
and acknowledged without block conditions will cause CPU to return to divide by 4 mode. For the serial
port reception, a switchback is generated by a falling edge associated with start bit if the serial port
reception is enabled. When a serial port transmission, an instruction which writes a byte of data to
serial port buffer will cause a switchback to ensure the correct transmission. The switchback feature is
unaffected by serial port interrupt flags. Similarly for I2C reception/transmission, a switchback is
generated when a start condition is determined. After a switchback is generated, the software can
manually return the CPU to Economy mode. Note that the modification of clock control bits CD0 and
CD1 will be ignored during I2C or serial port transmit/receive when switchback is enabled. The
Watchdog timer reset, power-on/fail reset, software reset, brownout reset or external reset will force
the CPU to return to divide by 4 mode.
10.3 Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this
will be the last instruction to be executed before the device goes into Power Down mode. In the Power
Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The N79E352(R) will exit the Power Down mode with a reset or by an external interrupt pin. An
external reset can be used to exit the Power down state. The high on RST pin terminates the Power
Down mode, and restarts the clock. The program execution will restart from 0000h. In the Power down
mode, the clock is stopped, so the Watchdog timer cannot be used to provide the reset to exit Power
down mode when its clock source is external OSC or crystal.
The sources that can wake up from the power down mode are external interrupts, keyboard interrupt
(KBI), brownout reset (BOR), and watchdog timer interrupt (if WDTCK = 0).
The N79E352(R) can be woken from the Power Down mode by forcing an external interrupt pin
activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and
the external input has been set to a level detect mode. If these conditions are met, then the low level
on the external pin re-starts the oscillator. Then device executes the interrupt service routine for the
corresponding external interrupt. After the interrupt service routine is completed, the program execution
returns to the instruction after the one which put the device into Power Down mode and continues from
there.
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Preliminary N79E352/N79E352R Data Sheet
Reset does not affect the on-chip RAM, however, so RAM is preserved as long as VDD remains above
approximately 2V, the minimum operating voltage for the RAM. If VDD falls below 2V, the RAM
contents are also lost. In either case, the stack pointer is always reset, so the stack contents are lost.
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset Watchdog reset Power on reset
WDCON 0xxx0x00b 0xxx0100b 01xx0000b
The POR bit WDCON.6 is set only by the power on reset. WTRF bit WDCON.2 is set when the
Watchdog timer causes a reset. A power on reset will also clear this bit. The EWRST bit WDCON.1 is
cleared by all reset. This disables the Watchdog timer resets.
All the bits in this SFR have unrestricted read access. WDRUN, POR, EWRST, WDIF and WDCLR
require Timed Access procedure to write. The remaining bits have unrestricted write accesses.
- 70 -
Preliminary N79E352/N79E352R Data Sheet
12.2.1 Mode 0
In Mode 0, the timer/counters act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode we
have a 13 bit timer/counter. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx. The
upper 3 bits of TLx are ignored.
The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx
moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves
from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if
TRx is set and either GATE = 0 or INTx = 1. When C / T is set to 0, then it will count clock cycles, and
if C / T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1.
When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The timer
overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when
used as a timer, the time-base may be either clock cycles/12 or clock cycles/4 as selected by the bits
TxM of the CKCON SFR.
GATE = TMOD.3
(GATE = TMOD.7) TFx Interrupt
INT0 = P3.2
TF0
(INT1 = P3.3)
(TF1)
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Preliminary N79E352/N79E352R Data Sheet
12.2.2 Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13
bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer
moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if
enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in
Mode 0. The gate function operates similarly to that in Mode 0.
12.2.3 Mode 2
In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count
register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx
bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues
from here. The reload operation leaves the contents of the THx register unchanged. Counting is
enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1
mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn.
T0M = CKCON.3
(T1M = CKCON.4) Timer 1 functions are shown in brackets
GATE = TMOD.3
(GATE = TMOD.7)
INT0 = P3.2 0 7
(INT1 = P3.3)
TH0
(TH1)
12.2.4 Mode 3
Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply
freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count
registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0
control bits C / T , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12 or
clock/4) or 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle
counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is
used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used
in Modes 0, 1 and 2., but its flexibility is somewhat limited. While its basic functionality is maintained, it
no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a
timer/counter and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by
switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the serial
port.
T0M = CKCON.3
TR0 = TCON.4
GATE = TMOD.3
INT0 = P3.2
TF1 Interrupt
TR1 = TCON.6 0 7
TH0
12.3 Timer/Counter 2
Timer/Counter 2 is a 16 bit up/down counter which is configured by the T2MOD register and controlled
by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the Timer
0 and Timer 1 counters, there exists considerable flexibility in selecting and controlling the clock, and in
defining the operating mode. The clock source for Timer/Counter 2 may be selected for either the
external T2 pin (C/T2 = 1) or the crystal oscillator, which is divided by 12 or 4 (C/T2 = 0). The clock is
then enabled when TR2 is a 1, and disabled when TR2 is a 0.
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Preliminary N79E352/N79E352R Data Sheet
T2M=CKCON.5
1/4
1
Fcpu C/T2=T2CON.1
0
0 T2CON.7
1/12 TL2 TH2 TF2
1
T2=P1.0
Timer2
TR2=T2CON.2
Interrupt
RCAP2L RCAP2H
T2EX=P1.1
EXF2
T2CON.6
EXEN2=T2CON.3
T2M=CKCON.5
1/4
1
Fcpu C/T2=T2CON.1
0
0 T2CON.7
1/12 TL2 TH2 TF2
1
T2=P1.0
Timer2
TR2=T2CON.2
Interrupt
RCAP2L RCAP2H
T2EX=P1.1
EXF2
T2CON.6
EXEN2=T2CON.3
registers. The next down count following the case where the contents of Timer/Counter equal the
capture registers will load an FFFFh into Timer/Counter 2. In either event a reload will set the TF2 bit.
A reload will also toggle the EXF2 bit. However, the EXF2 bit can not generate an interrupt while in this
mode.
Fcpu C/T2=T2CON.1
0 T2CON.7
0
1/12 TF2 Timer2
TL2 TH2
1
Interrupt
T2=P1.0
TR2=T2CON.2
RCAP2L RCAP2H
T2CON.6
Timer2
TL2 TH2
1
Overflow
T2=P1.0
TR2=T2CON.2
RCAP2L RCAP2H
T2EX=P1.1
EXF2 Timer2
Interrupt
T2CON.6
EXEN2=T2CON.3
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Preliminary N79E352/N79E352R Data Sheet
Timer2
Fcpu 1/2 Overflow
TL2 TH2 1/2 T2=P1.0
TR2=T2CON.2
RCAP2L RCAP2H
T2EX=P1.1
EXF2 Timer2
Interrupt
T2CON.6
EXEN2=T2CON.3
13.1 Operation
User is required to enable EnNVM (NVMCON.5) bit for NVM read. This is due to overlapping of NVM
data memory and external data memory physical address, the following table is defined. EnNVM bit
(NVMCON.5) will enable read access to NVM data memory area.
EnNVM Data Memory Area
0 Enable External RAM read/write access by
MOVX
1 Enable NVM data Memory read access by
MOVX only. If EER or EWR is set and NVM
flash erase or write control is busy, to set this
bit read NVM data is invalid.
Table 13-1: MOVX instruction to Enable Read Data Memory Area Definition Table
The NVM memory can be read/write by customer program to access. Read NVM data is by MOVX
A,@DPTR/R0/R1 instructions, and write data is by SFR of NVMADDR, NVMDAT and NVMCON.
Before write data to NVM memory, the page must be erased by providing page address on
NVMADDR, which address of On-Chip Code Memory space will decode, then set EER of NVMCON.7.
This will automatically hold fetch program code and PC Counter, and execute page erase. After
finished, this bit will be cleared by hardware. The erase time is ~ 5ms.
For writing data to NVM memory, user must set address and data to NVMADDR and NVMDAT, then
set EWR of NVMCON.6 to initiate nvm data write. The uC will hold program code and PC Counter, and
then write data to mapping address. Upon write completion, the EWR bit will be cleared by hardware,
the uC will continue execute next instruction. The program time is ~50us.
NVM data Flash Memory is permanently operating from 11.0592MHz internal clock source. In order to
reduce power consumption, the on chip oscillator will only be enabled when during program or erase,
through EWR or EER in NVMCON SFR. EWR or EER bits are cleared by hardware after program or
erase completed. The program/erase time is automatically controlled by hardware.
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Preliminary N79E352/N79E352R Data Sheet
Internal Signal
EnNVM
For security purposes this NVM data flash provide an independent “Lock bit” located in Security bits, it
is used to protect the customer’s data code in NVM. It may be enabled in CONFIG1.6 after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, NVM Flash
EPROM data can not be accessed again by hardware writer mode.
20KHz+/- Time-Out
15-bits Counter (WDCON.3)
100% RC Selector
Oscillator 00 WDIF
/Enable 0 5 Interrupt
(Security Bit) 01
WDTCK 6 8
EWDI
10 MUX (EIE.4) (WDCON.2)
Fcpu 9 12
WDRUN 11 WTRF
(WDCON.7) 13 14
512 clock
WDCLR WD1,WD0 delay Reset
(Reset Watchdog) (CKCON.7~6)
EWRST
(WDCON.0)
(WDCON.1)
The Watchdog Timer should first be restarted by using WDCLR. This ensures that the timer starts
from a known state. The WDCLR bit is used to restart the Watchdog Timer. This bit is self clearing, i.e.
after writing a 1 to this bit the software will automatically clear it. The Watchdog Timer will now count
clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and
CKCON.6). When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set.
After the time-out has occurred, the Watchdog Timer waits for an additional 512 clock cycles. If the
Watchdog Reset EWRST (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no
WDCLR, a system reset due to Watchdog Timer will occur. This will last for two machine cycles, and
the Watchdog Timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the
Watchdog was the cause of the reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a
time-out and the WDCLR allows software to restart the timer. The Watchdog Timer can also be used
as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an
interrupt will occur if the global interrupt enable EA is set.
The main use of the Watchdog Timer is as a system monitor. This is important in real-time control
applications. In case of some power glitches or electro-magnetic interference, the processor may begin
to execute errant code. If this is left unchecked the entire system may crash. Using the watchdog timer
interrupt during software development will allow the user to select ideal watchdog reset locations. The
code is first written without the watchdog interrupt or reset. Then the Watchdog interrupt is enabled to
identify code locations where interrupt occurs. The user can now insert instructions to reset the
Watchdog Timer, which will allow the code to run without any Watchdog Timer interrupts. Now the
Watchdog Timer reset is enabled and the Watchdog interrupt may be disabled. If any errant code is
- 80 -
Preliminary N79E352/N79E352R Data Sheet
executed now, then the reset Watchdog Timer instructions will not be executed at the required instants
and Watchdog reset will occur.
The Watchdog Timer time-out selection will result in different time-out values depending on the clock
speed. The reset will occur, when enabled, 512 clocks after the time-out has occurred.
6
The default Watchdog time-out is 2 clocks, which is the shortest time-out period. The EWRST, WDIF
and WDCLR bits are protected by the Timed Access procedure. This prevents software from
accidentally enabling or disabling the watchdog timer. More importantly, it makes it highly improbable
that errant code can enable or disable the Watchdog Timer.
The security bit WDTCK is located at bit 7 of CONFIG0 register. This bit is for user to configure the
clock source of watchdog timer either from the internal RC or from the uC clock.
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Preliminary N79E352/N79E352R Data Sheet
SM2 0 1 TX CLOCK TI
Serial Interrupt
RI
RX CLOCK
TXD
SHIFT CLOCK
P3.1 Alternate
Output Function
RI
LOAD SBUF
REN
RX START
RX SHIFT
Read SBUF
Serial Controllor CLOCK Internal
PAROUT SBUF Data Bus
RXD SIN
P3.0 Alternate
Input Function
The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive
data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch
data on the rising edge of shift clock. The external device should therefore present data on the falling
edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag is set
in C1 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI is
cleared by software.
15.2 Mode 1
In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of
10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes into RB8 in the SFR SCON. The baud rate in this
mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow or
1/16 of Timer 2 overflow. Since the Timer 1 and 2 can be set to different reload values, a wide variation
in baud rates is possible.
Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following
the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the next
rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16 counter
and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is
transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will be
at the 10th rollover of the divide by 16 counter after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with
the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line,
sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by
16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by
16 counter.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then
this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks
for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also
detected and shifted into the SBUF.
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and
RI is set. However certain conditions must be met before the loading and setting of RI can be done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
0 1 TX START TX SHIFT
TCLK
1/16 TX CLOCK
0 1
RCLK
Serial
1/16 TI
Controllor Serial Interrupt
RX CLOCK
RI
SAMPLE
1-To-0 LOAD SBUF
RX START
DETECTOR RX SHIFT Read SBUF
SBUF Internal
CLOCK PAROUT
Data Bus
BIT
RXD SIN D8 RB8
DETECTOR
Receive Shift Register
15.3 Mode 2
This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional
description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a
programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is
programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in
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Preliminary N79E352/N79E352R Data Sheet
PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at
C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1
following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the
divide by 16 counter, and not directly to the write to SBUF signal. After all 9 bits of data are transmitted,
the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD
pin. This will be at the 11th rollover of the divide by 16 counter after a write to SBUF. Reception is
enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection
of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sampling it at
the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 counter is
immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 counter.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port.
Fcpu/2 STOP
TB 8 D8
Internal
Write to PARIN
Data Bus SOUT TXD
SBUF START
1/ 2
LOAD
SMOD 0 1 CLOCK
TX START TX SHIFT
1 / 16 TX CLOCK
Serial
1 / 16
TI
Controllor
Serial Interrupt
RX CLOCK
RI
SAMPLE
1 - To - 0 LOAD SBUF
RX START
DETECTOR RX SHIFT Read SBUF
SBUF Internal
CLOCK PAROUT
Data Bus
BIT
RXD SIN D8 RB 8
DETECTOR
Receive Shift Register
Figure 15-3: Uart Serial Port Mode 2
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,
and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.
If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. After
shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is
set. However certain conditions must be met before the loading and setting of RI can be done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
Publication Release Date: Jul, 29, 2009
- 85 - Revision A06
Preliminary N79E352/N79E352R Data Sheet
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
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Preliminary N79E352/N79E352R Data Sheet
15.4 Mode 3
This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user
must first initialize the Serial related SFR SCON before any communication can take place. This
involves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3
are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a
clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the
incoming start bit if REN = 1. The external device will start the communication by transmitting the start
bit.
1/16
Serial
TI
Controllor Serial Interrupt
RX CLOCK
RI
SAMPLE
SBUF Internal
CLOCK PAROUT
Data Bus
BIT
RXD SIN D8 RB8
DETECTOR
Receive Shift Register
- 88 -
Preliminary N79E352/N79E352R Data Sheet
The following example shows how the user can define the Given Address to address different slaves.
Slave 1:
SADDR 1010 0100
SADEN 1111 1010
Given 1010 0x0x
Slave 2:
SADDR 1010 0111
SADEN 1111 1001
Given 1010 0xx1
The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it
is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate only
with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to
communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The
bit 3 position is don't care for both the slaves. This allows two different addresses to select both slaves
(1010 0001 and 1010 0101).
The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result are
defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the
Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two
SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX
XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature,
since any selectivity is disabled.
SDA
tBUF
tLOW
tr tf
SCL
tHIGH
tHD;STA tSU;STA tSU;STO
tHD;DAT tSU;DAT
The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode
specification. The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers,
and a status register (I2STATUS) reflects the status of the I2C bus.
The I2C port, SCL and SDA are at P1.2 and P1.3. When the I/O pins are used as I2C port, user must
set the pins to logic high in advance. When I2C port is enabled by setting ENS to high, the internal
states will be controlled by I2CON and I2C logic hardware. Once a new status code is generated and
stored in I2STATUS, the I2C interrupt flag (SI) will be set automatically. If both EA and EI2C are also in
logic high, the I2C interrupt is requested. The 5 most significant bits of I2STATUS stores the internal
state code, the lowest 3 bits are always zero and the content keeps stable until SI is cleared by
software.
16.1 I2C Bus
The I2C bus is a serial I/O port, which supports all transfer modes from and to the I2C bus. The I2C
port handles byte transfers autonomously. To enable this port, the bit ENSI in I2CON should be set to
'1'. The CPU interfaces to the I2C port through the following six special function registers: I2CON
(control register, C0H), I2STATUS (status register, BDH), I2DAT (data register, BCH), I2ADDR
(address registers, C1H), I2CLK (clock rate register BEH) and I2TIMER (Timer counter register, BFH).
The H/W interfaces to the I2C bus via two pins: SDA (P1.2, serial data line) and SCL (P1.3, serial clock
line). Pull up resistor is needed for Pin P1.2 and P1.3 for I2C operation as these are 2 open drain pins
(on I2C mode).
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Preliminary N79E352/N79E352R Data Sheet
The data baud rate of I2C setting is Data Baud Rate of I2C = Fcpu / (I2CLK+1). The Fcpu=Fosc/4. If
Fosc = 16MHz, the I2CLK = 40(28H), so data baud rate of I2C = 16MHz/(4X (40 +1)) = 97.56Kbits/sec.
The block diagram is as below figure.
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Preliminary N79E352/N79E352R Data Sheet
Fcpu 0
DIV4
SI
ENS1
ENTI
SI
- 94 -
Preliminary N79E352/N79E352R Data Sheet
08H
A START has been
transmitted.
(STA,STO,SI,AA)=(0,0,0,X)
SLA+W will be transmitted;
ACK bit will be received.
18H
SLA+W will be transmitted;
ACK bit will be received.
or
20H
SLA+W will be transmitted;
NOT ACK bit will be received.
(STA,STO,SI,AA)=(0,0,0,X) (STA,STO,SI,AA)=(0,1,0,X)
(STA,STO,SI,AA)=(1,0,0,X) (STA,STO,SI,AA)=(1,1,0,X)
Data byte will be transmitted; A STOP will be transmitted;
A repeated START will be transmitted; A STOP followed by a START will
ACK will be received. STO flag will be reset.
be transmitted;
STO flag will be reset.
28H 10H
Send a STOP
Data byte in S1DAT has been transmitted; A repeated START has
been transmitted. Send a STOP
ACK has been received.
followed by a START
or
30H
Data byte in S1DAT has been transmitted;
NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,0,X)
SLA+R will be transmitted;
38H
ACK bit will be transmitted;
Arbitration lost in SLA+R/W or
SIO1 will be switched to MST/REC mode.
Data byte.
To Master/Receiver (A)
(STA,STO,SI,AA)=(0,0,0,X) (STA,STO,SI,AA)=(1,0,0,X)
I2C bus will be release; A START will be transmitted when the
Not address SLV mode will be entered. bus becomes free.
Enter NAslave
Send a START
when bus becomes free
08H
A START has been
transmitted.
(STA,STO,SI,AA)=(0,0,0,X)
SLA+R will be transmitted;
ACK bit will be received.
48H 40H
SLA+R has been transmitted; SLA+R has been transmitted;
NOT ACK has been received. ACK has been received.
(STA,STO,SI,AA)=(0,0,0,0) (STA,STO,SI,AA)=(0,0,0,1)
Data byte will be received; Data byte will be received;
NOT ACK will be returned. ACK will be returned.
58H 50H
Data byte has been received; Data byte has been received;
NOT ACK has been returned. ACK has been returned.
(STA,STO,SI,AA)=(0,1,0,X)
(STA,STO,SI,AA)=(1,1,0,X) (STA,STO,SI,AA)=(1,0,0,X)
A STOP will be transmitted;
A STOP followed by a START will A repeated START will be transmitted;
STO flag will be reset.
be transmitted;
STO flag will be reset.
38H
(STA,STO,SI,AA)=(0,0,0,X)
Arbitration lost in NOT ACK
SLA+R will be transmitted;
bit.
ACK bit will be transmitted;
SIO1 will be switched to MST/REC mode.
To Master/Transmitter (B)
(STA,STO,SI,AA)=(1,0,0,X) (STA,STO,SI,AA)=(0,0,0,X)
A START will be transmitted; I2C bus will be release;
when the bus becomes free Not address SLV mode will be entered.
- 96 -
Preliminary N79E352/N79E352R Data Sheet
Set AA
A8H
Own SLA+R has been received;
ACK has been return.
or
B0H
Arbitration lost SLA+R/W as master;
Own SLA+R has been received;
ACK has been return.
(STA,STO,SI,AA)=(0,0,0,0) (STA,STO,SI,AA)=(0,0,0,1)
Last data byte will be transmitted; Data byte will be transmitted;
ACK will be received. ACK will be received.
C8H
C0H B8H
Last data byte in S1DAT has been transmitted;
Data byte or Last data byte in S1DAT has been Data byte in S1DAT has been transmitted;
ACK has been received.
transmitted; ACK has been received.
NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,0,0)
Last data will be transmitted; (STA,STO,SI,AA)=(0,0,0,1)
ACK will be received. Data byte will be transmitted;
ACK will be received.
A0H
A STOP or repeated START has been
received while still addressed as SLV/TRX.
(STA,STO,SI,AA)=(1,0,0,1) (STA,STO,SI,AA)=(1,0,0,0)
(STA,STO,SI,AA)=(0,0,0,1) (STA,STO,SI,AA)=(0,0,0,0)
Switch to not address SLV mode; Switch to not addressed SLV mode;
Switch to not addressed SLV mode; Switch to not addressed SLV mode;
Own SLA will be recognized; No recognition of own SLA;
Own SLA will be recognized. No recognition of own SLA.
A START will be transmitted when the A START will be transmitted when the
bus becomes free. becomes free.
Enter NAslave
Send a START
when bus becomes free
Set AA
60H
Own SLA+W has been received;
ACK has been return.
or
68H
Arbitration lost SLA+R/W as master;
Own SLA+W has been received;
ACK has been return.
(STA,STO,SI,AA)=(0,0,0,0) (STA,STO,SI,AA)=(0,0,0,1)
Data byte will be received; Data byte will be received;
NOT ACK will be returned. ACK will be returned.
80H
88H Previously addressed with own SLA address;
Previously addressed with own SLA address; Data has been received;
NOT ACK has been returned. ACK has been returned.
(STA,STO,SI,AA)=(0,0,0,0) (STA,STO,SI,AA)=(0,0,0,1)
Data will be received; Data will be received;
NOT ACK will be returned. ACK will be returned.
A0H
A STOP or repeated START has been
received while still addressed as SLV/REC.
(STA,STO,SI,AA)=(1,0,0,1) (STA,STO,SI,AA)=(1,0,0,0)
(STA,STO,SI,AA)=(0,0,0,1) (STA,STO,SI,AA)=(0,0,0,0)
Switch to not address SLV mode; Switch to not addressed SLV mode;
Switch to not addressed SLV mode; Switch to not addressed SLV mode;
Own SLA will be recognized; No recognition of own SLA;
Own SLA will be recognized. No recognition of own SLA.
A START will be transmitted when A START will be transmitted when the
the bus becomes free. becomes free.
Enter NAslave
Send a START
when bus becomes free
- 98 -
Preliminary N79E352/N79E352R Data Sheet
Set AA
70H
Reception of the general call address
and one or more data bytes;
ACK has been return.
or
78H
Arbitration lost SLA+R/W as master;
and address as SLA by general call;
ACK has been return.
(STA,STO,SI,AA)=(X,0,0,0) (STA,STO,SI,AA)=(X,0,0,1)
Data byte will be received; Data byte will be received;
NOT ACK will be returned. ACK will be returned.
98H 90H
Previously addressed with General Call; Previously addressed with General Call;
Data byte has been received; Data has been received;
NOT ACK has been returned. ACK has been returned.
(STA,STO,SI,AA)=(X,0,0,0) (STA,STO,SI,AA)=(X,0,0,1)
Data will be received; Data will be received;
NOT ACK will be returned. ACK will be returned.
A0H
A STOP or repeated START has been
received while still addressed as
SLV/REC.
(STA,STO,SI,AA)=(1,0,0,1) (STA,STO,SI,AA)=(1,0,0,0)
(STA,STO,SI,AA)=(0,0,0,1) (STA,STO,SI,AA)=(0,0,0,0)
Switch to not address SLV mode; Switch to not addressed SLV mode;
Switch to not addressed SLV mode; Switch to not addressed SLV mode;
Own SLA will be recognized; No recognition of own SLA;
Own SLA will be recognized. No recognition of own SLA.
A START will be transmitted when A START will be transmitted when the
the bus becomes free. becomes free.
Enter NAslave
Send a START
when bus becomes free
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Preliminary N79E352/N79E352R Data Sheet
In the first two examples, the writing to the protected bits is done before the 3 machine cycle window
closes. In Example 3, however, the writing to the protected bit occurs after the window has closed, and
so there is effectively no change in the status of the protected bit. In Example 4, the second write to TA
occurs 4 machine cycles after the first write, therefore the timed access window in not opened at all,
and the write to the protected bit fails.
18. INTERRUPTS
N79E352(R) has four priority level interrupts structure with 11 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can
be globally enabled or disabled.
18.1 Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, programmable
through bits IT0 and IT1 (SFR TCON). The bits IE0 and IE1 in TCON register are the flags which are
checked to generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every
machine cycle. If the sample is high in one cycle and low in the next, then a high to low transition is
detected and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since
the external interrupts are sampled every machine cycle, they have to be held high or low for at least
one complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If
the level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt
is serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced. The Watchdog timer can be used as a system monitor or a simple
timer. In either case, when the time-out count is reached, the Watchdog Timer interrupt flag WDIF
(WDCON.3) is set. If the interrupt is enabled by the enable bit EIE.4, then an interrupt will occur.
The timer 2 interrupt is generated through TF2 (timer 2 overflow/compare match). The hardware does
not clear these flags when a timer 2 interrupt is executed.
The uart serial block can generate interrupt on reception or transmission. There are two interrupt
sources from the uart block, which are obtained by the RI and TI bits in the SCON SFR. These bits are
not automatically cleared by the hardware, and the user will have to clear these bits using software.
This device also provide an independent I2C serial port. When new I2C state is present in I2STATUS,
the SI flag is set by hardware, and if EA and EI2 bits are both set, the I2C interrupt is requested. SI
must be cleared by software.
Keyboard interrupt is generated when any of the keypad connected to P0 pins is pressed. Each keypad
interrupt can be individually enabled or disabled. User will have to software clear the flag bit.
The input capture 0 interrupt is generated through CPTF0 flag. CPTF0 flag is set by input capture
events. The hardware does not clear this flag when the capture interrupt is executed. Software has to
clear the flag.
Brownout detect can cause brownout flag, BOF, to be asserted if power voltage drop below brownout
voltage level. Interrupt will occur if BOI (AUXR1.5), EBO (EIE.6) and global interrupt enable are set.
Source Vector Address Source Vector Address
External Interrupt 0 0003H Timer 0 Overflow 000BH
External Interrupt 1 0013H Timer 1 Overflow 001BH
Serial Port 0023H Brownout Interrupt 002BH
I2C Interrupt 0033H KBI Interrupt 003BH
Timer 2 Overflow 0043H - 004BH
Watchdog Timer 0053H - 005BH
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Preliminary N79E352/N79E352R Data Sheet
N79E352(R) uses a four priority level interrupt structure. This allows great flexibility in controlling the
handling of the interrupt sources.
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPXH IPX
0 0 Level 0 (lowest priority)
0 1 Level 1
1 0 Level 2
1 1 Level 3 (highest priority)
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IE
or EIE. The IE register also contains a global disable bit, EA, which disables all interrupts at once.
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service routine in progress can be
interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The
highest priority interrupt service cannot be interrupted by any other interrupt source. So, if two requests
of different priority levels are received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. This is called the arbitration ranking. Note that the arbitration
ranking is only used to resolve simultaneous requests of the same priority level.
Table below summarizes the interrupt sources, flag bits, vector address, enable bits, priority bits,
arbitration ranking, and whether each interrupt may wake up the CPU from Power Down mode.
Source Flag Vector Enable Flag Priority Arbitration Power-
address bit cleared by bit ranking down
wakeup
External IE0 0003H EX0 Hardware, IP0H.0, 1(highest) Yes
Interrupt 0 (IE.0) Software IP0.0
Brownout BOF 002BH EBO Hardware IP1H.6, 2 Yes
Detect (EIE.6) IP1.6
Watchdog WDIF 0053H EWDI Software IP1H.4, 3 Yes
Timer (EIE.4) IP1.4
Timer 0 TF0 000BH ET0 Hardware, IP0H.1, 4 No
Overflow (IE.1) Software IP0.1
I2C SI + TIF 0033h EI2 Software IP1H.0, 5 No
Interrupt (EIE.0) IP1.0
External IE1 0013H EX1 Hardware, IP0H.2, 6 Yes
Interrupt 1 (IE.2) Software IP0.2
KBI KBF 003BH EKB Software IP1H.1, 7 Yes
(EIE.1) IP1.1
Timer 1 TF1 001BH ET1 Hardware, IP0H.3, 8 No
Overflow (IE.3) Software IP0.3
UART RI + TI 0023H ES Software IP0H.4, 9 No
(IE.4) IP0.4
- 104 -
Preliminary N79E352/N79E352R Data Sheet
Since the external interrupt pins are sampled once each machine cycle, an input high or low should
hold for at least 6 CPU Clocks to ensure proper sampling. If the external interrupt is high for at least
one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the
transition is seen and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU
when the service routine is called.
If the external interrupt is level-activated, the external source must hold the request active until the
requested interrupt is actually generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is not necessary to clear the interrupt
flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the device is put into Power Down or Idle mode, the interrupt
will cause the processor to wake up and resume operation. Refer to the section on Power
Management for details.
IE0
EX0
IE1
EX1
BOF
EBO
KBF
EKB
Wakeup
(If in Power Down)
WDIF
EWDI TF0
ET0
EA Interrupt
TF1 to CPU
ET1
RI + TI
ES
SI
EI2
CPTF0
ECPTF
TF2
ET2
- 106 -
Preliminary N79E352/N79E352R Data Sheet
connected to specific pins of the N79E352(R), as shown below figure. This interrupt may be used to
wake up the CPU from Idle or Power Down modes, after chip is in Power Down or Idle Mode.
Keyboard function is supported through by Port 0. It can allow any or all pins of Port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits of KBI0 ~ KBI7 in the KBI register, as
shown below figure. The Keyboard Interrupt Flag (KBF) in the AUXR1 register is set when any enabled
pin is triggered while the KBI interrupt function is active, and the low pulse must be more than 1
machine cycle, an interrupt will be generated if it has been enabled. The KBF bit set by hardware and
must be cleared by software. In order to determine which key was pressed, the KBI will allow the
interrupt service routine to poll port 0.
The N79E352(R) has addition SFR KBL level configuration register to control either a low or high level
trigger.
KBL.7
High/low
P0.7
level
KBL.6 KBI.7
High/low
P0.6
level
KBI.6
KBL.5
High/low
P0.5
level
KBL.4 KBI.5
High/low
P0.4
level
KBI.4 KBF (KBI
KBL.3 Interrupt)
High/low
P0.3 EKB
level
KBI.3 (From EIE Register)
KBL.2
High/low
P0.2
level
KBL.1 KBI.2
High/low
P0.1
level
KBL.0 KBI.1
High/low
P0.0
level
KBI.0
SET
J Q Tx filtered
Tx D
SET
Q D
SET
Q D
SET
Q D
SET
Q
K Q
CLR
CLR
Q CLR
Q CLR
Q CLR
Q
Clk
The interval between pulses requirement for input capture is 1 machine cycle width, which is the same
as the pulse width required to guarantee a trigger for all trigger edge mode. For less than 3 system
clocks, anything less than 3 clocks will not have any trigger and pulse width of 3 or more but less than
4 clocks will trigger but will not guarantee 100% because input sampling is at stage C3 of the machine
cycle.
The trigger option is programmable through CCT0[1:0] (CAPCON0[3:2]). It supports positive edge,
negative edge and both edge triggers. The capture module consists of an enable, ICEN0 (T2MOD.4).
Timer/Counter 0 needs to be configured as mode 0 or 1 recommanded. It’s content will transfer to
CCL0 and CCH0 SFR when CPTF0 is set. If ICEN0 is enabled, each time the external pin trigger, the
content TL0 and TH0 (from Timer 0 block) will be captured/transferred into the capture registers, CCL0
and CCH0, depending which external pin trigger. This action also causes the CPTF0 flag bit in
CAPCON1 to be set, which will also generate an interrupt (if enabled by ECPTF bit in SFR EIE.7). The
flag is set by hardware and cleared by software.
Setting the T0CC bit (CAPCON1.6), will allow hardware to reset timer 0 automatically after the value of
TL0 and TH0 have been captured.
- 108 -
Preliminary N79E352/N79E352R Data Sheet
Capture 0 Block
CCL 0 CCH 0
CAPCON0.CCT0.1~0
Edge Select
CPTF0
With [00 ]
CAPCON1.ENF0
Schmitt
Trigger
T0 Noise [01 ]
(P3.4) Filter
T2MOD.ICEN0
[10 ]
Timer 0
CAPCON1.T0CC (recommanded mode 0 or 1)
(Timer 0 count clear enable)
Vdd P1.4
A compare value of all zeroes, 00H, causes the output to remain permanently high. A compare value of
all ones, FFH, results in the PWM output remaining permanently low.
The overall functioning of the PWM module is controlled by the contents of the PWMCON1 and
PWMCON3 registers. The operation of most of the control bits are straightforward. The transfer
Compare registers to the buffer registers is controlled by 8-bit counter overflow, while PWMCON1.7
(PWMRUN) allows the PWM to be either in the run or idle state. It has a CLRPWM bit to clear 8-bt up
counter.
When the PWMRUN is cleared, the PWM outputs take on the state they had just prior to the bit being
cleared. In general this state is not known. In order to place the outputs in a known state when
PWMRUN is cleared the Compare registers can be written to either the “all 1” or “all 0” so the output
will have the output desired when the counter is halted.
Note:
During PWM initial run, user is recommended to configure proper PWMn and/or PWM output pin (default high) follow by setting
PWMRUN and CLRPWM bits, prior to enable PWMnOE. This is to avoid unexpected PWM output.
- 110 -
Preliminary N79E352/N79E352R Data Sheet
The default port output configuration for standard N79E352(R) I/O ports is the quasi-bidirectional
output that is common on the 80C51 and most of its derivatives. This output type can be used as both
an input and output without the need to reconfigure the port. This is possible because when the port
outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is
pulled low, it is driven strongly and able to sink a fairly large current. These features are somewhat
similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional
output that serve different purposes. One of these pull-ups, called the “very weak” pull-up, is turned on
whenever the port latch for the pin contains a logic 1. The very weak pull-up sources a very small
current that will pull the pin high if it is left floating.
A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains a logic
1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a
quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external
device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin
low under these conditions, the external device has to sink enough current to overpower the weak pull-
up and take the voltage on the port pin below its input threshold.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-high
transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1.
When this occurs, the strong pull-up turns on for a brief time, two CPU clocks, in order to pull the port
pin high quickly. Then it turns off again. The quasi-bidirectional port configuration is shown as below.
VDD
2 CPU
P P Very P
Clock Delay Strong
Weak
Weak
Port Pin
Port Latch N
Data
Input Data
- 112 -
Preliminary N79E352/N79E352R Data Sheet
Port Pin
Port Latch N
Data
Input Data
VDD
Port Pin
Port Latch N
Data
Input Data
Schmitt-triggered or TTL
- 114 -
Preliminary N79E352/N79E352R Data Sheet
23. OSCILLATOR
N79E352(R) provides three oscillator input option. These are configured at CONFIG register
(CONFIG0) that include On-Chip RC Oscillator Option, External Clock Input Option and Crystal
Oscillator Input Option. The Crystal Oscillator Input frequency may be supported from 4MHz to 24MHz,
and without capacitor or resister.
XTAL1
External Oscillating
00
XTAL Circuit
XTAL2
Ext Clock 11 Fosc
CPU Clock Fcpu
Rate select
FRC22M
1
10
FRC11M
1/2 0
CD0 CD1
PMR[1:0]
FOSC1
FS1 FOSC0
(CONFIG1.5)
Internal
Oscillator Timers, UART
(22.1184MHz)
PWM, I2C
WDT
Internal
Oscillator
(~20kHz)
BOD
For BOD in
power-saving
mode
ISP
Idle, saving additional power. The clock output may also be enabled when the external clock input
option is selected.
- 116 -
Preliminary N79E352/N79E352R Data Sheet
BOS
BOV[1:0]
BOD Brownout 0 To Reset
LPBOV
Detect BOF
Circuit 1 To Brownout interrupt
BOI
VDD
Brown-out Status
BOS
- 118 -
Preliminary N79E352/N79E352R Data Sheet
Vcc
Vpp RST
To Reset or Input Pin
Data P1.6
To I/O pin
Clock P1.7
To I/O pin
Vss Vss
N79E352(R)
System Board
Figure 26-1: ICP Writer Tool connector pin assign
Note:
1. When using ICP to upgrade code, the RST, P1.6 and P1.7 must be taken within design system
board.
2. After program finished by ICP, to suggest system power must power off and remove ICP
connector then power on.
3. It is recommended that user performs erase function and programming configure bits
continuously without any interruption.
4. During ICP mode, all PWM pins will be tri-stated.
26.1 CONFIG0
7 6 5 4 3 2 1 0
4 - Reserved.
Config Brownout Detect Enable bit
3 CBOD 0: Disable Brownout Detect.
1: Enable Brownout Detect.
Bypass Clock Filter.
2 BPFR 0: Disable Clock Filter.
1: Enable Clock Filter.
1 Fosc1 CPU Oscillator Type select bit 1.
- 120 -
Preliminary N79E352/N79E352R Data Sheet
26.2 CONFIG1
7 6 5 4 3 2 1 0
C7 C6 FS1 - CBOV.1-0 C1 -
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
- 122 -
Preliminary N79E352/N79E352R Data Sheet
- 124 -
Preliminary N79E352/N79E352R Data Sheet
Sink Current P0, P1, P2, P3, P4, 13 18.5 24 mA VDD = 4.5V, VS = 0.45V
P5
ISK2
(Quasi-bidirectional and PUSH- 9 15 21 VDD = 2.4V, VS = 0.45V
PULL Mode)
Brownout voltage with BOV[1:0]
VBO2.4 2.55 2.6 2.85 V
=0xb
Brownout voltage with BOV[1:0]
VBO3.8 3.65 3.8 3.95 V
=10b
Brownout voltage with BOV[1:0]
VBO4.5 4.35 4.5 4.65 V
=11b
VDD = 2.4V~5.5V,
35 - 150 mV
(LPBOD,BOI) = (0,x) or (1,0)
Hysterisis range of BOD voltage VBh
VDD = 2.4V~5.5V,
10 - 60 mV
(LPBOD,BOI)=(1,1)
Sink current
[*2]
P0, P2, ALE, Isk31 -16 -26 -36 mA VDD=4.5V, Vs = 0.45V
/PSEN Isk32 -5 -7.9 -11 mA VDD=2.7V, Vs = 0.45V
Source current
[*2]
P0, P2, ALE, Isr31 13 18.5 24 mA VDD=4.5V, Vs = 2.4V
/PSEN Isr32 9 15 21 mA VDD=2.7V, Vs = 2.0V
Notes: *1. RST pin is a Schmitt trigger input. RST has internal pull-low resistor.
*2. XTAL1 is a CMOS input.
*3. Pins of P0, P1, P2, P3 and P5 can source a transition current when they are being externally driven from 1 to 0.
The transition current reaches its maximum value when Vin approximates to 2V.
tCLCL
tCLCH
tCLCX
tCHCL tCHCX
27.3.2 AC Specification
PARAMETER SYMBOL VARIABLE CLOCK MIN. VARIABLE CLOCK MAX. UNITS
Oscillator Frequency 1/tCLCL 0 24 MHz
tCLCL
tCLCH
tCLCX
tCHCL tCHCX
- 126 -
Preliminary N79E352/N79E352R Data Sheet
t AVIV1
t AVIV2
t LLDV
ALE
t WHLH
t LLWL
PSEN tRLRH
t LLAX1
tRLDV
RD t AVLL
t RHDZ
t RLAZ
t AVWL1
t RHDX
ALE
tWHLH
t LLWL
PSEN tWLWH
t LLAX2
WR t AVLL
t AVWL1
tWHQX
t QVWX
t AVDV2
- 128 -
Preliminary N79E352/N79E352R Data Sheet
Repeated
STOP START START STOP
SDA
tBUF
tLOW
tr tf
SCL
tHIGH
tHD;STA tSU;STA tSU;STO
tHD;DAT tSU;DAT
The above table shows the reference values for crystal applications.
C1
XTAL1
XTAL2
C2
N79E352(R)
- 130 -
Preliminary N79E352/N79E352R Data Sheet
1
E
1 20
S E
2
c
1
AA Base Plane
A
Seating Plane
L
B
e1 eA
α
B1
A1 0.010 0.25
A2 0.150 0.155 0.160 3.81 3.94 4.06
S 0.090 2.29
7 39
E E
E H G
17 29
18 28
c
L
2
A A
e b 1
A
Seating Plane b1 y
GD
- 132 -
Preliminary N79E352/N79E352R Data Sheet
44 34
1 33
E
E H
11
12 e 22
b
c
2
A A
1
0 0 10 0 10
- 134 -
Preliminary N79E352/N79E352R Data Sheet
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.