LD7591T

11/09/2012

Transition-Mode PFC Controller with Fault Condition Protection

REV. 00

General Description Features

The LD7591T is a voltage mode PFC controller operating  Transition mode of PFC pre-regulator
on transition mode, with several integrated functions of  Voltage mode control
protection, such as OVP, OCP, and Brown-in protection. It  Programmable max. on-time
reduces the components counts and is available in a  Low Startup Current (<30A)
SOP-8 or DIP-8 package. Those make it an ideal design  UVLO (Under Voltage Lockout)
for low cost applications.  LEB (Leading-Edge Blanking) on CS Pin
 Open-Feedback Protection and Disable Function
It provides functions of low startup current, over voltage
 OVP (Over Voltage Protection)
protection, open feedback protection, disable function,
 OCP (Cycle by cycle current limiting)
over current protection, under voltage lockout and
 800/-1200mA Driving Capability
integrated LEB of current sensing. Unlike the traditional
 Internal OTP function
current mode PFC controller, LD7591T is free from extra
rectified AC line voltage information to minimize the power Applications
loss.
 Adaptor of Output above 65W.
The LD7591T will be disabled if INV pin voltage falls  Open Frame Switching Power Supply
below 0.45V and the operating current rises over 65μA  LCD TV Power Supply
 LED Power Supply

Typical Application for Boost PFC

AC EMI
Input Filter

7
GATE
8 VCC

CS 4

LD7591T
5 ZCD
INV 1

3 RAMP COMP 2
GND
6

1
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Pin Configuration
SOP-8 & DIP-8 (TOP VIEW)

GND
VCC

OUT

ZCD
8 7 6 5

TOP MARK YY: Year code (D:2004, E:2005…)

WW: Week code
YYWWPP
PP: Production code

1 YYWWPP
2 3 4
INV

COMP

CS
RAMP

Ordering Information
Part number Package Top Mark Shipping

LD7591T GS SOP-8 LD7591TGS 2500 /tape & reel

LD7591T GN DIP-8 LD7591TGN 3600 /tube /Carton

The LD7591T is ROHS compliant/ Green Packaged.

Pin Descriptions
Pin NAME FUNCTION

1 INV Output voltage feed back control

2 COMP Output of the error amplifier for voltage loop compensation to achieve stable

3 RAMP Ramp generator, connecting a resistor to GND pin to set the saw tooth signal

4 CS Current sense pin, connect to sense the MOSFET current for OCP

5 ZCD Detecting zero crossing of input signal

6 GND Ground

7 OUT Gate drive output to drive the external MOSFET

8 VCC Power source VCC pin

Recommended Operating Conditions

Item Min. Max. Unit
Vcc pin capacitor 22 47 F
Comp pin capacitor 0.1 4.7 F
RAMP pin resistor 4.7k 100k 

2
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Block Diagram
VCC

VCC
OVP
21V

UVLO
VCC OK internal bias All
& Vref Blocks
12V/8.5V

Vref OK

Disable
Driver
Vref OK R Q
Stage
OUT
Burst
VCC Mode 13V
OVP S

Start
Timer

S Q
PWM
Ramp
Comparator
RAMP Generator
R
2.675V/
OCP OVP 2.5V
Comparator
Leading
CS Edge
Blanking
0.8V

Disable

0.45V/
0.35V

OSC TCR mode

Control
0.1V/0.2V

INV
GM Vref

Burst-
ZCD
Burst mode
Mode 0.95V/1.0V

GND COMP

3
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Absolute Maximum Ratings
Supply Voltage VCC -0.3 ~26V
OUT -0.3 ~VCC +0.3V
COMP, INV, CS, RAMP, ZCD -0.3 ~7V
Maximum Junction Temperature 150C
Operating Junction Temperature Range -40C to 125C
Operating Ambient Temperature Range -40C to 85C
Storage Temperature Range -65C to 150C
Package Thermal Resistance (SO-8, JA) 160C/W
Package Thermal Resistance (DIP-8, JA) 100C/W
Power Dissipation (SOT-8, at Ambient Temperature = 85C) 400mW
Power Dissipation (DIP-8, at Ambient Temperature = 85C) 650mW
Lead temperature (Soldering, 10sec) 260C
ESD Voltage Protection, Human Body Model 2.5 KV
ESD Voltage Protection, Machine Model 250 V
Gate Output Current 800mA/-1200mA

Caution:
Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.

4
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Electrical Characteristics
(VCC=14.0V, TA = 25C unless otherwise specified.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage (VCC Pin)
Startup Current VCC<UVLO ON 20 30 A
VCOMP=0V 2.0 mA
Operating Current VCOMP=3V 2.5 mA
(with 1nF load on OUT pin) VCC OVP 0.45 mA
VINV=0V 65 95 A
UVLO (off) 7.5 8.5 9.5 V
UVLO (on) 11.0 12.0 13.0 V
VCC OVP Level 19.5 21 22.5 V
Error Amplifier (Comp Pin)
Feedback Input Voltage, VREF 2.465 2.500 2.535 V
Input Bias Current VINV=1V~4V -0.5 0.5 A
Transconductance 140 mho
Output Sink Current VINV= VREF +0.05V 7 A
Output Source Current VINV= VREF -0.05V -7 A
Output Source Current VINV= VREF -1V -200 A
Output Upper Clamp Voltage VINV= VREF -0.1V 5.4 5.9 6.4 V
TCR Mode Frequency VCOMP=1.05V 70 90 110 KHz
Burst Mode COMP pin Threshold 0.95 V
Voltage Hysteresis 50 mV
INV pin
2.62 2.675 2.73 V
OVP Trip Level
OVP Hysteresis 0.175 V
0.4 0.45 0.5 V
Enable Threshold Voltage
Enable Hysteresis 0.1 V
Current Sensing (CS Pin)
Current Sense Input Threshold Voltage 0.75 0.8 0.85 V
Input bias current VCS=0V~1V 0 1.0 A
LEB time 250 ns
Zero Current Detector (ZCD Pin)
Upper Clamp Voltage IDET=100A 6.0 V
Lower Clamp Voltage IDET=100A -0.7 V
0.05 0.1 0.15 V
Input Voltage Threshold
Hysteresis 0.1 V

5
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input bias current VZCD=1V~4V, OUT=OFF 0.0 1.0 A
Maximum Delay from ZCD to Output 250 ns
Maximum ON-Time, Ton-max (Ramp Pin)
Maximum On Time Voltage RRAMP=40.5K 2.784 2.900V 3.016 V
Maximum On Time Programming RRAMP =40.5K 19 24 29 s
Maximum On Time RRAMP  100K 40 s
Minimum OFF-Time
Minimum OFF-Time 1 s
Ton-
Minimum OFF-Time Programming 0.10
max
Gate Drive Output (OUT Pin)
Output Low Level VCC=12V, ISINK=20mA 0.5 V
Output High Level VCC=12V, ISOURCE=20mA 9 12 V
Output High Clamp Level VCC=18V 13 V
Rising Time VCC =12V, CL=1000pF 75 150 ns
Falling Time VCC =12V, CL=1000pF 25 100 ns
Starter
Start Timer Period 50 150 300 s
OTP (Over Temp. Protection)
OTP Trip level 140 C
OTP Hysteresis 30 C

6
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Typical Performance Characteristics
10 13

9.5

12.5

UVLO (on) (V)

UVLO (off) (V)

8.5 12

11.5

7.5

7 11
-40 0 40 80 120 -40 0 40 80 120
Temperature (C) Temperature (C)
Fig. 1 UVLO (off) vs.Temperature Fig. 2 UVLO (on) vs.Temperature

3 1.3

2.9
1.2
2.8
1.1
2.7
1
INV-REF (V)

Vcs (off) (V)

2.6

2.5 0.9

2.4
0.8
2.3
0.7
2.2
0.6
2.1

2 0.5
-40 0 40 80 120 -40 0 40 80 120
Temperature (C) Temperature (C)
Fig. 3 INV-REF vs.Temperature Fig. 4 Vcs (off) vs.Temperature

7
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Application Information
Operation Overview the auxiliary winding of the PFC choke. Lower startup

The LD7591T is an excellent voltage mode PFC current requirement for the PFC controller will help to

controller. It meets the IEC61000-3-2 requirement and is increase the value of R1 and reduce the power

intended for the use in those pre-regulator that demand consumption on R1. By using CMOS process and the

low power harmonics distortion. It integrated more special circuit design, the maximum startup current of

functions to reduce the external components counts and LD7591T is only 30A. If a higher resistance value of R1

the size. Its major features are described as below. is chosen, it usually takes more time to start up. To
carefully select the value of R1 and C1 will optimize the
power consumption and startup time.
Under Voltage Lockout (UVLO)
Vin
R1
An UVLO comparator is implemented in it to detect the
voltage on the VCC pin. It would assure the supply Vout
C1
voltage enough to turn on the LD7591T PFC controllers
VCC
and further to drive the power MOSFET. As shown in
OUT
Fig. 5, a hysteresis is built in to prevent the shutdown
LD7591T
from the voltage dip during start up. The turn-on and
turn-off threshold level are set at 12.0V and 8.5V, CS
COMP GND
respectively. Rs
Vcc
Fig. 6
UVLO(on)
Output Voltage Setting
UVLO(off)
The LD7591T monitors the output voltage signal on INV
pin through a resistor divider pair of Ra and Rb. A
t transconductance amplifier is used to replace the
I(Vcc) operating current conventional voltage amplifier. The transconductance
(~ mA)
amplifier (voltage controlled current source) enhances the
implementation of OVP and disables function. The output
startup current
(~uA) current of the amplifier changes with the various voltage
t of the inverting and non-inverting input of the amplifier.
Fig. 5 The output voltage of the amplifier is compared with the

Startup Current and Startup Circuit internal ramp signal to generate the turn-off signal. The

The typical startup circuit to generate the LD7591T Vcc is output voltage is determined by the following relationship.
Ra
shown in Fig. 6. At the startup transient, the Vcc is lower VOUT  2.5V(1  )
Rb
than the UVLO threshold thus there is no gate pulse Where Ra and Rb are top and bottom feedback resistor
produced from LD7591T to drive power MOSFET. values (as shown in the Fig. 7).
Therefore, the current through R1 will provide the startup
current to charge the capacitor C1. When the Vcc voltage
is high enough to turn on the LD7591T and then it will
send a gate drive signal to draw the supply current from

8
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
INV
OVP 2.675V/
2.5V OVP Tripped
2.675V
Disable 2.5V
VOUT
0.45V/
0.35V
Vref
Ra
t
GM
Vout
INV
Rb Disable Vovp
Vnom

COMP
Non
Switching Switching
Fig. 7
t
Fig. 8
OVP and Disable on INV pin
To prevent the over-voltage on the output capacitor from
Zero Current Detection (ZCD)
the fault condition, LD7591T is implemented with an OVP
Fig. 9 shows typical ZCD-block. The Zero Current
function on INV pin. Once the INV voltage is higher than
Detection block will switch on the external MOSFET as
the OVP threshold voltage 2.675V, the output gate drive
the current through the boost inductor drops to zero in
circuit will be shut down simultaneously thus to stop the
using an auxiliary winding coupled with the inductor. This
switching of the power MOSFET until the INV pin down to
feature allows transition-mode operation. If the voltage of
2.5V. The OVP function in LD7591T is an auto-recovery
the ZCD pin goes higher than 0.2V, the ZCD comparator
type protection. The Fig. 8 shows its operation. On the
waits until the voltage rises above 0.1V. If the voltage
other hand, if the OVP condition is removed, the Vcc level
goes below 0.1V, the zero current detector will turn on the
will get back to normal level and the output will
MOSFET. The ZCD pin is protected internally by two
automatically return to the normal operation.
clamps, 6.0V-high clamp and -0.7V-low clamp. The
The disable comparator disables the operation of the
150s timer generates a MOSFET turn on signal if the
LD7591T when the voltage of the inverting input is lower
driver output has been low for more than 150s from the
than 0.35V and there is hysteresis of 100mV. An external
falling edge of the driver output.
small signal MOSFET can be used to disable the IC,
Turn-on
referring to Fig. 7. The IC operating current decreases Start Signal
Timer
below 65μA to reduce power consumption if the IC is 0.1V/0.2V
S Q’
disabled.
RZ1 ZCD
LS
R
RZ2

Fig. 9

9
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
IIN
Fig. 10 shows typical ZCD-related waveforms. Rz1 will L D VOUT
+
produce some delay because of the capacitance carried AC
- Q
by ZCD pin, it therefore delay the turn-on time accordingly. Co
CIN1
The switch will be turned on when the inductor current COSS
IL
reaches zero; because of the structure of the ZCD delay,
it will be turned on after some delay time. During this
Fig. 11
delay time, the stored charge of the COSS (MOSFET
output capacitor) will be discharged through the path Ramp Generator Block
indicated in Fig. 11. This charge is transferred into a small The output of the gm error amplifier and the output of the
filter capacitor CIN1, which is connected to the bridge ramp generator block are compared to determine the
diode. Therefore, there is no current flowing from the MOSFET on time, as shown in Fig. 12. The slope of the
input side. That is, the input current IIN is zero during this ramp is determined by an external resistor connected to
period. In order to reduce the negative current flowing to the RAMP pin. The voltage of the RAMP pin is 2.9V and
the internal diode, a larger resistance of RZ1 over 47k is the slope is proportional to the current flowing out of the

recommended. RAMP pin. The internal ramp signal has a 1V offset;

therefore, the drive output will be shut down if the voltage

OUT of the COMP pin is lower than 0.95V. The programmed

COMP on-time will be at its maximum when the COMP pin is
RAMP open. The COMP pin open voltage is about 5.4~6.4V.

IPEAK tzero According to the slope of the internal ramp, the maximum
0A on-time can be programmed. The necessary maximum
Inductor
Current
Ton Tdis
on-time will be achieved depending on the boost inductor,
INEG
lowest AC line voltage, and maximum output power. The
naux/np ∙ (VOUT – VIN)
resistor value should be designed properly. The

AUX maximum on-time can be obtained from below

0V
Voltage RRAMP
TON Time(MAX ) 
-naux/np ∙ VIN 1.58  109
Delay
Time
naux/np ∙ (VOUT –VIN)RZ2/(RZ1+RZ2)

ZCD 0.1V 1V Offest

Voltage
Ramp Saw
VOUT -0.7V-Clamp Tooth
Turn-off
2.9V Greneator Signal

VDS Comp
Minimum
Voltage
Turn-on 0V
Fig. 12

Fig. 10

10
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Output Drive Stage and PCB layout. It is strongly recommended to adopt a

An output stage of a CMOS buffer, with typical smaller R-C filter for higher power application to avoid the

800mA/-1200mA driving capability, is incorporated to CS pin being damaged by the negative turn-on spike.
250ns
drive a power MOSFET directly. The output voltage is
blanking
clamped at 13V to protect the MOSFET gate even when time
OUT
the VCC voltage is higher than 13V.

Current Sensing and Leading-edge OCP

Signal CS
Blanking
The typical voltage mode of PFC controller feedbacks the RS
voltage signals to close the control loop and achieve 0.8V

regulation. The LD7591T detects the primary MOSFET

Removable if the negative spike
current from the CS pin, which is for the pulse-by-pulse is not over spec. (-0.3V).

current limit. The maximum voltage threshold of the Fig. 13

current sensing pin is set at 0.8V. From above, the

Fault Protection
MOSFET peak current can be obtained from below.
There are several critical protections integrated in the
0.8V
IPEAK(MAX ) 
RS LD7591T to prevent the power supply or adapter from

A 250ns leading-edge blanking (LEB) time is included in being damaged. Those damages usually come from open

the input of CS pin to prevent the false-trigger from the or short condition on the pins of LD7591T.
Under the conditions listed below, the gate output will turn
current spike. The R-C filter may be eliminated in some
off immediately to protect the power circuit ---
low power applications, such as the pulse width of the
1. Ramp pin short to ground
turn-on spikes is below 250ns and the negative spike on
2. Ramp pin floating
the CS pin is below -0.3V.
3. CS pin floating
However, the pulse width of the turn-on spike is
determined according to the output power, circuit design

11
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
LD7591T
Reference Application Circuit --- 400V/100W (90~264VAC)

Fuse LF1 NTC LF2

DB C13 R13
C3
L1
AC T1
Input C1 C2 NP
V1 D2 C91 DC
C5 C5B C9 Output
C4 R61 D3 R10
Q1
R6 R10B
R9

www.leadtrend.com.tw
12
R3 R11 R12
RB4
R3B
C10 D1 CB2 R7
8 VCC GATE 7
R4
ZD1 C6 C61 CS 4
R5
NVcc LD7591T
5 ZCD INV 1
RZ2

Leadtrend Technology Corporation

C12
C11 3 RAMP COMP 2
GND
6
R8
R1 C7

LD7591T-DS-00 November 2012

C8
LD7591T
Reference Application Circuit --- LED -42V/350mA (90~264VAC)

Fuse LF1
C13 R13
NTC
AC C1 LF2 D2 LED+
T1
Input BD
R16 C2
C5 C5B C9
V1 C9A
R17 NP R12
D5 LED-
R61 D3 R12B
C16 R104B
R102

C102
R6 Q1 R104
R103
R9 Q2

C103
R3

www.leadtrend.com.tw
RB4

13
C101
D1 R4 R3B

R109
D4 CB2 R7 R105
8 VCC GATE 7

R110
C6 C62 C61 CS 4

D6
R5 C15 IC3
NVcc LD7591T
R15
INV 1 To Pin8 R112
5 ZCD
VCC

D7
R5B
C11 3 RAMP COMP 2
GND

Leadtrend Technology Corporation

C105
6 C14 R106

R108 C104
R1

R111
R14

LD7591T-DS-00 November 2012

C12
R15B IC2 IC3
PIN8

R107
 LD7591T
Package Information
SOP-8

Dimensions in Millimeters Dimensions in Inch

Symbols
MIN MAX MIN MAX

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.254 0.007 0.010
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
θ 0° 8° 0° 8°

14
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Package Information
DIP-8

Dimension in Millimeters Dimensions in Inches

Symbol
Min Max Min Max
A 9.017 10.160 0.355 0.400
B 6.096 7.112 0.240 0.280
C ----- 5.334 ------ 0.210
D 0.356 0.584 0.014 0.023
E 1.143 1.778 0.045 0.070
F 2.337 2.743 0.092 0.108
I 2.921 3.556 0.115 0.140
J 7.366 8.255 0.29 0.325
L 0.381 ------ 0.015 --------

Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers
should verify the datasheets are current and complete before placing order.

15
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012
 LD7591T
Revision History

Rev. Date Change notice

00 11/9/2012 Original specification

16
Leadtrend Technology Corporation www.leadtrend.com.tw
LD7591T-DS-00 November 2012