LD7523A

12/3/2008

Smart Green-Mode PWM Controller with Multiple Protections

REV: 01

General Description Features

The LD7523A is a low startup current, current mode PWM z High-Voltage CMOS Process with Excellent ESD
controller with green-mode power-saving operation. The protection
SOP-8/DIP-8 package integrates functions such as the z Very Low Startup Current (< 35μA)
leading- edge blanking of the current sensing, internal z Current Mode Control
z Non-audible-noise Green Mode Control
slope compensation, line compensation, and several
z UVLO (Under Voltage Lockout)
protection features including cycle-by-cycle current limit,
z LEB (Leading-Edge Blanking) on CS Pin
OVP, OTP, OLP, and brownout protection. It provides the
z Internal Slope Compensation
users a high efficiency, low external component counts
z Programmable Line Compensation
solution for AC/DC power applications. z OVP (Over Voltage Protection)
Furthermore, to satisfy various protection requirements, z OLP (Over Load Protection)
both latch-mode protection and auto-recoverable z OTP (Over Temperature Protection) through a NTC
z Brownout Protection
protection can be easily achieved by configuring LD7523A
z Flexibility on Latch/Auto-Recoverable Protection
on different operation modes.
Mode
The special green-mode control is not only to achieve the z 500mA Driving Capability
low power consumption but also to offer a
non-audible-noise operation when the LD7523A is Applications
operating under light load or no load condition. z Switching AC/DC Adaptor and Battery Charger
z Open Frame Switching Power Supply
z LCD Monitor/TV Power

Typical Application

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Pin Configuration
SOP-8 & DIP-8(TOP VIEW)

GND
OVP
VCC
OUT
8 7 6 5

YY : Year code (D: 2004, E: 2005…..)

TOP MARK WW : Week code
YYWWPP ## : Production code

1 2 3 4
(-)LATCH
BNO

COMP

CS

Ordering Information
Part number Package TOP MARK Shipping

LD7523A GS SOP-8 Green Package LD7523AGS 2500 /tape & reel

LD7523A GN DIP-8 Green Package LD7523AGN 3600/tube /carton

The LD7523A is ROHS Complaint/ Green Packaged.

Pin Descriptions
PIN NAME FUNCTION
Brownout Protection Pin. Connect a resistor divider from this pin to bulk
1 BNO capacitor voltage to set the brownout level and line compensation. When the
voltage of this pin is lower than a threshold voltage, the PWM output will be off.
Voltage feedback pin (same as the COMP pin in UC384X). Connecting a
2 COMP
photo-coupler to close the control loop and achieve the regulation.
Pulling this pin to lower than 2.5V will shutdown the controller to the latch mode
until the AC power-on recycling. Connecting a NTC from this pin to ground will
3 (-) LATCH
achieve the OTP protection function. Keep this pin floating to disable the latch
protection.
4 CS Current sense pin, for sensing the MOSFET current
5 GND Ground
6 OUT Gate drive output to drive the external MOSFET
7 VCC Supply voltage pin
This pin is high-active to provide the OVP function. Connecting a zener or a
resistor voltage divider to Vcc will set the OVP level. Whenever the voltage is
8 OVP
above 2.5V, the OVP is triggered and the gate drive will be off. Grounding this
pin disables the OVP function.

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Block Diagram

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Absolute Maximum Ratings
Supply Voltage VCC 30V
COMP, CS, (-) LATCH -0.3 ~7V
OVP, BNO -0.3 ~7V
Junction Temperature 150°C
Operating Ambient Temperature -40°C to 85°C
Storage Temperature Range -65°C to 150°C
Package Thermal Resistance (SOP-8) 160°C/W
Package Thermal Resistance (DIP-8) 100°C/W
Power Dissipation (SOP-8, at Ambient Temperature = 85°C) 400mW
Power Dissipation (DIP-8, at Ambient Temperature = 85°C) 650mW
Lead temperature (Soldering, 10sec) 260°C
ESD Voltage Protection, Human Body Model 2.5KV
ESD Voltage Protection, Machine Model 250V
Gate Output Current 500mA

Caution:
Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.

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Electrical Characteristics
(TA = +25oC unless otherwise stated, VCC=12.0V)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage (VCC Pin)
Startup Current 20 35 μA
VCOMP=0V 3.5 5.0 mA
Operating Current
VCOMP=3V 2.7 mA
(with 1nF load on OUT pin)
Protection Mode (note 1) 0.7 mA
UVLO (off) 9.0 9.75 10.7 V
UVLO (on) 12.0 12.75 13.5 V
Voltage Feedback (Comp Pin)
Short Circuit Current VCOMP=0V 2.5 4.0 mA
Green Mode Threshold VCOMP 2.35 V
Current Sensing (CS Pin)
VBNO=0V (note 2) 0.800 0.850 0.900 V
Maximum Input Voltage, VCS(OFF) VBNO=1.30V 0.748 0.798 0.848 V
VBNO=3.75V 0.650 0.700 0.750 V
Leading Edge Blanking Time 350 nS
Input impedance 1 MΩ
Delay to Output 150 nS
Gate Drive Output (OUT Pin)
Output Low Level VCC=15V, Io=20mA 1.0 V
Output High Level VCC=15V, Io=20mA 9.0 V
Rising Time Load Capacitance=1000pF 50 160 nS
Falling Time Load Capacitance=1000pF 30 60 nS
Oscillator
Frequency 60 65 70 KHz
Green Mode Frequency 20 KHz
Frequency Temp. Stability (-40°C –85°C) 3 %
Frequency Voltage Stability (VCC=12V-30V) 1 %
Latch Protection ((-)LATCH Pin)
(-)LATCH Pin Source Current 92 100 108 μA
Turn-On Trip Level 3.3 3.50 3.7 V
Turn-Off Trip Level 2.40 2.50 2.60 V
(-)LATCH pin de-bounce time 100 μS
De-latch Vcc Level (PDR, Power Down Reset) 6.8 8.0 8.7 V
Note 1: When OVP, OLP, or Latch Protection is tripped.
Note 2: Guaranteed by design because Vcs(off) can’t be measured when VBNO=0V.

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Electrical Characteristics (Continued)
(TA = +25oC unless otherwise stated, VCC=12.0V)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Brownout Protection & Line Compensation (BNO Pin)
Brownout Turn-On Trip Level 1.20 1.25 1.30 V
Brownout Turn-Off Trip Level 1.05 1.10 1.15 V
Saturation Voltage IBNO=1.5μA 5.0 V
Line Compensation Ratio 0.04 V/V
Over Voltage Protection (OVP Pin)
OVP Trip Level 2.35 2.50 2.65 V
Saturation Voltage IBNO=1.5μA 5.0 V
OVP de-bounce time 100 μS
OLP (Over Load Protection)
OLP Trip Level VCOMP(OLP) 5.0 V
OLP Delay Time VCOMP>5.2V 30 mS

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Typical Performance Characteristics
12.0
16.0

15.0 11.2
UVLO (on) (V)

UVLO (off) (V)

14.0 10.4

12.0 9.6

11.0 8.8

10.0 8.0
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C)
Temperature (°C)
Fig. 1 UVLO (on) vs. Temperature Fig. 2 UVLO (off) vs. Temperature

70 26
Green Mode Frequency (KHz)

67 24
Frequency (KHz)

64 22

61 20

58 18

55 16
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 3 Frequency vs. Temperature Fig. 4 Green Mode Frequency vs. Temperature

70 25
Green Mode Frequency (KHz)

68 23
Frequency (KHz)

66 21

64 19

62 17

60 15
12 14 16 18 20 22 24 12 14 16 18 20 22 24
VCC (V) VCC (V)
Fig. 5 Frequency vs. VCC Fig. 6 Green Mode Frequency vs. V CC

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85 0.90

0.85
80
VLIN E= 0V
Max Duty Cycle (%)

0.80

75

VCS (off) (V)

V LINE =1.25V
0.75

70
0.70

V LINE =3.75V
65 0.65

0.60
60
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 7 Max Duty Cycle vs. Temperature Fig. 8 Vcs (off) vs. Temperature

40 2.60

2.55
30
Startup Current (μA)

OVP (V)

2.50
20

2.45
10

0 2.40
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 9 Startup Current vs. Temperature Fig. 10 OVP-Trip Level vs. Temperature

6.0 5.5

5. 3
5.8

5. 1
5.6
VCOMP (V)

OLP (V)

5.4 4. 9

4. 7
5.2

5.0 4. 5
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 11 VCOMP open-loop voltage vs. Temperature Fig. 12 OLP-Trip Level vs. Temperature

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2.60 110

(-)Latch Pin Source Current (μA)

2.55 100
(-)Latch (V)

2.50 90

2.45 80

2.40 70
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 13 (-)Latch Pin Off-Level vs. Temperature Fig. 14 (-)Latch Pin Source Current vs Temperature

10 10

8 8

6 6
IBNO (μA)

IOVP (μA)

4 4

2 125°C 2 125°C

25°C 25°C
0 0
-40°C -40°C

-2 -2
0 1 2 3 4 5 0 1 2 3 4 5
VBNO VOVP
Fig. 15 VBNO vs. IBNO Fig. 16 VOVP vs. IOVP

1. 27 1.150

1. 26 1.125
BNO Pin On (V)

BNO Pin Off (V)

1. 25 1.100

1. 24 1.075

1. 23 1.050
-40 0 40 80 120 -40 0 40 80 120

Temperature (°C) Temperature (°C)

Fig. 17 BNO Pin On Level vs. Temperature Fig. 18 BNO Pin Off Level vs. Temperature

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Application Information
Operation Overview Therefore, the current through R1 will provide the startup

As long as the green power requirement becomes a trend current and to charge the capacitor C1. Whenever the

and the power saving is getting more and more important Vcc voltage is high enough to turn on the LD7523A and

for the switching power supplies and switching adapters, further to deliver the gate drive signal, the supply current

traditional PWM controllers are not able to support such is provided from the auxiliary winding of the transformer.

new requirements. Furthermore, the cost and size Lower startup current requirement on the PWM controller

limitation forces the PWM controllers to powerfully will help to increase the maximum value on R1 and then

integrate more functions for reducing the external part reduce the power consumption on R1. By using CMOS

counts. The LD7523A is targeted on such applications process and the special circuit design, the maximum

and provides an easy and cost effective solution; its startup current of LD7523A is only 35μA.

detailed features are described as below. If a higher resistance value of the R1 is chosen, it usually
takes more time to start up. Careful value selection of R1
and C1 will optimize the power consumption and startup
Under Voltage Lockout (UVLO)
time.
An UVLO comparator is implemented in it to detect the
voltage on the VCC pin, for assuring the supply voltage
high enough to turn on the LD7523A PWM controller and AC EMI
input Filter
to drive the power MOSFET. As shown in Fig. 19, a
R1
hysteresis is built in to prevent the shutdown due to the Cbulk
D1
voltage dip during startup. The turn-on and turn-off
threshold levels are set at 12.7V and 9.7V, respectively. C1
Vcc
VCC
OUT
UVLO(on)

UVLO(off) LD7523A
CS

t GND

I(Vcc) operating current

(~ mA)

Fig. 20

startup current
(~uA)
Output Stage and Maximum Duty-Cycle
t
An output stage of a CMOS buffer, with typical 500mA
Fig. 19
driving capability, is incorporated to drive a power
MOSFET directly. And the maximum duty-cycle of
Startup Current and Startup Circuit
LD7523A is limited to 75% to avoid the transformer
The typical startup circuit for the LD7523A is shown in Fig.
saturation.
20. During the startup transient, the Vcc is lower than
the UVLO threshold and thus there is no gate pulse
produced from the LD7523A to drive power MOSFET.

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Oscillator and Switching Frequency Current Sensing, Leading-edge Blanking
The switching frequency of LD7523A is fixed at 65KHz The typical current mode PWM controller feeds back both
internally to provide the optimized operations by current signal and voltage signal to close the control loop
considering the EMI performance, thermal treatment, and achieve regulation. The LD7523A detects the primary
component sizes and transformer design. MOSFET current from the CS pin, which is not only for the
peak current mode control but also for the pulse-by-pulse
Voltage Feedback Loop current limit. The maximum voltage threshold of the

The voltage feedback signal is provided from the TL431 in current sensing pin is set as 0.85V. Thus the MOSFET

the secondary side through the photo-coupler to the peak current can be calculated as:

COMP pin of LD7523A. The input stage of LD7523A, (0.85 − VLINE _ COMPENSATION )
IPEAK(MAX) =
like the UC384X, has 2 diodes voltage offset before RS
feeding into the voltage divider with 1/3 ratio, that is,
A 350nS leading-edge blanking (LEB) time is included in
1
V+ (PWM COMPARATOR ) = × ( VCOMP − 2VF )
3 the input of CS pin to prevent the false-trigger due to the
A pulling-high resistor is embedded internally to eliminate current spike. However, the total pulse width of the
the requirement of another resistor in the external circuit. turn-on spike is decided by the output power, circuit
design and PCB layout. It is strongly recommended to
Dual-Oscillator Green-Mode Operation adopt a smaller R-C filter (as shown in figure 21) to avoid
There are many different topologies implemented in the CS pin being damaged by the negative turn-on spike.
different chips for the green-mode or power saving
requirements, such as “burst-mode control”,
“skipping-cycle mode”, “variable off-time control “…etc.
The basic operation theory of all these approaches
intends to reduce the switching cycles under light-load or
no-load condition either by skipping some switching
pulses or reduce the switching frequency.
By using this dual-oscillator control, the green-mode
frequency can be well controlled and further to avoid the
generation of audible noise.

Internal Slope Compensation

A fundamental issue of current mode control is the
stability problem when its duty-cycle is higher than 50%.
To stabilize the control loop, slope compensation is
needed in the traditional UC384X design by injecting the
ramp signal from the RT/CT pin through a coupling
Fig. 21
capacitor. In the LD7523A, the internal slope
compensation circuit has been internally implemented to
simplify the external circuit design.

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Line Voltage
Brownout Protection & Line Compensation
BNO pin plays 2 different roles in LD7523A. The major
function is to set the brownout protection point, and at the t
same time, the second function provides the line
compensation function like in LD7520.
VBNO
Since the voltage on the BNO pin is proportional to the
bulk capacitor voltage, representing the line voltage. A 1.25V
1.10V
brownout comparator is implemented to detect the
AC OK area
abnormal line condition and, upon detection it shuts down
t
the controller to prevent damage. Figure 22 shows the
Vcc
operation. When VBNO is lower than 1.25V, the gate
output will be kept off even if the Vcc already achieves UVLO(on)

UVLO(on), therefore the Vcc will be hiccup between UVLO(off)

UVLO(on) and UVLO(off). Only if the line voltage is so t

high that VBNO is higher than 1.25V, the gate output will OUT

start switching when the next UVLO(on) is tripped. A

hysteresis is implemented to prevent the false trigger Non-
Non-Switching Switching
Switching
during turn-on and turn-off.
t
On the other hand, LD7523A detects the voltage on the
BNO pin to feed the line compensation signal on the
Fig. 22
current sense circuit. Figure 23 shows the circuit. Thanks
to this implementation, the OCP levels of high-line and 2 ⋅ Vac
low-line can be achieved at very close points.
The voltage gain from the BNO voltage to line
compensation is 0.04 (V/V). The relationship between
BNO pin voltage and the line compensation is illustrated
in figure 24.
In order to protect BNO pin from being damaged during
∑
the dividing resistors floating, an internal zener diode is
implemented in BNO pin. Fig. 15 shows the sinking
capability of the zener diode. To protect BNO pin, the
current flowing in BNO pin must be below 1.5μA, as Fig. 23
shown in Fig. 15.

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Line Fig. 25
Compensation By using such protection mechanism, the average input
power can be reduced to a very low level so that the
160mV
component temperature and stress can be controlled
150mV
within a safe operating area.
Linear Region

gain=0.04 Over Voltage Protection (OVP)

52mV
Turn-Off The Vgs ratings of the nowadays power MOSFETs most
Region
have the maximum of 30V. To prevent the component
Vpin1
1.30V 3.75V 4.0V damage in a fault condition, the LD7523A is implemented
Fig. 24 with the protection through the OVP pin. Figure 26 and
Over Load Protection (OLP) figure 27 show 2 different configurations to program the
To protect the circuit from the damage during over load OVP setting point --- zener detection and voltage divider.
condition or short condition, a smart OLP function is Figure 26 shows zero bias current under normal operation
implemented in the LD7523A. Figure 25 shows the so that it will not affect the startup timing. But the
waveforms of the OLP operation. Under such fault tolerance of OVP trip point will be higher due to the
condition, the feedback system will force the voltage loop breakdown voltage variation of a discrete zener diode.
toward saturation and thus pull the voltage on COMP pin On the other hand, the circuit of figure 27 will get the

(VCOMP) to high. Whenever the VCOMP trips the OLP benefits on the cost and the OVP accuracy, but R1 and
R2 must be of high resistance to avoid affecting the
threshold, 5.0V, and keeps longer than 30mS, the
startup time due to the load effect.
protection is activated to turn off the gate output and stop
As shown in figure 28, whenever the voltage on the OVP
the switching of power circuit. The 30mS delay time is to
pin is higher than the threshold voltage 2.5V, the output
prevent the false trigger during the power-on and turn-off
gate drive circuit will be shut down simultaneously,
transient.
stopping the switching of the power MOSFET.
VCC
Whenever the voltage on the OVP pin gets back to lower
UVLO(on) than 2.5V, the output is automatically returned to the

UVLO(off) normal operation on the next UVLO(on) level.

OLP
UVLO(off)
OLP Reset Vbulk-cap
t

COMP
30mS V(OVP)= Vz+2.5V

5.0V Vz

VCC
OLP trip Level
t
OVP
OUT LD7523A

GND
Switching Non-Switching Switching
Fig. 26
t

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and then latch off the power supply. For the LD7523A,

R2 the controller will be kept latched until the Vcc drops lower
V (OVP ) = 2.5V ⋅ (1 + )
R1 than 8V (power down reset) and the fault condition is
removed. That means the gate output may still be kept
off even the abnormal condition is released. The only
way to successfully re-start the circuit needs to meet 2
conditions. One is to cool down the circuit and thus NTC
resistance increases over 3.5V. Another condition is to
remove the AC power cord and begin another AC

Fig. 27 power-on recycling. The detail operation is depicted as

figure 29.

Fig. 28

(-)LATCH Pin and Over Temperature

Protection (OTP) --- Latched Mode
Protection
Under some abnormal conditions, the ambient
temperature may be increased significantly, causing some
damage on the components or, in a worsen scenario,
endangering the users. Thus, the OTP is required. The
OTP circuit is implemented by sensing a hot-spot of power Fig. 29

circuit like a power MOSFET or an output rectifier. It can

be easily achieved by connecting a NTC on the (-)LATCH
pin of a LD7523A. When the device temperature or
ambient temperature rises, the resistance of NTC
decreases so that the voltage on the (-)LATCH pin will be
V( − )LATCH = 100μA × RNTC

When the V(-)LATCH is lower than the threshold voltage

(typical 2.5V), LD7523A will shut down the gate output

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Summary of Protections
There are several ways to control the on/off of LD7523A.
The details are listed as the table below.

Turn Off Operation

Comp Pin < Cycle by Cycle Mode
COMP
1.4V Non-latch
Comp Pin >
OLP
5.0V
Hiccup Mode
OVP Pin >
OVP Non-latch
2.5 V
Re-start after next
BNO Pin <
UVLO(on)
Brownout 1.25V with
Hysteresis
(-)LATCH Pin Latch Mode
OTP
< 2.5V
Table 1

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Package Information
SOP-8

Dimensions in Millimeters Dimensions in Inch

Symbols
MIN MAX MIN MAX

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.229 0.007 0.009
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
θ 0° 8° 0° 8°

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Package Information
DIP-8

Dimension in Millimeters Dimensions in Inches

Symbol
Min Max Min Max

A 9.017 10.160 0.355 0.400

B 6.096 7.112 0.240 0.280

C ----- 5.334 ------ 0.210

D 0.356 0.584 0.014 0.023

E 1.143 1.778 0.045 0.070

F 2.337 2.743 0.092 0.108

I 2.921 3.556 0.115 0.140

J 7.366 8.255 0.29 0.325

L 0.381 ------ 0.015 --------

Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers

should verify the datasheets are current and complete before placing order.

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Revision History

Rev. Date Change Notice

00 10/27/2008 Original specification.
01 12/11/2008 Additional remark on BNO pin

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