Si5338a A GM PDF

Si5338
I 2 C - P R O G R A M M A B LE A N Y - F R E Q U E N C Y, A N Y -O UTPU T Q U A D C L OC K G E N E R A T O R
Features
 Low power MultiSynth™ technology  Single supply core with excellent
enables independent, any-frequency PSRR: 1.8, 2.5, 3.3 V
synthesis on four differential output  Independent frequency increment/
drivers decrement feature enables
 Highly-configurable output drivers with glitchless frequency adjustments in
up to four differential outputs, eight 1 ppm steps
single-ended clock outputs, or a  Independent phase adjustment on
combination of both each of the output drivers with an
 Low phase jitter of 0.7 ps RMS typ accuracy of <20 ps steps
 High precision synthesis allows true  Highly configurable spread Ordering Information:
zero ppm frequency accuracy on all spectrum (SSC) on any output: See page 168.
outputs Any frequency from 5 to 350 MHz
 Flexible input reference: Any spread from 0.5 to 5.0%
External crystal: 8 to 30 MHz Any modulation rate from 33 to Pin Assignments
CMOS input: 5 to 200 MHz 63 kHz
SSTL/HSTL input: 5 to 350 MHz  External feedback mode allows
Differential input: 5 to 710 MHz zero-delay mode Top View
RSVD_GND
 Independently configurable outputs  Loss of lock and loss of signal
VDDO0
CLK0B
CLK0A
support any frequency or format: alarms
VDD
SDA
LVPECL/LVDS: 0.16 to 710 MHz  I2C/SMBus compatible interface
24 23 22 21 20 19
HCSL: 0.16 to 250 MHz  Easy to use programming software
IN1 1 18 CLK1A
CMOS: 0.16 to 200 MHz  Small size: 4 x 4 mm, 24-QFN
SSTL/HSTL: 0.16 to 350 MHz  Low power: 45 mA core supply typ IN2 2 17 CLK1B
 Independent output voltage per driver:  Wide temperature range: –40 to IN3 3 16 VDDO1
GND
1.5, 1.8, 2.5, or 3.3 V +85 °C GND
Pad
IN4 4 15 VDDO2
Applications IN5 5 14 CLK2A
 Ethernet switch/router  Any-frequency clock conversion IN6 6

7 8 9
13 CLK2B
10 11 12
 PCI Express 2.0/3.0  MSAN/DSLAM/PON
SCL
INTR
VDDO3
CLK3B
CLK3A
VDD
 Broadcast video/audio timing  Fibre Channel, SAN

 Processor and FPGA clocking  Telecom line cards
Description
The Si5338 is a high-performance, low-jitter clock generator capable of
synthesizing any frequency on each of the device's four output drivers. This timing
IC is capable of replacing up to four different frequency crystal oscillators or
operating as a frequency translator. Using its patented MultiSynth™ technology,
the Si5338 allows generation of four independent clocks with 0 ppm precision.
Each output clock is independently configurable to support various signal formats
and supply voltages. The Si5338 provides low-jitter frequency synthesis in a
space-saving 4 x 4 mm QFN package. The device is programmable via an I2C/
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
3.3 V core supply. I2C device programming is made easy with the ClockBuilder™
Desktop software available at www.silabs.com/ClockBuilder.
Rev. 0.6 9/10 Copyright © 2010 by Silicon Laboratories Si5338

Si5338
Functional Block Diagram
VDD
Synthesis Synthesis Output

Osc noclk Stage
Stage 1 Stage 2
(PLL) VDDO0
IN1 P1DIV_IN
ref MultiSynth CLK0A
IN2 ÷R0
÷P1 ÷M0 CLK0B
IN3
Loop VDDO1
Phase VCO
Filter MultiSynth CLK1A
Frequency ÷R1
÷M1
P2DIV_IN Detector CLK1B
IN4 fb
IN5 ÷P2 VDDO2

IN6 noclk MultiSynth CLK2A
÷R2
÷M2 CLK2B
Control & Memory MultiSynth
÷N VDDO3
OEB/PINC/FINC
I2C_LSB/PDEC/FDEC MultiSynth CLK3A
÷R3
NVM ÷M3
Control RAM CLK3B
SCL (OTP)
SDA
INTR
2 Rev. 0.6
Si5338
TABLE O F C ONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.5. Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8. Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9. Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. Si5338 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1. Register Write-Allowed Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2. Register Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
8. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
9. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Rev. 0.6 3
Si5338
1. Electrical Specifications
Table 1. Recommended Operating Conditions

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA –40 25 85 °C
2.97 3.3 3.63 V
Core Supply Voltage VDD 2.25 2.5 2.75 V
1.71 1.8 1.98 V
Output Buffer Supply VDDOn 1.4 — 3.63 V
Voltage
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. Absolute Maximum Ratings
Parameter Symbol Test Condition Value Unit

DC Supply Voltage VDD –0.5 to 3.8 V
Storage Temperature Range TSTG –55 to 150 °C
ESD Tolerance HBM 2.5 kV
(100 pF, 1.5 k)
ESD Tolerance CDM 550 V
ESD Tolerance MM 175 V
Latch-up Tolerance JESD78 Compliant
Junction Temperature TJ 150 °C
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
4 Rev. 0.6
Si5338
Table 3. DC Characteristics

Core Supply Current IDD 100 MHz on all outputs, — 45 60 mA
25 MHz refclk
LVPECL, 710 MHz — — 30 mA
LVDS, 710 MHz — — 8 mA
HCSL, 250 MHz — — 20 mA

2 pF load
SSTL, 350 MHz — — 19 mA
CMOS, 50 MHz — — 28 mA
Output Buffer Supply Current IDDOx 15 pF load
CMOS, 200 MHz — — 20 mA
2 pF load, 3.3 V VDD0
CMOS, 200 MHz — 13 17 mA
2 pF load, 2.5 V
CMOS, 200 MHz — 11 15 mA
2 pF load, 1.8 V
HSTL, 350 MHz — — 19 mA
Table 4. Thermal Characteristics
Parameter Symbol Test Condition Value Unit

Thermal Resistance JA Still Air 37 °C/W
Junction to Ambient
Thermal Resistance JC Still Air 25 °C/W
Junction to Case
Rev. 0.6 5
Si5338
Table 5. Performance Characteristics

PLL Acquisition Time tACQ — — 25 ms
PLL Lock Range fLOCK 5000 — — ppm
PLL Loop Bandwidth fBW — 1.6 — MHz
MultiSynth Frequency fRES Output frequency < Fvco/8 0 0 1 ppb

Synthesis Resolution
CLKIN Loss of Signal Detect tLOS — 2.6 5 µs
Time
CLKIN Loss of Signal Release tLOSRLS 0.01 0.2 1 µs
Time
PLL Loss of Lock Detect Time tLOL — 5 10 ms
POR to Output Clock Valid tRDY — — 2 ms

(Pre-programmed Devices)
Input-to-Output Propagation tPROP Buffer Mode — 2.5 — ns
Delay (PLL Bypass)
Output-Output Skew tDSKEW Rn divider = 11 — — 100 ps
POR to I2C Ready — — 15 ms
Programmable Initial –45 — +45 ns

POFFSET
Phase Offset
Phase Increment/Decrement PSTEP — — 20 ps
Accuracy
Phase Increment/Decrement PRANGE –45 — +45 ns
Range
Frequency range for phase fPRANGE — — 3502 MHz
increment/decrement
Phase Increment/Decrement PUPDATE Pin control2,3 667 — — ns
Update Time MultiSynth output >18 MHz
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.9.3. Initial Phase Offset" on page 24.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.
6 Rev. 0.6
Si5338
Table 5. Performance Characteristics (Continued)

Phase Increment/Decrement PUPDATE Pin control2,3 — 12 — Periods
Update Time MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
Frequency Increment/ fSTEP R divider not used 1 — See ppm
Decrement Step Size Note 2
Frequency Increment/ fRANGE R divider not used — — 3502 MHz
Decrement Range
Frequency Increment/ fUPDATE Pin control2,3 667 — — ns
Decrement Update Time MultiSynth output >18 MHz
Frequency Increment/ fUPDATE Pin control2,3 — 12 — Periods
Decrement Update Time MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
Spread Spectrum PP SSDEV MultiSynth Output < ~Fvco/8 0.1 — 5.04 %
Frequency Deviation
Spread Spectrum Modulation SSDEV MultiSynth Output < ~Fvco/8 30 — 635 kHz
Rate
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.9.3. Initial Phase Offset" on page 24.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.
Table 6. Input and Output Clock Characteristics

Parameter Symbol Test Condition Min Typ Max Units
Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)
Frequency fIN 5 — 710 MHz
Differential Voltage VPP 710 MHz input 0.4 — 2.4 VPP

Swing
Rise/Fall Time tR/tF 20%–80% — — 1.0 ns
1 DC < 1 ns tr/tf 40 — 60 %
Duty Cycle
Notes:
1. For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns
2. Not in PLL bypass mode.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns
4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6.
5. Includes effect of internal series 22  resistor.
Rev. 0.6 7
Si5338
Table 6. Input and Output Clock Characteristics (Continued)
Input Impedance RIN 10 — — k
Input Capacitance CIN — 3.5 — pF
Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)
Frequency fIN CMOS 5 — 200 MHz
Input Voltage VI –0.1 — 3.63 V
Input Voltage Swing 200 MHz 0.8 — VDD+10% Vpp
Rise/Fall Time tR/tF 20%–80% — — 2 ns
Duty Cycle2,3 DC < 4 ns tr/tf 40 — 60 %
Input Capacitance CIN — 2.0 — pF
Output Clocks (Differential)

0.16 — 350 MHz
LVPECL, LVDS 367 — 473.33 MHz

Frequency4 fOUT
550 — 710 MHz
HCSL 0.16 — 250 MHz
VOC common mode — VDDO–1.45 V — V

LVPECL Output Voltage peak-to-peak single-
VSEPP 0.55 0.8 0.96 VPP
ended swing
VOC common mode 1.125 1.2 1.275 V

LVDS Output Voltage
(2.5/3.3 V) peak-to-peak single-
VSEPP 0.25 0.35 0.45 VPP
ended swing

LVDS Output Voltage
(1.8 V) peak-to-peak single-
VSEPP 0.25 0.35 0.45 VPP
ended swing
HCSL Output Voltage peak-to-peak single-
VSEPP 0.575 0.725 0.85 VPP
ended swing
Rise/Fall Time tR/tF 20%–80% — — 450 ps
Duty Cycle2 DC 45 — 55 %
Notes:
8 Rev. 0.6
Si5338
Table 6. Input and Output Clock Characteristics (Continued)
Output Clocks (Single-Ended)
CMOS 0.16 — 200 MHz

Frequency fOUT
SSTL, HSTL 0.16 — 350 MHz
CMOS 20%–80% tR/tF 2 pF load — 0.45 0.85 ns

Rise/Fall Time
CMOS 20%–80% tR/tF 15 pF load — — 1.7 ns
Rise/Fall Time
CMOS Output Resis- — 50 — 
tance
SSTL Output — 50 — 
Resistance
HSTL Output — 50 — 
Resistance
VOH 4 mA load VDDO – 0.3 — V
CMOS Output Voltage5
VOL 4 mA load — 0.3 V
VOH SSTL-3 VDDOx = 2.97 0.45xVDDO+0.41 — — V
VOL to 3.63 V — — 0.45xVDDO–0.41 V
VOH SSTL-2 VDDOx = 2.25 0.5xVDDO+0.41 — — V

SSTL Output Voltage
VOL to 2.75 V — — 0.5xVDDO–0.41 V
VOH SSTL-18 VDDOx = 1.71 0.5xVDDO+0.34 — V
VOL to 1.98 V — — 0.5xVDDO–0.34 V
VOH 0.5xVDDO+0.3 — — V
HSTL Output Voltage VDDO = 1.4 to 1.6 V
VOL — — 0.5xVDDO –0.3 V
Duty Cycle2 DC 45 — 55 %
Notes:
Rev. 0.6 9
Si5338
Table 7. Control Pins

Parameter Symbol Condition Min Typ Max Unit

Input Control Pins (IN3, IN4)
0.3 x
Input Voltage Low VIL –0.1 — V
VDD
0.7 x
Input Voltage High VIH — 3.63 V
VDD
Input Capacitance CIN — — 4 pF
Input Resistance RIN — 20 — k
Output Control Pins (INTR)
Output Voltage Low VOL ISINK = 3 mA 0 — 0.4 V
Rise/Fall Time 20–80% tR/tF CL < 10 pf, pull up 1 k — — 10 ns
10 Rev. 0.6
Si5338
Table 8. Crystal Specifications for 8 to 11 MHz

Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 8 — 11 MHz
Load Capacitance (on-chip differential) cL 11 12 13 pF
Crystal Output Capacitance cO — — 6 pF
Equivalent Series Resistance rESR — — 300 
Crystal Max Drive Level dL 100 — — µW

Crystal Frequency fXTAL 11 — 19 MHz
Crystal Output Capacitance cO — — 5 pF
Equivalent Series Resistance rESR — — 200 
Crystal Max Drive Level dL 100 — — µW

Crystal Frequency fXTAL 19 26 MHz
Crystal Output Capacitance cO 5 pF
Equivalent Series Resistance rESR 100 
Crystal Max Drive Level dL 100 µW

Crystal Frequency fXTAL 26 30 MHz
Crystal Output Capacitance cO 5 pF
Equivalent Series Resistance rESR 75 
Crystal Max Drive Level dL 100 µW
Rev. 0.6 11
Si5338
Table 12. Jitter Specifications1,2


GbE Random Jitter CLKIN = 25 MHz
JGBE — 0.7 1 ps RMS
(12 kHz–20 MHz)3 All CLKn at 125 MHz4
GbE Random Jitter CLKIN = 25 MHz
RJGBE — 0.38 0.79 ps RMS
(1.875–20 MHz) All CLKn at 125 MHz4
CLKIN = 19.44 MHz
OC-12 Random Jitter
JOC12 All CLKn at — 0.7 1 ps RMS
(12 kHz–5 MHz)
155.52 MHz4
CLKIN = 25 MHz
PCI Express 3.0
All CLKn at 100 MHz
Random Jitter JPCIERJ1 — 0.6 1 ps RMS
Spread Spectrum not
(1.5 MHz—50 MHz)3
enabled4
CLKIN = 25 MHz
PCI Express 3.0
All CLKn at 100 MHz
Random Jitter JPCIERJ2 — 0.7 1 ps RMS
Spread Spectrum not
(12 kHz—20 MHz)3
enabled4
CLKIN = 25 MHz
PCI Express 3.0 All CLKn at 100 MHz
— 8 15 ps pk-pk
Period Jitter Spread Spectrum not
enabled4
CLKIN = 25 MHz
PCI Express 3.0 All CLKn at 100 MHz
— 13 30 ps pk-pk
Cycle-Cycle Jitter Spread Spectrum not
enabled4
Period Jitter JPER N = 10,000 cycles5 — 10 30 ps pk-pk
N = 10,000 cycles
JCC Output MultiSynth — 9 29 ps pk6
Cycle-Cycle Jitter
operated in integer or
fractional mode5
Output and feedback
Random Jitter
RJ MultiSynth in integer or — 0.7 1.5 ps RMS
(12 kHz–20 MHz)
fractional mode5
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. DJ for PCI and GBE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
6. Measured in accordance with JEDEC standard 65.
7. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
12 Rev. 0.6
Si5338
Table 12. Jitter Specifications1,2 (Continued)

Output MultiSynth
operated in fractional — 3 15 ps pk-pk
5
mode
Deterministic Jitter DJ
Output MultiSynth
operated in integer — 2 10 ps pk-pk
mode5
Output MultiSynth
operated in fractional — 13 36 ps pk-pk
Total Jitter TJ = DJ+14xRJ mode5
(12 kHz–20 MHz) (See Note 7) Output MultiSynth
operated in integer — 12 20 ps pk-pk
mode5
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. DJ for PCI and GBE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
6. Measured in accordance with JEDEC standard 65.
7. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
Table 13. Typical Phase Noise Performance
Offset Frequency 25MHz XTAL 27 MHz Ref In 19.44 MHz Ref In Units
to 156.25 MHz to 148.3517 MHz to 155.52 MHz
100 Hz –90 –87 –110
1 kHz –120 –117 –116
10 kHz –126 –123 –123
dBc/Hz
100 kHz –132 –130 –128
1 MHz –132 –132 –128
10 MHz –145 –145 –145
Rev. 0.6 13
Si5338
Table 14. I2C Specifications (SCL,SDA)1

Parameter Symbol Test Condition Standard Mode Fast Mode Unit
Min Max Min Max
LOW Level Input VILI2C –0.5 0.3 x VDDI2C –0.5 0.3 x VDDI2C2 V
Voltage
HIGH Level Input VIHI2C 0.7 x VDDI2C 3.63 0.7 x VDDI2C2 3.63 V
Voltage
Hysteresis of VHYS N/A N/A 0.1 — V
Schmitt Trigger
Inputs
LOW Level Out- VOLI2C2 VDDI2C2 = 2.5/3.3 V 0 0.4 0 0.4 V
put Voltage (open
drain or open col- VDDI2C2 = 1.8 V N/A N/A 0 0.2 x VDDI2C V
lector) at 3 mA
Sink Current
Input Current II2C –10 10 –10 10 µA
Capacitance for CI2C VIN = –0.1 to VDDI2C — 4 — 4 pF

each I/O Pin
I2C Bus Timeout — Timeout Enabled 25 35 25 35 ms
Notes:
1. Refer to NXP’s UM10204 I2C-bus specification and user manual, Revision 03, for further details:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. Only I2C pullup voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I2C bus voltage
is less than 2.5 V to maintain compatibility with the I2C bus standard.
14 Rev. 0.6
Si5338
2. Typical Application Circuits
+3.3 V
SD/HD/3G-SDI
0.1 uF Power Supply Video/Audio
Decoupling Capacitors
(1 per VDD or VDDOx pin) Format Converter
7 24 20 16 15 11
SD/HD/3G SD/HD/3G
VDD
VDD
VDDOA
VDDOB
VDDOD
VDDOC
SDI IN SDI OUT
SDI Video SDI
Optional XTAL for 27 MHz 1
IN1 Deserializer Processor Serializer
Free-run Applications XTAL 2
IN2
3
Single-ended or 27 MHz IN3 22 100 MHz 100
CLK0A
Differential Inputs 74.25 MHz 5 21
74.25/1.001 MHz IN5 CLK0B x
for Synchronous 74.25 MHz, 74.25/1.001 MHz
Applications 148.5 MHz 100 Si5338C 18 148.5 MHz, 148.5/1.001 MHz
6 CLK1A
148.5/1.001 MHz IN6 17
CLK1B
+3.3 V 14
Audio Out
CLK2A x Audio
13 IN3
CLK2B x Processor
1k 1k 1k
8 24.576 MHz / 6.144 MHz
INTR 10
19 CLK3A
2 9
I C Bus SDA
CLK3B x
12
SCL
2 4
I C Address = 111 0000 or 111 0001 I2C_LSB
GND
GND
23
23 PAD
PAD
Storage Area
Network
+3.3 V
0.1 uF Power Supply disk SAS2

Decoupling Capacitors 4/8 Port
(1 per VDD or VDDOx pin) Controller
disk Ethernet
7 24 20 16 15 11
Fiber
VDD
VDD
VDDOA
VDDOB
VDDOD
VDDOC
PCIe Channel
disk SAS2 Switch
25 MHz 1
IN1
4/8 Port
XTAL 2 Controller
IN2 disk
3
IN3 22 37.5/75/120/150 MHz
CLK0A
5 21
x IN5 CLK0B
6 Si5338C 18 100 MHz

IN6 CLK1A
17
CLK1B x Network
Processor
+3.3V 14 66 MHz
CLK2A
13
1k 1k 1k
CLK2B x
8
INTR 10 106.25 MHz
19 CLK3A
I2C Bus SDA
CLK3B
9
x
12
SCL
4
I2C Address = 111 0000 or 111 0001 I2C_LSB
GND
GND
23
23 PAD
PAD
Rev. 0.6 15
Si5338
3. Functional Description
VDD
Input Synthesis Synthesis Output

Osc
Stage Stage 1 Stage 2 Stage
(PLL) VDDO0
MultiSynth CLK0A
÷R0
IN1 CLKIN ÷M0 CLK0B
ref
IN2 ÷P1
IN3 Loop VDDO1
Phase VCO
Filter MultiSynth CLK1A
Frequency ÷R1
÷M1
FDBK Detector CLK1B
IN4 fb
IN5 ÷P2 VDDO2
IN6 MultiSynth CLK2A
÷R2
÷M2 CLK2B
Control & Memory MultiSynth
÷N VDDO3
OEB/PINC/FINC
I2C_LSB/PDEC/FDEC MultiSynth CLK3A
÷R3
NVM ÷M3
SCL Control RAM CLK3B
(OTP)
SDA
INTR
Figure 1. Si5338 Block Diagram

3.1. Overview
The Si5338 is a high-performance, low-jitter clock A zero-delay mode is also available to help minimize
generator capable of synthesizing four independent input-to-output delay. Spread spectrum is available on
user-programmable clock frequencies up to 350 MHz each of the clock outputs for EMI-sensitive applications,
and select frequencies up to 710 MHz. The device such as PCI Express.
supports free-run operation using an external crystal, or Configuration and control of the Si5338 is mainly
it can lock to an external clock for generating handled through the I2C/SMBus interface. Some
synchronous clocks. The output drivers support four features, such as output enable and frequency or phase
differential clocks or eight single-ended clocks or a adjustments, can optionally be pin controlled. The
combination of both. The output drivers are configurable device has a maskable interrupt pin that can be
to support common signal formats, such as LVPECL, monitored for loss of lock or loss of input signal
LVDS, HCSL, CMOS, HSTL, and SSTL. Separate conditions.
output supply pins allow supply voltages of 3.3, 2.5, 1.8,
The device also provides the option of storing a user-
and 1.5 V to support the multi-format output driver. The
definable clock configuration in its non-volatile memory
core voltage supply accepts 3.3, 2.5, or 1.8 V and is
(NVM), which becomes the default clock configuration
independent from the output supplies.
at power-up.
Using its two-stage synthesis architecture and patented
3.1.1. ClockBuilder™ Desktop Software
high-resolution MultiSynth technology, the Si5338 can
generate four independent frequencies from a single To simplify device configuration, Silicon Labs provides
input frequency. In addition to clock generation, the ClockBuilder Desktop software. To ease these steps,
inputs can bypass the synthesis stage enabling the Silicon Labs has released ClockBuilder Desktop. The
Si5338 to be used as a high-performance clock buffer or software serves two purposes: configure the Si5338
a combination of a buffer and generator. with optimal divider ratios based on the desired
frequencies, and to control the EVB, if connected to the
For applications that need fine frequency adjustments,
host PC. The optimal configuration can be saved from
such as clock margining, each of the synthesized
the software in text files that can be used in any system,
frequencies can be incremented or decremented in
which configures the device over I2C.
user-defined steps as low as 1 ppm per step.
ClockBuilder Desktop can be downloaded from
Output-to-output phase delays are also adjustable in
www.silabs.com/ClockBuilder and runs on Windows XP,
user-defined steps with an error of <20 ps to
Windows Vista, and Windows 7.
compensate for PCB trace delays or for fine tuning of
setup and hold margins.
16 Rev. 0.6
Si5338
3.2. Input Stage IN3 and IN4 accept single-ended signals from 5 MHz to
200 MHz. The single-ended inputs are internally ac-
The input stage supports four inputs. Two are used as
coupled; so, they can accept a wide variety of signals
the clock inputs to the synthesis stage, and the other
without requiring a specific dc level. The input signal
two are used as feedback inputs for zero delay or
only needs to meet a minimum voltage swing and must
external feedback mode. In cases where external
not exceed a maximum VIH or a minimum VIL. Refer to
feedback is not required, all four inputs are available to
Table 6 for signal voltage limits. A typical single-ended
the synthesis stage. The reference selector selects one
connection is shown in Figure 3. For additional
of the inputs as the reference to the synthesis stage.
termination options, refer to “AN408: Termination
The input configuration is selectable through the IC
Options for Any-Frequency, Any-Output Clock
interface. The input MUXes are set automatically in
Generators and Clock Buffers—Si5338, Si5334,
ClockBuilder Desktop (see “3.1.1. ClockBuilder™
Si5330”.
Desktop Software”). For information on setting the input
MUXs manually, see “AN411: Configuring the Si5338”. For free-run operation, the internal oscillator can
operate from a low-frequency fundamental mode crystal
(XTAL) with a resonant frequency between 8 and
30 MHz. A crystal can easily be connected to pins IN1
Osc noclk
and IN2 without external components as shown in
To Synthesis Stage
IN1 P1DIV_IN Figure 4. See Tables 8–11 for crystal specifications that
IN2 ÷P1 are guaranteed to work with the Si5338.
IN3
IN1
P2DIV_IN
IN4
XTAL Osc To synthesis stage
IN5 ÷P2
noclk
or output selectors
IN6
IN2
Figure 2. Input Stage

Figure 4. Connecting an XTAL to the Si5338
IN1/IN2 and IN5/IN6 are differential inputs capable of Refer to “AN360: Crystal Selection Guide for Si533x/5x
accepting clock rates from 5 to 710 MHz. The Devices” for information on the crystal selection.
differential inputs are capable of interfacing to multiple
3.2.1. Loss-of-Signal (LOS) Alarm Detectors
signals, such as LVPECL, LVDS, HSCL, HCSL, and
CML. Differential signals must be ac-coupled as shown There are two LOS detectors: LOS_CLKIN and
in Figure 3. A termination resistor of 100  placed close LOS_FDBK. These detectors are tied to the outputs of
to the input pins is also required. Refer to Table 6 for the P1 and P2 frequency dividers, which are always
signal voltage limits. enabled. See "3.6. Status Indicators" on page 22 for
details on the alarm indicators. These alarms are used
during programming to ensure that a valid input clock is
0.1 uF
detected. The input MUXs are set automatically in
50 ClockBuilder Desktop (see AN411 to set manually).
IN1 / IN5
100
IN2 / IN6 3.3. Synthesis Stages
50
Next-generation timing applications require a wide
0.1 uF
range of frequencies that are often non-integer related.
Traditional clock architectures address this by using
Rs
50 IN3 / IN4 multiple single PLL ICs, often at the expense of BOM
complexity and power. The Si5338 uses patented
MultiSynth technology to dramatically simplify timing
Figure 3. Interfacing Differential and Single- architectures by integrating the frequency synthesis
Ended Signals to the Si5338 capability of four Phase-Locked Loops (PLLs) in a
single device, greatly reducing size and power
requirements versus traditional solutions.
Rev. 0.6 17
Si5338
Synthesis of the output clocks is performed in two The second stage of synthesis consists of the output
stages, as shown in Figure 5. The first stage consists of MultiSynth dividers (Mx). Based on a fractional N
a high-frequency analog phase-locked loop (PLL) that divider, the MultiSynth divider shown in Figure 6
multiplies the input stage to a frequency within the switches seamlessly between the two closest integer
range of 2.2 to 2.84 GHz. Multiplication of the input divider values to produce the exact output clock
frequency is accomplished using a proprietary and frequency with 0 ppm error.
highly precise MultiSynth feedback divider (N), which To eliminate phase error generated by this process, the
allows the PLL to generate any frequency within its MultiSynth block calculates the relative phase difference
VCO range with much less jitter than typical fractional N between the clock produced by the fractional-N divider
PLL. and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
Synthesis Synthesis approach makes it possible to generate any output
Stage 1 Stage 2
clock frequency without sacrificing jitter performance.
(APLL)
MultiSynth This architecture allows the output of each MultiSynth to
÷M0
From Input Stage
ref 2.2-2.84 GHz produce any frequency from 5 to Fvco/8 MHz. To

Loop
support higher frequency operation, the MultiSynth
Phase VCO divider can be bypassed. In bypass mode, integer divide
To Output Stage
Filter MultiSynth
Frequency
Detector
÷M1 ratios of 4 and 6 are supported. This allows for output
fb frequencies of Fvco/4 and Fvco/6 MHz, which translates
to 367–473.33 MHz and 550–710 MHz respectively.
MultiSynth
÷M2 Because each MultiSynth uses the same VCO output,
MultiSynth there are output frequency limitations when output
÷N frequencies greater than Fvco/8 are desired.
MultiSynth
÷M3
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
Figure 5. Synthesis Stages any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce Fvco/4 = 562.5 MHz or Fvco/6 = 375 MHz. Only
two unique frequencies above Fvco/8 can be output:
Fvco/6 and Fvco/4.
MultiSynth
Fractional-N Phase
fVCO Divider Adjust fOUT
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
Figure 6. Silicon Labs’ MultiSynth Technology
18 Rev. 0.6
Si5338
3.4. Output Stage Each of the outputs can also be enabled or disabled
through the I2C port. A single pin to enable/disable all
The output stage consists of output selectors, output
outputs is available in the Si5338K/L/M.
dividers, and programmable output drivers as shown in
Figure 7. 3.5. Configuring the Si5338
The Si5338 is a highly-flexible clock generator that is
entirely configurable through its I2C interface. The
Output device’s default configuration is stored in non-volatile
Stage
VDDO0 memory (NVM) as shown in Figure 8. The NVM is a
÷R0
CLK0A one-time programmable memory (OTP), which can
CLK0B store a custom user configuration at power-up. This is a
useful feature for applications that need a clock present
From Synthesis Stage
VDDO1
at power-up (e.g., for providing a clock to a processor).
or Input Stage
CLK1A
÷R1
CLK1B Power-Up/POR
VDDO2
CLK2A
÷R2
CLK2B NVM
(OTP)
VDDO3 RAM
CLK3A Default
÷R3
CLK3B Config
Figure 7. Output Stage I2C

The output selectors select the clock source for the Figure 8. Si5338 Memory Configuration
output drivers. By default, each output driver is During a power cycle or a power-on reset (POR), the
connected to its own MultiSynth block (e.g. M0 to CLK0, contents of the NVM are copied into random access
M1 to CLK1, etc), but other combinations are possible memory (RAM), which sets the device configuration that
by reconfiguring the device. The PLL can be bypassed will be used during operation. Any changes to the
by connected the input stage signals (osc, ref, refdiv, fb, device configuration after power-up are made by
or fbdiv) directly to the output divider. Bypassing an reading and writing to registers in the RAM space
input directly to an output will not allow phase alignment through the I2C interface. ClockBuilder Desktop (see
of that output to other outputs. Each of the output "3.1.1. ClockBuilder™ Desktop Software" on page 16)
drivers can also connect to the first MultiSynth block can be used to easily configure register map files that
(M0) enabling a fan-out function. This allows the Si5338 can be written into RAM (see “3.5.2. Creating a New
to act as a clock generator, a fanout buffer, or a Configuration for RAM” for details). Alternatively, the
combination of both in the same package. register map file can be created manually with the help
The output dividers (R0, R1, R2, R3) allow another of the equations in AN411.
stage of clock division.These dividers are configurable Two versions of the Si5338 are available. First,
as divide by 1 (default), 2, 4, 8, 16, or 32. When an Rn standard, non-customized Si5338 devices are available
does not equal 1, the phase alignment function for that in which the RAM can be configured in-circuit via I2C
output will not work. (example part number Si5338C-A-GM). Alternatively,
The output drivers are configurable to support common standard Si5338 devices can be field-programmed
signal formats, such as LVPECL, LVDS, HCSL, CMOS, using the Si5338-PROG-EVB field programmer.
HSTL, and SSTL. Separate output supply pins (VDDOn) Second, custom factory-programmed Si5338 devices
are provided for each output buffer. are available that include a user-specified startup
The voltage on these supply pins can be 3.3, 2.5, 1.8, or frequency configuration (example part number
1.5 V as needed for the possible output formats. Si5338C-Axxxxx-GM).
Additionally, the outputs can be configured to stop high,
low, or tri-state when the PLL has lost lock. If the Si5338
is used in a zero delay mode, the output that is fed back
must be set for always on, which will override any
output disable signal.
Rev. 0.6 19
Si5338
3.5.1. Ordering a Custom NVM Configuration When writing a configuration to RAM, use the following
The Si5338 is orderable with a factory-programmed procedure:
custom NVM configuration. This is the simplest way of 1. Create a device configuration (register map) using
using the Si5338 since it generates the desired output ClockBuilder Desktop (v2.7 or later; see "3.1.1.
frequencies at power-up or after a power-on reset ClockBuilder™ Desktop Software" on page 16) or
(POR). This default configuration can be reconfigured in manually using the equations in “AN411: Configuring
RAM through the I2C interface after power-up (see the Si5338”.
“3.5.2. Creating a New Configuration for RAM”). a. Configure the frequency plan.
The first step in ordering a custom device is generating b. Configure the output driver format and supply
an NVM file which defines the input and output clock voltage.
frequencies and signal formats. This is easily done
c. Configure frequency and/or phase inc/dec (if
using the ClockBuilder Desktop software (see "3.1.1.
desired).
ClockBuilder™ Desktop Software" on page 16). This
GUI based software generates an NVM file, which is d. Configure spread spectrum (if desired).
used by the factory to manufacture custom parts. Each e. Configure for zero-delay mode (if desired,
custom part is marked with a unique part number see "3.9.5. Zero-Delay Mode" on page 24).
identifying the specific configuration (e.g., Si5338C- f. If needed go to the Advanced tab and make
A00100-GM). Consult your local sales representative additional configurations.
for more details on ordering a custom Si5338.
2. Save the configuration using the Options > Save
3.5.2. Creating a New Configuration for RAM Register Map File or Options > Save C code Header
Any Si5338 device can be configured by writing to File, or create the register contents by the
registers in RAM through the I2C interface. A non- conversions listed in AN411.
factory programmed device must be configured in this 3.5.3. Writing a Custom Configuration to RAM
manner.
Writing a new configuration (register map) to the RAM
consists of pausing the LOL state-machine, writing new
values to the IC accounting for the write-allowed mask
given in "6.1. Register Write-Allowed Mask" on page 28,
validating the input clock or crystal, locking the PLL to
the input with the new configuration, restarting the LOL
state-machine, and calibrating the VCO for robust
operation across temperature. The flow chart in
Figure 9 on page 21 enumerates the details:
Note: The write-allowed mask specifies which bits must be
read and modified before writing the entire register
byte (a.k.a. read-modify-write). “AN428: Jump Start: In-
System, Flash-Based Programming for Silicon Labs’
Timing Products” illustrates the procedure defined in
Section 3.5.2 with ANSI C code.
20 Rev. 0.6
Si5338
Disable Outputs
Set OEB_ALL = 1; reg230[4]
Pause LOL
Set DIS_LOL = 1; reg241[7]
Write new configuration to device

Register
accounting for the write-allowed mask
Map
(See Section 6.1)
Use ClockBuilder
Desktop v2.7 or later
Validate input clock status
Input clocks are NO

validated with the
LOS alarms. See
Is input clock valid?
Register 218 to
determine which LOS
should be monitored YES
Configure PLL for locking

Set FCAL_OVRD_EN = 0; reg49[7]
Initiate Locking of PLL

Set SOFT_RESET = 1; reg246[1]
Restart LOL
Set DIS_LOL = 0; reg241[7]
Wait 25 ms
Confirm PLL lock status
NO
PLL is locked when
PLL_LOL, SYS_CAL, and Is PLL locked?
all other alarms are
cleared
YES Copy registers as follows:
237[1:0] to 47[1:0]
Copy FCAL values to 236[7:0] to 46[7:0]
active registers 235[7:0] to 45[7:0]
Set 47[7:2] = 000101b
Set PLL to use FCAL values

Set FCAL_OVRD_EN = 1; reg49[7]
Enable Outputs
Set OEB_ALL = 0; reg230[4]
Figure 9. I2C Programming Procedure
Rev. 0.6 21
Si5338
3.5.4. Modifying a MultiSynth Output Divider Ratio/ 3.6.1. Using the INTR Pin in Systems with I2C
Frequency Configuration
The INTR output pin is not latched and thus it should not
The output MultiSynth dividers of a configured and be a polled input to an MCU but an edge-triggered
phase-locked Si5338 can be modified without relocking interrupt. An MCU can process an interrupt event by
the PLL (i.e. without following section 3.5.3). This reading the sticky register 247 to see what event
feature allows any of the four output frequencies to be caused the interrupt. The same register can be cleared
modified without disturbing the others. by writing zeros to the bits that were set. Individual
In this case, only write the set of registers associated interrupt bits can be masked by register 6[4:0].
with the output MultiSynth divider (MultiSynth
3.6.2. Using the INTR Pin in Systems without I2C
Frequency Configuration; see Section 6.2). The
feedback MultiSynth must not be modified unless The INTR pin also provides a useful function in systems
following the procedure in Section 3.5.3. that require a pin-controlled fault indicator. Pre-setting
the interrupt mask register allows the INTR pin to
To avoid intermediate frequencies, it is recommended
become an indicator for a specific event, such as LOS
that the output be disabled before changing the divider
and/or LOL. Therefore, the INTR pin can be used to
ratio (see Register 230).
indicate a single fault event or even multiple events.
Any output MultiSynth that is reconfigured will lose its
phase alignment with the other outputs. SOFT_RESET Control & Memory
can be used to resynchronize the outputs (see "3.8. VDD
Reset Options" on page 23).
NVM
3.5.5. Writing a Custom Configuration to NVM 1k Control RAM
(OTP)
An alternative to ordering an Si5338 with a custom NVM INTR
configuration is to use the field programming kit
(Si5338-PROG-EVB) to write directly to the NVM of a
"blank" Si5338. Since NVM is an OTP memory, it can
only be written once. The default configuration can be Figure 11. INTR Pin with Required Pull-Up
reconfigured by writing to RAM through the I2C interface 3.7. Output Enable
(see “3.5.2. Creating a New Configuration for RAM”).
There are two methods of enabling and disabling the
3.6. Status Indicators output drivers: Pin control, and I2C control.
A logic-high interrupt pin (INTR) is available to indicate 3.7.1. Enabling Outputs Using Pin Control
a loss of signal (LOS) condition, a PLL loss of lock
The Si5338K/L/M devices provide an Output Enable pin
(PLL_LOL) condition, or that the PLL is in process of
(OEB) as shown in Figure 12. Pulling this pin high will
acquiring lock (SYS_CAL). PLL_LOL is held high when
turn all outputs off. The state of the individual drivers
the input frequency drifts beyond the PLL lock range. It
when turned off is controllable. If an individual output is
is held low during all other times and during a POR or
set to always on, then the OEB pin will not have an
soft reset. SYS_CAL is held high during a POR or SOFT
effect on that driver. Drive state options and always on
reset so that no chattering occurs during the locking
are explained in “3.7.2. Enabling Outputs through the
process. As shown in Figure 10, a status register at
I2C Interface”.
address 218 is available to help identify the exact event
that caused the interrupt pin to become active. Control & Memory
7 6 5 4 3 2 1 0
218 PLL_LOL LOS_FDBK LOS_CLKIN

Sys NVM
Cal Control RAM
(OTP)
System Calibration
(Lock Acquisition)
0 = Enabled OEB
1 = Disabled
Loss Of Signal
Clock Input
Loss Of Signal
Feedback Input Figure 12. Output Enable Pin (Si5338K/L/M)
Loss Of Lock
Figure 10. Status Register

Figure 11 shows a typical connection with the required
pull-up resistor to VDD.
22 Rev. 0.6
Si5338
3.7.2. Enabling Outputs through the I2C Interface 3.8. Reset Options
Output enable can be controlled through the I2C There are two types of resets on the Si5338, POR and
interface. As shown in Figure 13, register 230[3:0] soft reset. A POR reset automatically occurs whenever
allows control of each individual output driver. Register the supply voltage on the VDD is applied.
230[4] controls all drivers at once. When register 230[4] The soft reset is forced by writing 0x02 to register 246.
is set to disable all outputs, the individual output This bit is not self-clearing, and thus it may read back as
enables will have no effect. Registers 110[7:6], 114[7:6], a 1 or a 0. A soft reset will not download any pre-
118[7:6], and 112[7:6] control the output disabled state programmed NVM and will not change any register
as tri-state, low, high, or always on. If always on is set, values in RAM.
that output will always be on regardless of any other
The soft reset performs the following sequence:
register or chip state. In addition, the always on mode
must be selected for an output that is fed back in a Zero 1. All outputs turn off except if programmed to be
Delay application. always on.
2. Internal calibrations are done and MultiSynths are
initialized.
7 6 5 4 3 2 1 0
OEB OEB OEB OEB OEB a. Outputs that are synchronous are phase
230 All 3 2 1 0 aligned (if Rn = 1).
3. 25 ms is allowed for the PLL to lock (no delay occurs
0 = enable Bits reserved
1 = disable when FCAL_OVRD_EN = 1).
4. Turn on all outputs that were turned off in step 1.
3.9. Features of the Si5338
7 6 5 4 3 2 1 0
CLK0 OEB
The Si5338 offers several features and functions that
110 are useful in many timing applications. The following
State
paragraphs describe in detail the main features and
7 6 5 4 3 2 1 0
typical applications. All of these features can be easily
CLK1 OEB
configured using the ClockBuilder Desktop. See "3.1.1.
114 ClockBuilder™ Desktop Software" on page 16.
State
3.9.1. Frequency Increment/Decrement

7 6 5 4 3 2 1 0 Each of the output clock frequencies can be
118 CLK2 OEB independently stepped up or down in predefined steps
State
as low as 1 ppm per step and with a resolution of
1 ppm. Setting of the step size and control of the
7 6 5 4 3 2 1 0
frequency increment or decrement is accomplished
122 CLK3 OEB
State
through the I2C interface. Alternatively, the Si5338 can
be ordered with optional frequency increment (FINC)
00 = disabled tri-state
and frequency decrement (FDEC) pins for pin-
Bits used by other functions
01 = disabled low controlled applications. See Table 18 for ordering
10 = disabled high
11 = always enabled
information of pin-controlled devices.
The frequency increment and decrement feature is
Figure 13. Output Enable Control Registers useful in applications requiring a variable clock
frequency (e.g., CPU speed control, FIFO overflow
management, etc.) or in applications where frequency
margining (e.g., fout ±5%) is necessary for design
verification and manufacturing test. Frequency
increment or decrement can be applied as fast as
1.5 MHz when it is done by pin control. When under I2C
control, the frequency increment and decrement update
rate is limited by the I2C bus speed. The magnitude of
the frequency step has 0 ppm error. Frequency steps
are seamless and glitchless.
Rev. 0.6 23
Si5338
3.9.2. Output Phase Increment/Decrement Non-unity settings of R0 will affect the Finc/Fdec step
The Si5338 has a digitally-controlled glitchless phase size at the MultiSynth0 output. For example, if the
increment and decrement feature that allows adjusting MultiSynth0 output step size is 2.56 MHz and R0 = 8,
the phase of each output clock in relation to the other the step size at the output of R0 will be 2.56 MHz
output clocks. The phase of each output clock can be divided by 8 = .32 MHz. When the Rn divider is set to
adjusted with an accuracy of 20 ps over a range of non-unity, the initial phase of the CLKn output with
±45 ns. Setting of the step size and control of the phase respect to other CLKn outputs is not guaranteed.
increment or decrement is accomplished through the 3.9.5. Zero-Delay Mode
I2C interface. Alternatively, the Si5338 can be ordered The Si5338 supports an optional zero delay mode of
with optional phase increment (PINC) and phase operation for applications that require minimal input-to-
decrement (PDEC) pins for pin-controlled applications. output delay. In this mode, one of the device output
In pin controlled applications the phase increment and clocks is fed back to the feedback input pin (IN4 or IN5/
decrement update rate is as fast as 1.5 MHz. In I2C IN6) to implement an external feedback path essentially
applications, the maximum update rate is limited by the nullifying the delay between the reference input and the
speed of the I2C. See Table 18 for ordering information output clocks. Figure 14 shows the Si5338 in a typical
of pin-controlled devices. zero-delay configuration. It is generally recommended
The phase increment and decrement feature provides a that Clk3 be LVDS and that the feedback input be pins 5
useful method for fine tuning setup and hold timing and 6. For the differential input configuration to pins 5
margins or adjusting for mismatched PCB trace lengths. and 6, see Figure 3 on page 17. The zero-delay mode
3.9.3. Initial Phase Offset combined with the phase increment/decrement feature
allows unprecedented flexibility in generating clocks
Each output clock can be set for its initial phase offset
with precise edge alignment.
up to ±45 ns. In order for the initial phase offset to be
applied correctly at power up, the VDDOx output supply
Si5338
voltage must cross 1.2 V before the VDD (pins 7,24)
core power supply voltage crosses 1.45 V. This applies
to the each driver output individually. A soft_reset will M0 R0 Clk0
also guarantee that the programmed Initial Phase Offset
Clk
is applied correctly. The initial phase offset only works Input
P1 M1 R1 Clk1
on outputs that have their R divider set to 1. PLL
3.9.4. Output R Divider P2 M2 R2 Clk2
When the requested output frequency of a channel is
below 5 MHz, the Rn (n = 0,1,2,3) divider needs to be M3 R3 Clk3
set and enabled. This is automatically done in register
maps generated by the ClockBuilder Desktop. When
the Rn divider is active the step size range of the
frequency increment and decrement function will Figure 14. Si5338 in Zero Delay Clock
decrease by the Rn divide ratio. The Rn divider can be Generator Mode
set to {1, 2, 4, 8, 16, 32}.
24 Rev. 0.6
Si5338
3.9.6. Spread Spectrum 4. Applications of the Si5338
To help reduce electromagnetic interference (EMI), the
Si5338 supports spread spectrum modulation. The Because of its flexible architecture, the Si5338 can be
output clock frequencies can be modulated to spread configured to serve several functions in the timing path.
energy across a broader range of frequencies, lowering The following sections describe some common
system EMI. The Si5338 implements spread spectrum applications.
using its patented MultiSynth technology to achieve 4.1. Free-Running Clock Generator
previously unattainable precision in both modulation
rate and spreading magnitude as shown in Figure 15. Using the internal oscillator (Osc) and an inexpensive
Spread spectrum can be applied to any output clock, external crystal (XTAL), the Si5338 can be configured
any clock frequency, and any spread amount. The as a free-running clock generator for replacing high-end
device supports center spread (±0.1% to ±5%) and and long-lead-time crystal oscillators found on many
down spread (–0.1% to –5%). In addition, the device printed circuit boards (PCBs). Replacing several crystal
has extensive on-chip voltage regulation so that power oscillators with a single IC solution helps consolidate the
supply variations do not influence the device’s spread- bill of materials (BOM), reduces the number of
spectrum clock waveforms. suppliers, and reduces the number of long-lead-time
components on the PCB. In addition, since crystal
20
oscillators tend to be the least reliable aspect of many
systems, the overall FIT rate improves with the
+/- 0%
10
elimination of each oscillator.
+/- 1%
0
+/- 2.5% Up to four independent clock frequencies can be
+/- 5% generated at any rate within its supported frequency
-10
range and with any of supported output types. Features,
such as frequency increment and decrement and phase
Power Spectrum (dBm)
-20
adjustments on a per-output basis, provide

-30
unprecedented flexibility for PCB designs. Figure 16
-40 shows the Si5338 configured as a free-running clock
generator.
-50
-60
ref
XTAL Osc PLL M0 R0 F0
-70
-80
-10% -8% -6% -4% -2% 0% 2% 4% 6% 8% 10%
M1 R1 F1
Relative Frequency
M2 R2 F2
Figure 15. Configurable Spread Spectrum
M3 R3 F3
Si5338
Figure 16. Si5338 as a Free-Running Clock

Generator
Rev. 0.6 25
Si5338
4.2. Synchronous Frequency Translation 4.3. Configurable Buffer and Level
In other cases, it is useful to generate an output Translator
frequency that is synchronous (or phase-locked) to Using the output selectors, the synthesis stage can be
another clock frequency. The Si5338 is the ideal choice entirely bypassed allowing the Si5338 to act as a
for generating up to four clocks with different configurable clock buffer/divider with level translation
frequencies with a fixed phase relationship to an input and selectable inputs. Because of its highly selectable
reference. Because of its highly precise frequency configuration, virtually any combination is possible. The
synthesis, the Si5338 can generate all four output configurable output drivers allow four differential
frequencies with 0 ppm error to the input reference. The outputs, eight single-ended outputs, or a combination of
Si5338 is an ideal choice for applications that have both. Figure 18 shows the Si5338 configured as a
traditionally required multiple stages of frequency flexible clock buffer.
synthesis to achieve complex frequency translations.
Examples are in broadcast video (e.g., 148.5 MHz to
148.351648351648 MHz), WAN/LAN applications (e.g. S i5 3 3 8
1
R0 F in *
155.52 MHz to 156.25 MHz), and Forward Error R0
Correction (FEC) applications (e.g., 156.25 MHz to
1
161.1328125 MHz). Using the input reference selectors, R1 F in *
R1
the Si5338 can select from one of four inputs (IN1/IN2, F in
IN3, IN4, and IN5/IN6). Figure 17 shows the Si5338 R2 F in *
1
configured as a synchronous clock generator. R2
Frequencies and multiplication ratios may be entered 1
R3 F in *
into ClockBuilder Desktop using fractional notation to R3
ensure that the exact scaling ratios can be achieved.
Figure 18. Si5338 as a Configurable Clock
Si5338 Buffer/Divider with Level Translation
M0 R0 F0
4.3.1. Combination Free-Running and Synchronous
Clock Generator
P1 M1 R1 F1
ref Another application of the Si5338 is in generating both
Fin PLL
P2
free-running and synchronous clocks in one device.
M2 R2 F2
This is accomplished by configuring the input and
output selectors for the desired split configuration. An
M3 R3 F3
example of such an application is shown in Figure 19.
Figure 17. Si5338 as a Synchronous Clock Si5338

Generator or Frequency Translator
XTAL Osc R0 F0
R1 F1
M0 R2 F2
F in ref
P2 PLL
M1 R3 F3
Figure 19. Si5338 In a Free-Running and

Synchronous Clock Generator Application
26 Rev. 0.6
Si5338
5. I2C Interface Write Operation – Single Byte
Configuration and operation of the Si5338 is controlled S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P
by reading and writing to the RAM space using the I2C
interface. The device operates in slave mode with 7-bit
addressing and can operate in Standard-Mode Write Operation - Burst (Auto Address Increment)
(100 kbps) or Fast-Mode (400 kbps) and supports burst S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P
data transfer with auto address increments.
Reg Addr +1
The I2C bus consists of a bidirectional serial data line
(SDA) and a serial clock input (SCL) as shown in
1 – Read
Figure 20. Both the SDA and SCL pins must be From slave to master
0 – Write
connected to the VDD supply via an external pull-up as From master to slave A – Acknowledge (SDA LOW)
recommended by the I2C specification. N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
OEB/PINC/FINC
Figure 22. I2C Write Operation
VDD
I2C_LSB I2C_LSB/PDEC/FDEC
0/1 A read operation is performed in two stages. A data
Control write is used to set the register address, then a data
SCL
I2C Bus SDA
read is performed to retrieve the data from the set
address. A read burst operation is also supported. This
is shown in Figure 23.
Figure 20. I2C and Control Signals
Read Operation – Single Byte
The 7-bit device (slave) address of the Si5338 consists
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
of a 6-bit fixed address plus a user-selectable LSB bit as
shown in Figure 21. The LSB bit is selectable using the S Slv Addr [6:0] 1 A Data [7:0] N P
optional I2C_LSB pin which is available as an ordering
option for applications that require more than one
Si5338 on a single I2C bus. Devices without the Read Operation - Burst (Auto Address Increment)
I2C_LSB pin option have a fixed 7-bit address of 70h
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
(111 0000) as shown in Figure 21. Other custom I2C
addresses are also possible. See Table 18 for details on S Slv Addr [6:0] 1 A Data [7:0] A Data [7:0] N P
device ordering information with the optional I2C_LSB
pin. Reg Addr +1
6 5 4 3 2 1 0
Slave Address 1 – Read
(with I2C_LSB Option) 1 1 1 0 0 0 0/1 From slave to master
0 – Write
I2C_LSB pin From master to slave A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
6 5 4 3 2 1 0 P – STOP condition
Slave Address
(without I2C_LSB Option) 1 1 1 0 0 0 0
Figure 23. I2C Read Operation
AC and DC electrical specifications for the SCL and
Figure 21. Si5338 I2C Slave Address SDA pins are shown in Table 14. The timing
Data is transferred MSB first in 8-bit words as specified specifications and timing diagram for the I2C bus are
by the I2C specification. A write command consists of a compatible with the I2C-Bus Standard. SDA timeout is
7-bit device (slave) address + a write bit, an 8-bit supported for compatibility with SMBus interfaces.
register address, and 8 bits of data as shown in The I2C bus can be operated at a bus voltage of 1.71 to
Figure 22. A write burst operation is also shown where 3.63 V and is 3.3 V tolerant. If a bus voltage of less than
every additional data word is written using an auto- 2.5 V is used, register 27[7] = 1 must be written to
incremented address. maintain compatibility with the I2C bus standard.
Rev. 0.6 27
Si5338
6. Si5338 Registers 0xFF, all the bits in the register can be changed. All
other registers require a read-modify-write procedure to
This section describes the registers and their usage in write to the registers. ClockBuilder Desktop can be used
detail. These values are easily configured using to create ANSI C code (Options  Save C code header
ClockBuilder Desktop (see "3.1.1. ClockBuilder™ file) with the register contents and mask values. AN428
Desktop Software" on page 16). See AN428 for a demonstrates the usage of this header file and the read-
working example using Silicon Labs' F301 MCU. modify-write procedure.
6.1. Register Write-Allowed Mask The following code demonstrates the application of the
above write allowed mask.
The masks listed in Table 15 indicate which bits in each
 Let addr be the address of the register to access.
register of the Si5338 can be modified and which bits
 Let data be the data or value to write to the register
cannot. Therefore, these masks are write-allowed or
write-enabled bits. These masks must be used to located at addr.
perform a read-modify-write on each register.  Let mask be the write-allowed bits defined for the
corresponding register.
If a mask is 0x00, all bits in the associated register are
reserved and must remain unchanged. If the mask is
// ignore registers with masks of 0x00

if(mask != 0x00){
if(mask == 0xFF){
// do a regular I2C write to the register
// at addr with the desired data value
write_Si5338(addr, data);
} else {
// do a read-modify-write using I2C and
// bit-wise operations
// get the current value from the device at the

// register located at addr
curr_val = read_Si5338(addr);
// clear the bits that are allowed to be

// accessed in the current value of the register
clear_curr_val = curr_val AND (NOT mask);
// clear the bits in the desired data that

// are not allowed to be accessed
clear_new_val = data AND mask;
// combine the cleared values to get the new

// value to write to the desired register
combined = clear_curr_val OR clear_new_val;
write_Si5338(addr, combined);
}
28 Rev. 0.6
Si5338
Table 15. Register Write-Allowed Masks

Address (Decimal) Mask (Hex)
0 0x00
1 0x00
2 0x00
3 0x00
4 0x00
5 0x00
6 0x1D
7 0x00
8 0x00
9 0x00
10 0x00
11 0x00
12 0x00
13 0x00
14 0x00
15 0x00
16 0x00
17 0x00
18 0x00
19 0x00
20 0x00
21 0x00
22 0x00
23 0x00
24 0x00
25 0x00
26 0x00
27 0x80
28 0xFF
*Note: See Figure 9, “I2C Programming Procedure,” on page 21 for the
correct usage of registers 230, 241, and 246. These registers are
not saved in the register map or C code header file from
ClockBuilder Desktop (v2.7 or later).
Rev. 0.6 29
Si5338
Table 15. Register Write-Allowed Masks (Continued)
29 0xFF
30 0xFF
31 0xFF
32 0xFF
33 0xFF
34 0xFF
35 0xFF
36 0x1F
37 0x1F
38 0x1F
39 0x1F
40 0xFF
41 0x7F
42 0x3F
43 0x00
44 0x00
45 0xFF
46 0xFF
47 0x3F
48 0xFF
49 0xFF
50 0xFF
51 0xFF
52 0x7F
53 0xFF
54 0xFF
55 0xFF
56 0xFF
57 0xFF
30 Rev. 0.6
Si5338
58 0xFF
59 0xFF
60 0xFF
61 0xFF
62 0x3F
63 0x7F
64 0xFF
65 0xFF
66 0xFF
67 0xFF
68 0xFF
69 0xFF
70 0xFF
71 0xFF
72 0xFF
73 0x3F
74 0x7F
75 0xFF
76 0xFF
77 0xFF
78 0xFF
79 0xFF
80 0xFF
81 0xFF
82 0xFF
83 0xFF
84 0x3F
85 0x7F
86 0xFF
Rev. 0.6 31
Si5338
87 0xFF
88 0xFF
89 0xFF
90 0xFF
91 0xFF
92 0xFF
93 0xFF
94 0xFF
95 0x3F
96 0x00
97 0xFF
98 0xFF
99 0xFF
100 0xFF
101 0xFF
102 0xFF
103 0xFF
104 0xFF
105 0xFF
106 0xBF
107 0xFF
108 0x7F
109 0xFF
110 0xFF
111 0xFF
112 0x7F
113 0xFF
114 0xFF
115 0xFF
32 Rev. 0.6
Si5338
116 0xFF
117 0xFF
118 0xFF
119 0xFF
120 0xFF
121 0xFF
122 0xFF
123 0xFF
124 0xFF
125 0xFF
126 0xFF
127 0xFF
128 0xFF
129 0x0F
130 0x0F
131 0xFF
132 0xFF
133 0xFF
134 0xFF
135 0xFF
136 0xFF
137 0xFF
138 0xFF
139 0xFF
140 0xFF
141 0xFF
142 0xFF
143 0xFF
144 0xFF
Rev. 0.6 33
Si5338
145 0x00
146 0x00
147 0x00
148 0x00
149 0x00
150 0x00
151 0x00
152 0xFF
153 0xFF
154 0xFF
155 0xFF
156 0xFF
157 0xFF
158 0x0F
159 0x0F
160 0xFF
161 0xFF
162 0xFF
163 0xFF
164 0xFF
165 0xFF
166 0xFF
167 0xFF
168 0xFF
169 0xFF
170 0xFF
171 0xFF
172 0xFF
173 0xFF
34 Rev. 0.6
Si5338
174 0xFF
175 0xFF
176 0xFF
177 0xFF
178 0xFF
179 0xFF
180 0xFF
181 0x0F
182 0xFF
183 0xFF
184 0xFF
185 0xFF
186 0xFF
187 0xFF
188 0xFF
189 0xFF
190 0xFF
191 0xFF
192 0xFF
193 0xFF
194 0xFF
195 0xFF
196 0xFF
197 0xFF
198 0xFF
199 0xFF
200 0xFF
201 0xFF
202 0xFF
Rev. 0.6 35
Si5338
203 0x0F
204 0xFF
205 0xFF
206 0xFF
207 0xFF
208 0xFF
209 0xFF
210 0xFF
211 0xFF
212 0xFF
213 0xFF
214 0xFF
215 0xFF
216 0xFF
217 0xFF
218 0x00
219 0x00
220 0x00
221 0x00
222 0x00
223 0x00
224 0x00
225 0x00
226 0x04
227 0x00
228 0x00
229 0x00
230* 0xFF
231 0x00
36 Rev. 0.6
Si5338
232 0x00
233 0x00
234 0x00
235 0x00
236 0x00
237 0x00
238 0x00
239 0x00
240 0x00
241* 0xFF
242 0x02
243 0x00
244 0x00
245 0x00
246* 0xFF
247 0x00
248 0x00
249 0x00
250 0x00
251 0x00
252 0x00
253 0x00
254 0x00
255 0xFF
256 0x00
257 0x00
258 0x00
259 0x00
260 0x00
Rev. 0.6 37
Si5338
261 0x00
262 0x00
263 0x00
264 0x00
265 0x00
266 0x00
267 0x00
268 0x00
269 0x00
270 0x00
271 0x00
272 0x00
273 0x00
274 0x00
275 0x00
276 0x00
277 0x00
278 0x00
279 0x00
280 0x00
281 0x00
282 0x00
283 0x00
284 0x00
285 0x00
286 0x00
287 0xFF
288 0xFF
289 0xFF
38 Rev. 0.6
Si5338
290 0xFF
291 0xFF
292 0xFF
293 0xFF
294 0xFF
295 0xFF
296 0xFF
297 0xFF
298 0xFF
299 0x0F
300 0x00
301 0x00
302 0x00
303 0xFF
304 0xFF
305 0xFF
306 0xFF
307 0xFF
308 0xFF
309 0xFF
310 0xFF
311 0xFF
312 0xFF
313 0xFF
314 0xFF
315 0x0F
316 0x00
317 0x00
318 0x00
Rev. 0.6 39
Si5338
319 0xFF
320 0xFF
321 0xFF
322 0xFF
323 0xFF
324 0xFF
325 0xFF
326 0xFF
327 0xFF
328 0xFF
329 0xFF
330 0xFF
331 0x0F
332 0x00
333 0x00
334 0x00
335 0xFF
336 0xFF
337 0xFF
338 0xFF
339 0xFF
340 0xFF
341 0xFF
342 0xFF
343 0xFF
344 0xFF
345 0xFF
346 0xFF
347 0x0F
40 Rev. 0.6
Si5338
348 0x00
349 0x00
350 0x00
Rev. 0.6 41
Si5338
6.2. Register Categories
This is a list of registers needed to define the Configuration of a device. Set the PAGEBIT to access registers with
addresses greater than 255.
Address (Decimal) Bits Function

6 4:0 Mask bits for LOS_CLKIN,LOS_FB, LOL, SYS_CAL
27 7:6
I2C Configuration
27 7
28 - 30 7:0 Input Mux Configuration
31 - 39 7:0 Output Configuration
40 7:0
41 6:0 Output Driver Trim Bits
42 4:0
47 5:2 Input Configuration
48 7:0
49 6:0
PLL Configuration
50 7:0
51 7:4, 2:0
52 6:0 MultiSynth0 Freq inc/dec, SS, Phase inc/dec Configuration
53-61 7:0
MultiSynth0 frequency Configuration
62 5:0
63 6:0
64-72 7:0 MultiSynth1 frequency Configuration
73 5:0
74 6:0
84 5:0
85 6:0
95 5:0
97-105 7:0
MultiSynthN Feedback divider Configuration
106 5:0
107 - 110 7:0 MultiSynth0 Phase inc/dec, SS Configuration, drive state
42 Rev. 0.6
Si5338
119 7:0
120 6:0 MultiSynth3 Phase inc/dec, SS Configuration, drive state
121 - 122 7:0
123-128 7:0
129 3:0
MultiSynth0 freq inc/dec Configuration, ID config
130 6:0
131 - 144 7:0
152 - 173 7:0 MultiSynth1 freq inc/dec Configuration
174 - 195 7:0 MultiSynth2 freq inc/dec Configuration
196 - 216 7:0
MultiSynth3 freq inc/dec Configuration
217 6:0
241 7:0 Reserved - set to 0x65 if not factory-programmed.
287 7:0
288 6:0
289 7:0
290 6:0
291 7:0
292 7:0
293 7:0 MultiSynth0 spread spectrum Configuration
294 7:0
295 6:0
296 7:0
297 6:0
298 7:0
299 7:0
Rev. 0.6 43
Si5338
303 7:0
304 6:0
305 7:0
306 6:0
307 7:0
308 7:0
310 7:0
311 6:0
312 7:0
313 6:0
314 7:0
315 7:0
319 7:0
320 6:0
321 7:0
322 6:0
323 7:0
324 7:0
326 7:0
327 6:0
328 7:0
329 6:0
330 7:0
331 7:0
44 Rev. 0.6
Si5338
335 7:0
336 6:0
337 7:0
338 6:0
339 7:0
340 7:0
342 7:0
343 6:0
344 7:0
345 6:0
346 7:0
347 7:0
Rev. 0.6 45
Si5338
6.3. Register Summary
Table 16. Register Summary

Register 7 6 5 4 3 2 1 0
0 REVID[2:0]
PLL_LOL_ LOS_FDBK_ LOS_CLKIN_ SYS_CAL_

6
MASK MASK MASK MASK
27 I2C_1P8_SEL I2C_ADDR[6:0]
28 FDBK_PDN P2DIV_IN[0] P1DIV_IN[2:0] XTAL_FREQ[1:0]
29 PFD_IN_REF[2:0] P1DIV_IN[4:3] P1DIV[2:0]
30 PFD_IN_FB[2:0] P2DIV_IN[2:1] P2DIV[2:0]
31 R0DIV_IN[2:0] R0DIV[2:0] MS0_PDN DRV0_PDN
35 DRV3_VDDO[1:0] DRV2_VDDO[1:0] DRV1_VDDO[1:0] DRV0_VDDO[1:0]
36 DRV0_INV[1:0] DRV0_FMT[2:0]
40 DRV1_TRIM[2:0] DRV0_TRIM[4:0]
41 DRV2_TRIM[4:0] DRV1_TRIM[4:3]
42 DRV3_TRIM[4:0]
45 FCAL_OVRD[7:0]
46 FCAL_OVRD[15:8]
47 FCAL_OVRD[17:16]
48 PFD_EXTFB PLL_KPHI[6:0]
49 FCAL_OVRD_EN VCO_GAIN[2:0] RSEL[1:0] BWSEL[1:0]
50 PLL_ENABLE[1:0] MSCAL[5:0]
51 MS3_HS MS2_HS MS1_HS MS0_HS MS_PEC[2:0]
52 MS0_FIDCT[1:0] MS0_FIDDIS MS0_SSMODE[1:0] MS0_PHIDCT[1:0]
53 MS0_P1[7:0]
54 MS0_P1[15:8]
55 MS0_P2[5:0] MS0_P1[17:16]
56 MS0_P2[13:6]
57 MS0_P2[21:14]
58 MS0_P2[29:22]
59 MS0_P3[7:0]
46 Rev. 0.6
Si5338
Table 16. Register Summary (Continued)
Register 7 6 5 4 3 2 1 0
60 MS0_P3[15:8]
61 MS0_P3[23:16]
62 MS0_P3[29:24]
63 MS1_FIDCT[1:0] MS1_FIDDIS MS1_SSMODE[1:0] MS1_PHIDCT[1:0]
64 MS1_P1[7:0]
65 MS1_P1[15:8]
66 MS1_P2[5:0] MS1_P1[17:16]
67 MS1_P2[13:6]
68 MS1_P2[21:14]
69 MS1_P2[29:22]
70 MS1_P3[7:0]
71 MS1_P3[15:8]
72 MS1_P3[23:16]
73 MS1_P3[29:24]
74 MS2_FRCTL[1:0] MS2_FIDDIS MS2_SSMODE[1:0] MS2_PHIDCT[1:0]
75 MS2_P1[7:0]
76 MS2_P1[15:8]
77 MS2_P2[5:0] MS2_P1[17:16]
78 MS2_P2[13:6]
79 MS2_P2[21:14]
80 MS2_P2[29:22]
81 MS2_P3[7:0]
82 MS2_P3[15:8]
83 MS2_P3[23:16]
84 MS2_P3[29:24]
85 MS3_FIDCTL[1:0] MS3_FIDDIS MS3_SSMODE[1:0] MS3_PHIDCTL[1:0]
86 MS3_P1[7:0]
87 MS3_P1[15:8]
88 MS3_P2[5:0] MS3_P1DIV[17:16]
89 MS3_P2[13:6]
90 MS3_P2[21:14]
91 MS3_P2[29:22]
92 MS3_P3[7:0]
93 MS3_P3[15:8]
94 MS3_P3[23:16]
95 MS3_P3[29:24]
Rev. 0.6 47
Si5338
Register 7 6 5 4 3 2 1 0
97 MSN_P1[7:0]
98 MSN_P1[15:8]
99 MSN_P2[5:0] MSN_P1[17:16]
100 MSN_P2[13:6]
101 MSN_P2[21:14]
102 MSN_P2[29:22]
103 MSN_P3[7:0]
104 MSN_P3[15:8]
105 MSN_P3[23:16]
106 MSN_P3[29:24]
107 MS0_PHOFF[7:0]
108 MS0_PHOFF[14:8]
109 MS0_PHSTEP[7:0]
110 CLK0_DISST[1:0] MS0_PHSTEP[13:8]
111 MS1_PHOFF[7:0]
112 MS1_PHOFF[14:8]
113 MS1_PHSTEP[7:0]
115 MS2_PHOFF[7:0]
116 MS2_PHOFF[14:8]
117 MS2_PHSTEP[7:0]
119 MS3_PHOFF[7:0]
120 MS3_PHOFF[14:8]
121 MS3_PHSTEP[7:0]
123 MS0_FIDP1[7:0]
124 MS0_FIDP1[15:8]
125 MS0_FIDP1[23:16]
126 MS0_FIDP1[31:24]
127 MS0_FIDP1[39:32]
128 MS0_FIDP1[47:40]
129 MS0_FIDP1[51:48]
130 MS0_FIDP2[51:48]
131 MS0_FIDP2[47:40]
132 MS0_FIDP2[39:32]
48 Rev. 0.6
Si5338
Register 7 6 5 4 3 2 1 0
133 MS0_FIDP2[31:24]
134 MS0_FIDP2[23:16]
135 MS0_FIDP2[15:8]
136 MS0_FIDP2[7:0]
137 MS0_FIDP3[7:0]
138 MS0_FIDP3[15:8]
139 MS0_FIDP3[23:16]
140 MS0_FIDP3[31:24]
141 MS0_FIDP3[39:32]
142 MS0_FIDP3[47:40]
143 MS0_FIDP3[51:48]
144 MS0_ALL MS0_FIDP3[62:56]
152 MS1_FIDP1[7:0]
153 MS1_FIDP1[15:8]
154 MS1_FIDP1[23:16]
155 MS1_FIDP1[31:24]
156 MS1_FIDP1[39:32]
157 MS1_FIDP1[47:40]
158 MS1_FIDP1[51:48]
159 MS1_FIDP2[51:48]
160 MS1_FIDP2[47:40]
161 MS1_FIDP2[39:32]
162 MS1_FIDP2[31:24]
163 MS1_FIDP2[23:16]
164 MS1_FIDP2[15:8]
165 MS1_FIDP2[7:0]
166 MS1_FIDP3[7:0]
167 MS1_FIDP3[15:8]
168 MS1_FIDP3[23:16]
169 MS1_FIDP3[31:24]
170 MS1_FIDP3[39:32]
171 MS1_FIDP3[47:40]
172 MS1_FIDP3[51:48]
173 MS1_FIDP3[62:56]
174 MS2_FIDP1[7:0]
175 MS2_FIDP1[15:8]
Rev. 0.6 49
Si5338
Register 7 6 5 4 3 2 1 0
176 MS2_FIDP1[23:16]
177 MS2_FIDP1[31:24]
178 MS2_FIDP1[39:32]
179 MS2_FIDP1[47:40]
180 MS2_FIDP1[51:48]
181 MS2_FIDP2[51:48]
182 MS2_FIDP2[47:40]
183 MS2_FIDP2[39:32]
184 MS2_FIDP2[31:24]
185 MS2_FIDP2[23:16]
186 MS2_FIDP2[15:8]
187 MS2_FIDP2[7:0]
188 MS2_FIDP3[7:0]
189 MS2_FIDP3[15:8]
190 MS2_FIDP3[23:16]
191 MS2_FIDP3[31:24]
192 MS2_FIDP3[39:32]
193 MS2_FIDP3[47:40]
194 MS2_FIDP3[51:48]
195 MS2_FIDP3[62:56]
196 MS3_FIDP1[7:0]
197 MS3_FIDP1[15:8]
198 MS3_FIDP1[23:16]
199 MS3_FIDP1[31:24]
200 MS3_FIDP1[39:32]
201 MS3_FIDP1[47:40]
202 MS3_FIDP1[51:48]
203 MS3_FIDP2[51:48]
204 MS3_FIDP2[47:40]
205 MS3_FIDP2[39:32]
206 MS3_FIDP2[31:24]
207 MS3_FIDP2[23:16]
208 MS3_FIDP2[15:8]
209 MS3_FIDP2[7:0]
210 MS3_FIDP3[7:0]
211 MS3_FIDP3[15:8]
50 Rev. 0.6
Si5338
Register 7 6 5 4 3 2 1 0
212 MS3_FIDP3[23:16]
213 MS3_FIDP3[31:24]
214 MS3_FIDP3[39:32]
215 MS3_FIDP3[47:40]
216 MS3_FIDP3[51:48]
217 MS3_FIDP3[62:56]
218 PLL_LOL LOS_FDBK LOS_CLKIN SYS_CAL
230 OEB_ALL OEB_3 OEB_2 OEB_1 OEB_0
235 FCAL[7:0]
236 FCAL[15:8]
237 FCAL[17:16]
241 DIS_LOL
242 DCLK_DIS
246 SOFT_RESET
LOS_FDBK_ LOS_CLKIN_
247 PLL_LOL_STK SYS_CAL_STK
STK STK
255 PAGE_SEL
287 MS0_SSUPP2[7:0]
288 MS0_SSUPP2[14:8]
289 MS0_SSUPP3[7:0]
290 MS0_SSUPP3[14:8]
291 MS0_SSUPP1[7:0]
292 MS0_SSUDP1[3:0] MS0_SSUPP1[11:8]
293 MS0_SSUDP1[11:4]
294 MS0_SSDNP2[7:0]
295 MS0_SSDNP2[14:8]
296 MS0_SSDNP3[7:0]
297 MS0_SSDNP3[14:8]
298 MS0_SSDNP1[7:0]
299 MS0_SSDNP1[11:8]
303 MS1_SSUPP2[7:0]
304 MS1_SSUPP2[14:8]
305 MS1_SSUPP3[7:0]
306 MS1_SSUPP3[14:8]
307 MS1_SSUPP1[7:0]
308 MS1_SSUDP1[3:0] MS1_SSUPP1[11:8]
Rev. 0.6 51
Si5338
Register 7 6 5 4 3 2 1 0
309 MS1_SSUDP1[11:4]
310 MS1_SSDNP2[7:0]
311 MS1_SSDNP2[14:8]
312 MS1_SSDNP3[7:0]
313 MS1_SSDNP3[14:8]
314 MS1_SSDNP1[7:0]
315 MS1_SSDNP1[11:8]
319 MS2_SSUPP2[7:0]
320 MS2_SSUPP2[14:8]
321 MS2_SSUPP3[7:0]
322 MS2_SSUPP3[14:8]
323 MS2_SSUPP1[7:0]
324 MS2_SSUDP1[3:0] MS2_SSUPP1[11:8]
325 MS2_SSUDP1[11:4]
326 MS2_SSDNP2[7:0]
327 MS2_SSDNP2[14:8]
328 MS2_SSDNP3[7:0]
329 MS2_SSDNP3[14:8]
330 MS2_SSDNP1[7:0]
331 MS2_SSDNP1[11:8]
335 MS3_SSUPP2[7:0]
336 MS3_SSUPP2[14:8]
337 MS3_SSUPP3[7:0]
338 MS3_SSUPP3[14:8]
339 MS3_SSUPP1[7:0]
340 MS3_SSUDP1[3:0] MS3_SSUPP1[11:8]
341 MS3_SSUDP1[11:4]
342 MS3_SSDNP2[7:0]
343 MS3_SSDNP2[14:8]
344 MS3_SSDNP3[7:0]
345 MS3_SSDNP3[14:8]
346 MS3_SSDNP1[7:0]
347 MS3_SSDNP1[11:8]
52 Rev. 0.6
Si5338
6.4. Register Descriptions
In many registers, the byte reset value contains one or more “x”s because a factory-programmed device can have
multiple values for these bits.
Register 0.
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name REVID[2:0]
Type R
Reset value = xxxx xxxx
Bit Name Function

7:3 Reserved Reserved.
2:0 REVID[2:0] Device Revision ID.
Rev. 0.6 53
Si5338
Register 6.
Name PLL_LOL_MASK LOS_FDBK_MASK LOS_CLKIN_MASK Reserved SYS_CAL_MASK
Type R/W R/W R/W R/W
Bit Name Function

7:5 Reserved Reserved. Must only write 000b to these bits.
Mask Bit for PLL_LOL.
When true, the PLL_LOL bit (Register 218) will not cause an interrupt. See also
4 PLL_LOL_MASK Register 247.
0: PLL Loss of Lock (LOL) triggers active interrupt on INTR output pin.
1: PLL Loss of Lock (LOL) ignored in generating interrupt output.
Mask Bit for Loss of Signal on IN4 or IN5,6.
When true, the LOS_FDBK bit (Register 218) will not cause an interrupt. See
3 LOS_FDBK_MASK also Register 247.
0: FDBK LOS triggers active interrupt on INTR output pin.
1: FDBK LOS ignored in generating interrupt output.
Mask Bit for Loss of Signal on IN1,2 or IN3.
When true, the LOS_CLKIN bit (Register 218) will not cause an interrupt.
2 LOS_CLKIN_MASK See also Register 247.
0: CLKIN LOS triggers active interrupt on INTR output pin.
1: CLKIN LOS ignored in generating interrupt output.
1 Reserved Reserved. Must only write 0 to this bit.
Chip Calibration Mask Bit.
When true, the SYS_CAL bit (Register 218) will not cause an interrupt. See also
0 SYS_CAL_MASK Register 247.
0:PLL self-calibration triggers active interrupt on INTR output pin.
1:PLL self-calibration ignored in generating interrupt output.
54 Rev. 0.6
Si5338
Register 27.
Name I2C_1P8_SEL I2C_ADDR[6:0]
Type R/W R/W*
Bit Name Function
I2C Reference VDD.

7 I2C_1P8_SEL External I2C VDD 0 = 3.3 V/2.5 V, 1 = 1.8 V.
0: 3.3 V/2.5 V (default)
1: 1.8 V
7-Bit I2C Address.

If and only if there is an I2C_LSB pin, the actual I2C LSB address is the logical “or” of
the bit in position 0 with the state of the I2C_LSB pin. Otherwise, the actual I2C_LSB
6:0* I2C_ADDR[6:0] is the LSB of this 7-bit address. Custom 7-bit I2C addresses may be requested but
2
must be even numbers if pin control of the I C address is to be implemented. For
example, if the I2C address = 70h, the I2C_LSB pin can change the LSB from 0 to 1.
However, if the I2C address = 71h, the I2C_LSB pin will have no effect upon the I2C
address.
*Note: Although these bits are R/W, writing them is not supported. Custom I2C addresses can be set at the factory. Contact
your local sales office for details.
Rev. 0.6 55
Si5338
Register 28.
Name P2DIV_IN[0] P1DIV_IN[2:0] XTAL_FREQ[1:0]
Bit Name Function

7:6 Reserved Reserved. Must only write a 00 to these bits.
This bit and Register 30[4:3] create a 3-bit field that selects the input to the P2
divider [reg30[4:3] reg28[5]] = P2DIV_IN[2:0].
000b: Clock from IN5,IN6 is input to P2 divider
5 P2DIV_IN[0]
011b: Clock from IN4 is input to P2
100b: No clock is input to P2
All other bit values are reserved.
These three bits are combined with Register 29[4:3] and create a 5-bit field that
selects the input to the P1 divider [reg29[4:3] reg28[4:2]] = P1DIV_IN[4:0].
00000b: Clock from IN1,IN2 selected
4:2 P1DIV_IN[2:0]
01010b: Clock from IN3 selected
10101b: Crystal oscillator selected
All other bit values are reserved and should not be written.
Crystal Frequency Range.
Select Xtal Frequency that you are using. For more information on using crystals,
see “AN360: Crystal Selection Guide for Si533x/5x Devices”.
1:0 XTAL_FREQ[1:0] 0: 8–11 MHz
1: 11–19 MHz
2: 19–26 MHz
3: 26–30 MHz
56 Rev. 0.6
Si5338
Register 29.
Name PFD_IN_REF[2:0] P1DIV_IN[4:3] P1DIV[2:0]
Type R/W R/W R/W
Bit Name Function

Selects the input clock to be provided to the reference input of PLL Phase
Frequency Detector (PFD).
0: P1DIV_IN selected
1: P2DIV_IN selected
2: P1DIV_OUT (P1 divider output) selected
7:5 PFD_IN_REF[2:0]
4: XOCLK selected
5: No Clock selected
6: Reserved
7: Reserved
These two bits along with reg28[4:2] create a 5-bit field that selects the input to
the P1 divider [reg29[4:3] reg28[4:2]] = P1DIV_IN[4:0].
00000b: Clock from IN,2 selected
4:3 P1DIV_IN[4:3]
01010b: Clock from IN3 selected
10101b: Crystal oscillator selected
All other bit values are reserved
Sets the value of the P1 divider.
0: Divide by 1
1: Divide by 2
2:0 P1DIV[2:0] 2: Divide by 4
3: Divide by 8
4: Divide by 16
5: Divide by 32
Rev. 0.6 57
Si5338
Register 30.
Name PFD_IN_FB[2:0] P2DIV_IN[2:1] P2DIV[2:0]
Type R/W R/W R/W
Bit Name Function

Selects the external input applied to the PFD feedback input. See also Register
48[7].
0: P2DIV_IN (fbclk)
1: P1DIV_IN (refclk)
7:5 PFD_IN_FB[2:0]
4: Reserved
6: Reserved
7: Reserved
These two bits and Register 28[5] create a 3-Bit field that selects the input to the
P2 divider [reg30[4:3] reg28[5]] = P2DIV_IN[2:0].
000b: Clock from IN5,IN6 is input to P2 divider
4:3 P2DIV_IN[2:1]
011b: Clock from IN4 is input to P2
100b: No clock is input to P2
All other bit values are reserved.
Sets the value of the P2 the divider.
0: Divide by 1
1: Divide by 2
2:0 P2DIV[2:0] 2: Divide by 4
3: Divide by 8
4: Divide by 16
5: Divide by 32
58 Rev. 0.6
Si5338
Register 31.
Name R0DIV_IN[2:0] R0DIV[2:0] MS0_PDN DRV0_PDN
Bit Name Function

Selects the input to the R0 divider. R0 divider output goes to CLK0.
0: P2DIV_IN (fbclk) selected
1: P1DIV_IN (refclk) selected
7:5 R0DIV_IN[2:0] 3: P1DIV_OUT (P1 divider output) selected
4: XOCLK selected
5: MultiSynth0 output selected
CLK0 R0 Output Divider.
0: Divide by 1
1: Divide by 2
4:2 R0DIV[2:0] 2: Divide by 4
3: Divide by 8
4: Divide by 16
5: Divide by 32
MultiSynth0 Power Down.
1 MS0_PDN 0: MS0 MultiSynth powered up
1: MS0 MultiSynth powered down
R0 and CLK0 Power Down.
0 DRV0_PDN 0: R0 output divider and CLK0 driver powered up
1: R0 output divider and CLK0 driver powered down
Rev. 0.6 59
Si5338
Register 32.
Bit Name Function

4: XOCLK selected
0: Divide by 1
1: Divide by 2
3: Divide by 8
4: Divide by 16
5: Divide by 32
1 MS1_PDN 0: MultiSynth1 is powered up
1: MultiSynth1 is powered down
60 Rev. 0.6
Si5338
Register 33.
Bit Name Function

4: XOCLK selected
0: Divide by 1
1: Divide by 2
3: Divide by 8
4: Divide by 16
5: Divide by 32
1 MS2_PDN 0: MultiSynth2 powered up
1: MultiSynth2 powered down
Rev. 0.6 61
Si5338
Register 34.
Bit Name Function

4: XOCLK selected
0: Divide by 1
1: Divide by 2
3: Divide by 8
4: Divide by 16
5: Divide by 32
1 MS3_PDN 0: MultiSynth3 is power up
1: MultiSynth3 powered down
R3 and CLK3 Powerdown.
62 Rev. 0.6
Si5338
Register 35.
Name DRV3_VDDO[1:0] DRV2_VDDO[1:0] DRV1_VDDO[1:0] DRV0_VDDO[1:0]
Bit Name Function

VDDO Setting for CLK3.
0: VDDO3 = 3.3 V (not for HSTL)
7:6 DRV3_VDDO[1:0] 1: VDDO3 = 2.5 V (not for HSTL)
2: VDDO3 = 1.8 V (not for HSTL or LVPECL)
3: VDDO3 = 1.5 V (HSTL only)
Note: If the VDDOx voltage is below the minimum allowed voltage of the programmed voltage setting in Register 35, the
output driver may not turn on.
Rev. 0.6 63
Si5338
Register 36.
Name DRV0_INV[1:0] DRV0_FMT[2:0]
Type R/W R/W
Bit Name Function

Invert Driver for CLK0 for CMOS/SSTL/HSTL Outputs.
0: Both outputs are in phase
4:3 DRV0_INV[1:0] 1: CLK0A inverted
2: CLK0B inverted
3: CLK0A/B inverted and in phase
CLK0 Signal Format.
0: Reserved
1: CLK0A = (CMOS/SSTL/HSTL), CLK0B = off
2: CLK0B = (CMOS/SSTL/HSTL), CLK0A = off
2:0 DRV0_FMT[2:0] 3: CLK0A,B = (CMOS/SSTL/HSTL)
4: LVPECL
5: Reserved
6: LVDS
7: HCSL
64 Rev. 0.6
Si5338
Register 37.
Type R/W R/W
Bit Name Function

4:3 DRV1_INV[1:0] 1: CLK1A invert
2: CLK1B invert
3: CLK1A/B invert and in phase
CLK1 Signal Format.
0: Reserved
4: LVPECL
5: Reserved
6: LVDS
7: HCSL
Rev. 0.6 65
Si5338
Register 38.
Type R/W R/W
Bit Name Function

2: CLK2B inverted
CLK2 Signal Format.
0: Reserved
4: LVPECL
5: Reserved
6: LVDS
7: HCSL
66 Rev. 0.6
Si5338
Register 39.
Type R/W R/W
Bit Name Function

2: CLK3B inverted
CLK3 Signal Format.
0: Reserved
4: LVPECL
5: Reserved
6: LVDS
7: HCSL
Register 40.
Name DRV1_TRIM [2:0] DRV0_TRIM [4:0]
Type R/W R/W
Bit Name Function

Trim Bits for CLK1 Driver.
7:5 DRV1_TRIM [2:0] Clockbuilder Desktop sets these values automatically. See AN411 for required
manual settings information
manual settings information
Rev. 0.6 67
Si5338
Register 41.
Name DRV2_TRIM [4:0] DRV1_TRIM [4:3]
Type R/W R/W
Bit Name Function

7 Reserved Reserved.
manual settings information.
settings information.
Register 42.
Name DRV3_TRIM [4:0]
Type R/W
Bit Name Function

5 Reserved Must write 1b to this bit.
Trim Bits for CLK3.
manual settings information.
68 Rev. 0.6
Si5338
Register 45.
Name FCAL_OVRD[7:0]
Type R/W
Bit Name Function

7:0 FCAL_OVRD[7:0] Bits 7:0 of the Override Frequency Calibration for the VCO.
Register 46.
Name FCAL_OVRD[15:8]
Type R/W
Bit Name Function

7:0 FCAL_OVRD[15:8] Bits 15:8 of the Override Frequency Calibration for the VCO
Register 47.
Name Reserved FCAL_OVRD[17:16]
Type R R/W
Bit Name Function

Reserved.
7:2 Reserved
Must write 000101b to these bits if the device is not factory programmed.
1:0 FCAL_OVRD[17:16] Bits 17:16 of the Override Frequency Calibration for the VCO.
Rev. 0.6 69
Si5338
Register 48.
Name PFD_EXTFB PLL_KPHI[6:0]
Type R/W R/W
Bit Name Function

Selects PFD feedback input from internal (see Register 30[7:5]) or external source.
7 PFD_EXTFB 0: Internal feedback path
1: External feedback path (zero delay mode)
6:0 PLL_KPHI[6:0] Sets the charge pump current for the PFD. Clockbuilder Desktop sets these values
automatically. See AN411 for manual setting.
Register 49.
Name FCAL_OVRD_EN VCO_GAIN[2:0] RSEL[1:0] BWSEL[1:0]
Bit Name Function

FCAL Override Enable.
7 FCAL_OVRD_EN 0: Do not use FCAL value in registers 45,46,47
1: Use FCAL value in registers 45,46,47
Sets the VCO Gain.
6:4 VCO_GAIN[2:0] Clockbuilder Desktop sets these values automatically. See AN411 for manual set-
ting.
Loop Filter Resistor Select.
3:2 RSEL[1:0] Clockbuilder Desktop sets these values automatically. See AN411 for manual set-
ting.
Select the PLL Loopfilter.
1:0 BWSEL[1:0] Clockbuilder Desktop sets these values automatically. See AN411 for manual set-
ting.
70 Rev. 0.6
Si5338
Register 50.
Name PLL_ENABLE[1:0] MSCAL[5:0]
Type R/W
Bit Name Function

00: Disable PLL
11: Enable PLL
7:6 PLL_ENABLE[1:0]
It is expected that all Si5338 applications will need to have the PLL enabled; how-
ever, the PLL may be disabled when the Si5338 is set up in buffer mode.
MultiSynth Calibration Value for Optimum Performance.
5:0 MSCAL[5:0] Clockbuilder Desktop sets these values automatically. See AN411 for manual set-
ting.
Rev. 0.6 71
Si5338
Register 51.
Name MS3_HS MS2_HS MS1_HS MS0_HS MS_PEC[2:0]
Reset value = xxxx x111
Bit Name Function

MultiSynth3 High Speed Mode.
When this bit is asserted, MultiSynth3 will only accept divide ratios of 4.0 or 6.0. Incre-
7 MS3_HS ment/decrement, SSC, and all phase functions are not available when this bit is set.
0: MultiSynth3 implements fractional divide ratios between 8 and 1023
1: MultiSynth3 can only implement 4.0 or 6.0 divide ratio.
0: MultiSynth2 implements fractional divide ratios between 8 and 1023.
3 Unused Unused.
MultiSynth Phase Error Correction.
2:0 MS_PEC[2:0]
All non-factory programmed devices must have 111b written to these bits.
72 Rev. 0.6
Si5338
Register 52.
Name MS0_FIDCT[1:0] MS0_FIDDIS MS0_SSMODE[1:0] MS0_PHIDCT[1:0]
Bit Name Function

MultiSynth0 Frequency Increment/Decrement Control.
Bit 4 (disable) must be 0 before writing an increment or decrement
to these bits. Only MS0 can have pin control of Frequency Incre-
ment/Decrement.
6:5 MS0_FIDCT[1:0]
0: No frequency inc/dec on MS0
1: Enable pin control of frequency inc/dec
2: Frequency increment on MS0, self-clearing
3: Frequency decrement on MS0, self-clearing
MultiSynth0 Frequency Increment/Decrement Disable (see also
Register 242[1]).
4 MS0_FIDDIS
0: Frequency inc/dec enabled on MS0
1: Frequency inc/dec disabled on MS0
MultiSynth0 Spread Spectrum Mode Select.
0: No SSC on MS0
3:2 MS0_SSMODE[1:0] 1: Center spread on MS0
2: Reserved
3: Down spread MS0
MultiSynth0 Phase Increment/Decrement Control.
0: No phase inc/dec on MS0
1:0 MS0_PHIDCT[1:0] 1: Enable pin control of phase inc/dec
2: Phase increment on MS0, self clearing
3: Phase decrement on MS0, self clearing
Rev. 0.6 73
Si5338
Register 53.
Name MS0_P1[7:0]
Type R/W
Bit Name Function

MultiSynth0 Parameter 1.
7:0 MS0_P1[7:0] This 18-bit number is an encoded representation of the integer part of the
MultiSynth0 divider.
Register 54.
Name MS0_P1[15:8]
Type R/W
Bit Name Function

74 Rev. 0.6
Si5338
Register 55.
Name MS0_P2[5:0] MS0_P1[17:16]
Type R/W R/W
Bit Name Function

7:2 MS0_P2[5:0] This 30-bit number is an encoded representation of the numerator for the frac-
tional part of the MultiSynth0 Divider.
Register 56.
Name MS0_P2[13:6]
Type R/W
Bit Name Function

Rev. 0.6 75
Si5338
Register 57.
Name MS0_P2[21:14]
Type R/W
Bit Name Function

Register 58.
Name MS0_P2[29:22]
Type R/W
Bit Name Function

7:0 MS0_P2[29:22] This 30-bit number is an encoded representation of the numerator for the
fractional part of the MultiSynth0 Divider.
76 Rev. 0.6
Si5338
Register 59.
Name MS0_P3[7:0]
Type R/W
Bit Name Function

7:0 MS0_P3[7:0] This 30-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth0 divider.
Register 60.
Name MS0_P3[15:8]
Type R/W
Bit Name Function

Register 61.
Name MS0_P3[23:16]
Type R/W
Bit Name Function

Rev. 0.6 77
Si5338
Register 62.
Name MS0_P3[29:24]
Type R/W
Bit Name Function

78 Rev. 0.6
Si5338
Register 63.
Bit Name Function

to these bits.
6:5 MS1_FIDCT[1:0] 0: No frequency inc/dec on MS1
1: Reserved
MultiSynth1 Frequency Increment/Decrement Disable.
See also Register 242[1].
4 MS1_FIDDIS
0: No SSC on MS1
2: Reserved
3: Downspread MS1
Writing a 10 or 11 will self clear back to 0.
1:0 MS1_PHIDCT[1:0]
1: Enable pin control of phase inc/dec
Rev. 0.6 79
Si5338
Register 64.
Name MS1_P1[7:0]
Type R/W
Bit Name Function

Register 65.
Name MS1_P1[15:8]
Type R/W
Bit Name Function

80 Rev. 0.6
Si5338
Register 66.
Name MS1_P2[5:0] MS1_P1[17:16]
Type R/W R/W
Bit Name Function

Register 67.
Name MS1_P2[13:6]
Type R/W
Bit Name Function

7:0 MS1_P2[13:6] This 30-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth1 Divider.
Rev. 0.6 81
Si5338
Register 68.
Name MS1_P2[21:14]
Type R/W
Bit Name Function

Register 69.
Name MS1_P2[29:22]
Type R/W
Bit Name Function

Register 70.
Name MS1_P3[7:0]
Type R/W
Bit Name Function

7:0 MS1_P3[7:0] This 30-bit number is an encoded representation of the denominator for the fractional
82 Rev. 0.6
Si5338
Register 71.
Name MS1_P3[15:8]
Type R/W
Bit Name Function

Register 72.
Name MS1_P3[23:16]
Type R/W
Bit Name Function

Register 73.
Name MS1_P3[29:24]
Type R/W
Bit Name Function

7:6 Reserved Reserved
Rev. 0.6 83
Si5338
Register 74.
Bit Name Function

to these bits.
1: Reserved
Register 242[1]).
4 MS2_FIDDIS
0: No SSC on MS2
2: Reserved
3: Down spread MS2
84 Rev. 0.6
Si5338
Register 75.
Name MS2_P1[7:0]
Type R/W
Bit Name Function

Register 76.
Name MS2_P1[15:8]
Type R/W
Bit Name Function

Rev. 0.6 85
Si5338
Register 77.
Name MS2_P2[5:0] MS2_P1[17:16]
Type R/W R/W
Bit Name Function

Register 78.
Name MS2_P2[13:6]
Type R/W
Bit Name Function

7:0 MS2_P2[13:6] This 30-bit number is an encoded representation of the numerator for the fractional
86 Rev. 0.6
Si5338
Register 79.
Name MS2_P2[21:14]
Type R/W
Bit Name Function

Register 80.
Name MS2_P2[29:22]
Type R/W
Bit Name Function

Rev. 0.6 87
Si5338
Register 81.
Name MS2_P3[7:0]
Type R/W
Bit Name Function

MS2_P3[7:0] This 30-bit number is an encoded representation of the denominator for the fractional
Register 82.
Name MS2_P3[15:8]
Type R/W
Bit Name Function

88 Rev. 0.6
Si5338
Register 83.
Name MS2_P3[23:16]
Type R/W
Bit Name Function

Register 84.
Name MS2_P3[29:24]
Type R/W
Bit Name Function

MS2_P3[29:24] This 30-bit number is an encoded representation of the denominator for the frac-
Rev. 0.6 89
Si5338
Register 85.
Bit Name Function

Bit 4 (disable) must be 3 before writing an increment or decrement to these
bits.
1: Reserved
Register 242[1]).
4 MS3_FIDDIS
0: No SSC on MS3
2: Reserved
3: Down spread MS3
2: Phase increment on MS3
3: Phase decrement on MS3
90 Rev. 0.6
Si5338
Register 86.
Name MS3_P1[7:0]
Type R/W
Bit Name Function

Register 87.
Name MS3_P1[15:8]
Type R/W
Bit Name Function

MultiSynth3 divider
Rev. 0.6 91
Si5338
Register 88.
Name MS3_P2[5:0] MS3_P1[17:16]
Type R/W R/W
Bit Name Function

7:2 MS3_P2[5:0] This 30-bit number is an encoded representation of the denominator for the
fractional part of the MultiSynth3 Divider.
Register 89.
Name MS3_P2[13:6]
Type R/W
Bit Name Function

92 Rev. 0.6
Si5338
Register 90.
Name MS3_P2[21:14]
Type R/W
Bit Name Function

Register 91.
Name MS3_P2[29:22]
Type R/W
Bit Name Function

Register 92.
Name MS3_P3[7:0]
Type R/W
Bit Name Function

7:0 MS3_P3[7:0] This 30-bit number is an encoded representation of the denominator for the fractional
Rev. 0.6 93
Si5338
Register 93.
Name MS3_P3[15:8]
Type R/W
Bit Name Function

tional part of the MultiSynth3 Divider
Register 94.
Name MS3_P3[23:16]
Type R/W
Bit Name Function

tional part of the MultiSynth3 Divider
Register 95.
Name MS3_P3[29:24]
Type R/W
Bit Name Function

94 Rev. 0.6
Si5338
Register 97.
Name MSN_P1[7:0]
Type R/W
Bit Name Function

Feedback MultiSynthN Parameter 1.
7:0 MSN_P1[7:0] This 18-bit number is an encoded representation of the integer part of the MultiSynth
Feedback divider.
Register 98.
Name MSN_P1[15:8]
Type R/W
Bit Name Function

7:0 MSN_P1[15:8] This 18-bit number is an encoded representation of the integer part of the MultiSynth
Feedback divider.
Rev. 0.6 95
Si5338
Register 99.
Name MSN_P2[5:0] MSN_P1[17:16]
Type R/W R/W
Bit Name Function

7:2 MSN_P2[5:0] This 18-bit number is an encoded representation of the numerator for the frac-
tional part of the MultiSynth Feedback divider.
1:0 MSN_P1[17:16] This 18-bit number is an encoded representation of the integer part of the Multi-
Synth Feedback divider.
Register 100.
Name MSN_P2[13:6]
Type R/W
Bit Name Function

7:0 MSN_P2[13:6] This 18-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth Feedback divider.
96 Rev. 0.6
Si5338
Register 101.
Name MSN_P2[21:14]
Type R/W
Bit Name Function

7:0 MSN_P2[21:14] This 18-bit number is an encoded representation of the numerator for the fractional
Register 102.
Name MSN_P2[29:22]
Type R/W
Bit Name Function

7:0 MSN_P2[29:22] This 18-bit number is an encoded representation of the numerator for the frac-
Register 103.
Name MSN_P3[7:0]
Type R/W
Bit Name Function

7:0 MSN_P3[7:0] This 18-bit number is an encoded representation of the denominator for the fractional
Rev. 0.6 97
Si5338
Register 104.
Name MSN_P3[15:8]
Type R/W
Bit Name Function

7:0 MSN_P3[15:8] This 18-bit number is an encoded representation of the denominator for the fractional
part of the MultiSynth Feedback divider
Register 105.
Name MSN_P3[23:16]
Type R/W
Bit Name Function

7:0 MSN_P3[23:16] This 18-bit number is an encoded representation of the denominator for the frac-
98 Rev. 0.6
Si5338
Register 106.
Name NOTERM_FB MSN_P3[29:24]
Type R/W R/W
Bit Name Function

Reserved.
7 Reserved
Must write 1b to this bit.
5:0 MSN_P3[29:24] This 18-bit number is an encoded representation of the denominator for the frac-
Register 107.
Name MS0_PHOFF[7:0]
Type R/W
Bit Name Function

MultiSynth0 Initial Phase Offset.
MultiSynth0_PHOFF[14:0] is a 2s complement number. The initial phase
7:0 MS0_PHOFF[7:0]
offset is MultiSynth0_PHOFF[14:0]*Tvco/128 where Tvco is the period of
the VCO.
Rev. 0.6 99
Si5338
Register 108.
Name MS0_PHOFF[14:8]
Type R/W
Bit Name Function

6:0 MS0_PHOFF[14:8] MultiSynth0_PHOFF[14:0] is a 2s complement number. The initial
phase offset is MultiSynth0_PHOFF[14:0]*Tvco/128 where Tvco is the
period of the VCO.
Register 109.
Name MS0_PHSTEP[7:0]
Type R/W
Bit Name Function

MultiSynth0 Phase Step Size.
The phase step size is MultiSynth0_PHSTEP[13:0]*Tvco/128 where
7:0 MS0_PHSTEP[7:0] Tvco is the period of the VCO. Either the phase inc/dec pins (if avail-
able) or register 52[1:0] will control the stepping of phase. A phase
increment will delay the clock edge.
100 Rev. 0.6

Si5338
Register 110.
Name CLK0_DISST[1:0] MS0_PHSTEP[13:8]
Type R/W R/W
Bit Name Function

CLK0 Output Driver State When Disabled.
00: High impedance
7:6 CLK0_DISST[1:0 01: Logic low
10: Logic high
11: Always on even if disabled
MS0 Phase Step Size.
The phase step size is MS0_PHSTEP[13:0]*Tvco/128 where Tvco is
5:0 MS0_PHSTEP[13:8] the period of the VCO. Either the phase inc/dec pins (if available) or
register 52[1:0] will control the stepping of phase. A phase increment
will delay the clock edge.
Register 111.
Name MS1_PHOFF[7:0]
Type R/W
Bit Name Function

7:0 MS1_PHOFF[7:0] MultiSynth1_PHOFF[14:0] is a 2s complement number. The initial phase
offset is MultiSynth1_PHOFF[14:0]*Tvco/128 where Tvco is the period of
the VCO.
Rev. 0.6 101

Si5338
Register 112.
Type R/W
Bit Name Function

7 Reserved Reserved
phase offset is MultiSynth1_PHOFF[14:0] x Tvco/128 where Tvco is the
period of the VCO.
Register 113.
Type R/W
Bit Name Function

The phase step size is MultiSynth1_PHSTEP[13:0] x Tvco/128 where
102 Rev. 0.6

Si5338
Register 114.
Type R/W R/W
Bit Name Function

MultiSynth1 Output Driver State When Disabled.
00: High impedance
7:6 CLK1_DISST[1:0] 01: Logic low
10: Logic high
Register 115.
Name MS2_PHOFF[7:0]
Type R/W
Bit Name Function

offset is MultiSynth2_PHOFF[14:0] x Tvco/128 where Tvco is the period
of the VCO.
Rev. 0.6 103

Si5338
Register 116.
Type R/W R/W
Bit Name Function

Reserved.
7 Reserved
Must write 1b to this bit.
MultiSynth2_PHOFF[14:0] is a 2s complement number. The initial
6:0 MS2_PHOFF[14:8]
phase offset is MultiSynth2_PHOFF[14:0] x Tvco/128 where Tvco is
the period of the VCO.
Register 117.
Type R/W
Bit Name Function

104 Rev. 0.6

Si5338
Register 118.
Type R/W R/W
Bit Name Function

00: High impedance
10: Logic high
Register 119.
Name MS3_PHOFF[7:0]
Type R/W
Bit Name Function

offset is MultiSynth3_PHOFF[14:0] x Tvco/128 where Tvco is the period
of the VCO.
Rev. 0.6 105

Si5338
Register 120.
Type R/W
Bit Name Function

7 Unused Unused.
phase offset is MultiSynth3_PHOFF[14:0] x Tvco/128 where Tvco is the
period of the VCO.
Register 121.
Type R/W
Bit Name Function

106 Rev. 0.6

Si5338
Register 122.
Type R/W R/W
Bit Name Function

00: High impedance
10: Logic high
Register 123.
Name MS0_FIDP1[7:0]
Type R/W
Bit Name Function

7:0 MS0_FIDP1[7:0] MultiSynth0 Frequency Increment/Decrement Parameter 1.
Rev. 0.6 107

Si5338
Register 124.
Name MS0_FIDP1 [15:8]
Type R/W
Bit Name Function

7:0 MS0_FIDP1 [15:8] MultiSynth0 Frequency Increment/Decrement Parameter 1.
Register 125.
Type R/W
Bit Name Function

Register 126.
Type R/W
Bit Name Function

108 Rev. 0.6

Si5338
Register 127.
Type R/W
Bit Name Function

Register 128.
Type R/W
Bit Name Function

Register 129.
Type R/W
Reset value = 001x xxxx
Bit Name Function

Rev. 0.6 109

Si5338
Register 130.
Type R/W
Bit Name Function

Register 131.
Type R/W
Bit Name Function

Register 132.
Type R/W
Bit Name Function

110 Rev. 0.6

Si5338
Register 133.
Type R/W
Bit Name Function

Register 134.
Type R/W
Bit Name Function

Register 135.
Type R/W
Bit Name Function

Rev. 0.6 111

Si5338
Register 136.
Type R/W
Bit Name Function

Register 137.
Type R/W
Bit Name Function

Register 138.
Type R/W
Bit Name Function

112 Rev. 0.6

Si5338
Register 139.
Type R/W
Bit Name Function

Register 140.
Type R/W
Bit Name Function

Register 141.
Type R/W
Bit Name Function

Rev. 0.6 113

Si5338
Register 142.
Type R/W
Bit Name Function

Register 143.
Type R/W
Bit Name Function

Register 144.
Name MS0_ALL MS0_FIDP3[62:56]
Type R/W
Bit Name Function

Use MultiSynth0 for All Outputs.
7 MS0_ALL If set, the MultiSynth0 output is routed to the mux at the input of each R divider.
Unused MultiSynths should be powered down to save power.
114 Rev. 0.6

Si5338
Register 152.
Name MS1_FIDP1[7:0]
Type R/W
Reset value = 0000 0000
Bit Name Function

Register 153.
Name MS1_FIDP1[15:8]
Type R/W
Bit Name Function

Register 154.
Type R/W
Bit Name Function

Rev. 0.6 115

Si5338
Register 155.
Type R/W
Bit Name Function

Register 156.
Type R/W
Bit Name Function

Register 157.
Type R/W
Bit Name Function

116 Rev. 0.6

Si5338
Register 158.
Type R/W
Bit Name Function

Register 159.
Type R/W
Bit Name Function

Register 160.
Type R/W
Bit Name Function

Rev. 0.6 117

Si5338
Register 161.
Type R/W
Bit Name Function

Register 162.
Type R/W
Bit Name Function

Register 163.
Type R/W
Bit Name Function

118 Rev. 0.6

Si5338
Register 164.
Type R/W
Bit Name Function

Register 165.
Name MS1_FIDP2[7:0]
Type R/W
Bit Name Function

Register 166.
Name MS1_FIDP3[7:0]
Type R/W
Bit Name Function

Rev. 0.6 119

Si5338
Register 167.
Type R/W
Bit Name Function

Register 168.
Type R/W
Bit Name Function

Register 169.
Type R/W
Bit Name Function

120 Rev. 0.6

Si5338
Register 170.
Type R/W
Bit Name Function

Register 171.
Type R/W
Bit Name Function

Register 172.
Type R/W
Bit Name Function

Rev. 0.6 121

Si5338
Register 173.
Type R/W
Bit Name Function

7 Unused Unused.
Register 174.
Name MS2_FIDP1[7:0]
Type R/W
Bit Name Function

Register 175.
Type R/W
Bit Name Function

122 Rev. 0.6

Si5338
Register 176.
Type R/W
Bit Name Function

Register 177.
Type R/W
Bit Name Function

Register 178.
Type R/W
Bit Name Function

Rev. 0.6 123

Si5338
Register 179.
Type R/W
Bit Name Function

Register 180.
Type R/W
Bit Name Function

7:4 Unused Unused.
Register 181.
Type R/W
Bit Name Function

124 Rev. 0.6

Si5338
Register 182.
Type R/W
Bit Name Function

Register 183.
Type R/W
Bit Name Function

Register 184.
Type R/W
Bit Name Function

Rev. 0.6 125

Si5338
Register 185.
Type R/W
Bit Name Function

Register 186.
Type R/W
Bit Name Function

Register 187.
Name MS2_FIDP2[7:0]
Type R/W
Bit Name Function

126 Rev. 0.6

Si5338
Register 188.
Name MS2_FIDP3[7:0]
Type R/W
Bit Name Function

Register 189.
Type R/W
Bit Name Function

Register 190.
Type R/W
Bit Name Function

Rev. 0.6 127

Si5338
Register 191.
Type R/W
Bit Name Function

Register 192.
Type R/W
Bit Name Function

Register 193.
Type R/W
Bit Name Function

128 Rev. 0.6

Si5338
Register 194.
Type R/W
Bit Name Function

Register 195.
Type R/W
Bit Name Function

7 Unused Unused.
Register 196.
Name MS3_FIDP1[7:0]
Type R/W
Bit Name Function

Rev. 0.6 129

Si5338
Register 197.
Type R/W
Bit Name Function

Register 198.
Type R/W
Bit Name Function

Register 199.
Type R/W
Bit Name Function

130 Rev. 0.6

Si5338
Register 200.
Type R/W
Bit Name Function

Register 201.
Type R/W
Bit Name Function

Register 202.
Type R/W
Bit Name Function

7:4 Unused Unused.
Rev. 0.6 131

Si5338
Register 203.
Type R/W
Bit Name Function

Register 204.
Type R/W
Bit Name Function

Register 205.
Type R/W
Bit Name Function

132 Rev. 0.6

Si5338
Register 206.
Type R/W
Bit Name Function

Register 207.
Type R/W
Bit Name Function

Register 208.
Type R/W
Bit Name Function

Rev. 0.6 133

Si5338
Register 209.
Name MS3_FIDP2[7:0]
Type R/W
Bit Name Function

Register 210.
Name MS3_FIDP3[7:0]
Type R/W
Bit Name Function

Register 211.
Type R/W
Bit Name Function

134 Rev. 0.6

Si5338
Register 212.
Type R/W
Bit Name Function

Register 213.
Type R/W
Bit Name Function

Register 214.
Type R/W
Bit Name Function

Rev. 0.6 135

Si5338
Register 215.
Type R/W
Bit Name Function

Register 216.
Type R/W
Bit Name Function

Register 217.
Type R/W
Bit Name Function

7 Unused Unused
136 Rev. 0.6

Si5338
Register 218.
Name PLL_LOL LOS_FDBK LOS_CLKIN SYS_CAL
Type R R R R
Bit Name Function

PLL Loss of Lock (LOL).
Asserts when the two PFD inputs have a frequency difference > 1000 ppm.
4 PLL_LOL This bit is held high during a POR_reset until the PLL has locked. This bit will not
chatter while the PLL is locking. PLL_LOL does not assert when the input from
IN1,IN2 or IN3 is lost. When PLL_LOL asserts, the part will automatically try to
re-acquire to the input clock. See Register 241[7].
3 LOS_FDBK Loss of Signal on Feedback Clock from IN5,6 or IN4.
2 LOS_CLKIN Loss of Signal on Input Clock from IN1,2 or IN3.
1 Reserved Reserved
0 SYS_CAL Device Calibration in Process.
Rev. 0.6 137

Si5338
Register 230.
Name OEB_ALL OEB_3 OEB_2 OEB_1 OEB_0
Type R/W R/W R/W R/W R/W
Bit Name Function

7:5 Unused Unused.
Disable All Clock Outputs.
4 OEB_ALL 0: All output clocks are disabled
1: Output clocks are not disabled
CLK3 Disable.
3 OEB_3 0: CLK1 output is disabled
1: CLK1 output is not disabled
CLK2 Disable.
CLK1 Disable.
CLK0 Disable.
Register 235.
Name FCAL[7:0]
Type R
Bit Name Function

7:0 FCAL[7:0] Bits 7:0 of the Frequency Calibration for the VCO.
138 Rev. 0.6

Si5338
Register 236.
Name FCAL[15:8]
Type R
Bit Name Function

Register 237.
Name Reserved FCAL[17:16]
Type R R
Bit Name Function

Register 241.
Name DIS_LOL Reserved. Write to 0x65.
Type R/W
Bit Name Function

When asserted, the PLL_LOL status in register 218 is prevented from
7 DIS_LOL
asserting.
6:0 Reserved On a non-factory-programmed device this register must be set to 0x65.

On a factory programmed device, this register must stay 0x65.
Rev. 0.6 139

Si5338
Register 242.
Name DCLK_DIS
Type R/W
Bit Name Function

Disable Clock to INC/DEC State Machine.
1 DCLK_DIS When true, the frequency inc/dec logic is disabled, which saves about 2 mA of current.
See also Registers 52[4], 63[4], 74[4], 85[4].
Register 246.
Name SOFT_RESET
Type R/W R/W
Bit Name Function

Soft Reset.
This reset will disable all clock outputs, then re-acquire the PLL to the input clock and
the enable all the clock outputs. Retains device configuration stored in RAM. Do not
1 SOFT_RESET
use read-modify-write procedure to perform soft reset. Instead, write reg246=0x02,
regardless of the current value of this bit. Reading this bit after a soft reset will return a
1.
140 Rev. 0.6

Si5338
Register 247.
Name PLL_LOL_STK LOS_FDBK_STK LOS_CLKIN_STK SYS_CAL_STK
Bit Name Function

PLL Loss of Lock Sticky Bit.
4 PLL_LOL_STK Sticky version of PLL_LOL. See also Registers 6 and 218. Only a soft or POR
reset or writing a “0” to this bit will clear it.
Feedback Clock Loss of Signal Sticky Bit.
3 LOS_FDBK_STK Sticky version of LOS_FDBK. See also Registers 6 and 218. Only a soft or
POR reset or writing a “0” to this bit will clear it.
Input Clock Loss of Signal Sticky Bit.
2 LOS_CLKIN_STK Sticky version of LOS_CLKIN_STK. See also Registers 6 and 218. Only a soft
or POR reset or writing a “0” to this bit will clear it.
System Calibration in Process Sticky Bit.
0 SYS_CAL_STK Sticky version of SYS_CAL. See also Registers 6 and 218. Only a soft or POR
reset or writing a “0” to this bit will clear it.
Rev. 0.6 141

Si5338
Register 255.
Name PAGE_SEL
Type R/W
Bit Name Function

7:1 Unused Unused.
0 PAGE_SEL Set to 0 to access registers 0–254, set to 1 to access register 256 to 347.
Register 287.
Name MS0_SSUPP2[7:0]
Type R/W
Bit Name Function

7:0 MS0_SSUPP2[7:0] MultiSynth0 Spread Spectrum Up Parameter 2.
142 Rev. 0.6

Si5338
Register 288.
Type R/W
Bit Name Function

7 Unused Unused.
Register 289.
Type R/W
Bit Name Function

Register 290.
Type R/W
Bit Name Function

7 Unused Unused
Rev. 0.6 143

Si5338
Register 291.
Type R/W
Bit Name Function

Register 292.
Name MS0_SSUDP1[3:0] MS0_SSUPP1[11:8]
Type R/W R/W
Bit Name Function

7:4 MS0_SSUDP1[3:0] MultiSynth0 Spread Spectrum Up/Down Parameter 1.
Register 293.
Name MS0_SSUDP1[11:4]
Type R/W
Bit Name Function

7:0 MS0_SSUDP1[11:4] MultiSynth0 Spread Spectrum Up Parameter 1.
144 Rev. 0.6

Si5338
Register 294.
Name MS0_SSDNP2[7:0]
Type R/W
Bit Name Function

7:0 MS0_SSDNP2[7:0] MultiSynth0 Spread Spectrum Down Parameter 2.
Register 295.
Type R/W
Bit Name Function

7 Unused Unused.
Register 296.
Type R/W
Bit Name Function

Rev. 0.6 145

Si5338
Register 297.
Type R/W
Bit Name Function

7 Unused Unused.
Register 298.
Type R/W
Bit Name Function

Register 299.
Type R/W R/W
Bit Name Function

146 Rev. 0.6

Si5338
Register 303.
Type R/W
Bit Name Function

Register 304.
Type R/W
Bit Name Function

7 Unused Unused.
Register 305.
Type R/W
Bit Name Function

Rev. 0.6 147

Si5338
Register 306.
Type R/W
Bit Name Function

7 Unused Unused.
Register 307.
Type R/W
Bit Name Function

Register 308.
Type R/W R/W
Bit Name Function

148 Rev. 0.6

Si5338
Register 309.
Type R/W
Bit Name Function

Register 310.
Type R/W
Bit Name Function

Register 311.
Type R/W
Bit Name Function

7 Unused Unused.
Rev. 0.6 149

Si5338
Register 312.
Type R/W
Bit Name Function

Register 313.
Type R/W
Bit Name Function

7 Unused Unused.
Register 314.
Type R/W
Bit Name Function

150 Rev. 0.6

Si5338
Register 315.
Type R/W R/W
Bit Name Function

Register 319.
Type R/W
Bit Name Function

Register 320.
Type R/W
Bit Name Function

7 Unused Unused.
Rev. 0.6 151

Si5338
Register 321.
Type R/W
Bit Name Function

Register 322.
Type R/W
Bit Name Function

7 Unused Unused.
Register 323.
Type R/W
Bit Name Function

152 Rev. 0.6

Si5338
Register 324.
Type R/W R/W
Bit Name Function

Register 325.
Type R/W
Bit Name Function

Register 326.
Type R/W
Bit Name Function

Rev. 0.6 153

Si5338
Register 327.
Type R/W
Bit Name Function

7 Unused Unused.
Register 328.
Type R/W
Bit Name Function

Register 329.
Type R/W
Bit Name Function

7 Unused Unused.
154 Rev. 0.6

Si5338
Register 330.
Type R/W
Bit Name Function

Register 331.
Type R/W R/W
Bit Name Function

Register 335.
Type R/W
Bit Name Function

Rev. 0.6 155

Si5338
Register 336.
Type R/W
Bit Name Function

7 Unused Unused.
Register 337.
Type R/W
Bit Name Function

Register 338.
Type R/W
Bit Name Function

7 Unused Unused.
156 Rev. 0.6

Si5338
Register 339.
Type R/W
Bit Name Function

Register 340.
Type R/W R/W
Bit Name Function

Register 341.
Type R/W
Bit Name Function

Rev. 0.6 157

Si5338
Register 342.
Type R/W
Bit Name Function

Register 343.
Type R/W
Bit Name Function

7 Unused Unused.
Register 344.
Type R/W
Bit Name Function

158 Rev. 0.6

Si5338
Register 345.
Type R/W
Bit Name Function

7 Unused Unused.
Register 346.
Type R/W
Bit Name Function

Register 347.
Type R/W R/W
Bit Name Function

Rev. 0.6 159

Si5338
7. Pin Descriptions
Top View
RSVD_GND
VDDO0
CLK0B
CLK0A
VDD
SDA
24 23 22 21 20 19
IN1 1 18 CLK1A
IN2 2 17 CLK1B
IN3 3 16 VDDO1
GND
GND
IN4 4 Pad 15 VDDO2
IN5 5 14 CLK2A
IN6 6 13 CLK2B
7 8 9 10 11 12
SCL
INTR
VDDO3
VDD
CLK3B
Note: Center pad must be tied to GND for normal operation. CLK3A
Table 17. Si5338 Pin Descriptions

Pin # Pin Name I/O Signal Type Description
CLKIN/CLKINB.
These pins are used as the main differential clock input or as the
XTAL input. See "3.2. Input Stage" on page 17, Figure 3 and
Figure 4, for connection details. Clock inputs to these pins must be
1,2 IN1/IN2 I Multi ac-coupled. Keep the traces from pins 1,2 to the crystal as short as
possible and keep other signals and radiating sources away from
the crystal.
When not in use, leave IN1 unconnected and IN2 connected to
GND.
160 Rev. 0.6

Si5338
Table 17. Si5338 Pin Descriptions (Continued)
This pin can have one of the following functions depending on the
part number:
CLKIN (for Si5338A/B/C and Si5338N/P/Q devices only)
Provides a high-impedance clock input for single ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
Stage”, Figure 3.
If this pin is not used, it should be connected to ground.
PINC (for Si5338D/E/F devices only)
Used as the phase increment pin. See "3.9.2. Output Phase
3 IN3 I Multi Increment/Decrement" on page 24 for more details. Minimum
pulse width of 100 ns is required for proper operation. If this pin is
not used, it should be connected to ground.
FINC (for Si5338G/H/J devices only)
Used as the frequency increment pin. See "3.9.1. Frequency
Increment/Decrement" on page 23 for more details. Minimum
pulse width of 100 ns is required for proper operation. If this pin is
not used, it should be connected to ground.
OEB (for Si5338K/L/M devices only)
Used as an output enable pin. 0 = All outputs enabled; 1 = All
outputs disabled. By default, outputs are tri-stated when disabled.
This pin can have one of the following functions depending on the
part number
I2C_LSB (for Si5338A/B/C and Si5338K/L/M devices only)
This is the LSB of the Si5338 I2C address. 0 = I2C address
70h (111 0000), 1 = I2C address 71h (111 0001).
FDBK (for Si5338N/P/Q devices only)
Provides a high-impedance feedback input for single-ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
Stage”, Figure 3. If this pin is not used, it should be connected to
4 IN4 I Multi ground.
PDEC (for Si5338D/E/F) devices only)
Used as the phase decrement pin. See “3.9.2. Output Phase
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
FDEC (for Si5338G/H/J devices only)
Used as the frequency decrement pin. See “3.9.1. Frequency
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
Rev. 0.6 161

Si5338
FDBK/FDBKB.
These pins can be used as a differential feedback input in zero
delay mode or as a secondary clock input. See section 3.2,
Figure 3, for termination details. See "3.9.5. Zero-Delay Mode" on
5,6 IN5/IN6 I Multi
page 24 for zero delay mode set-up. Inputs to these pins must be
ac-coupled.
When not in use, leave IN5 unconnected and IN6 connected to
GND.
Core Supply Voltage.
This is the core supply voltage, which can operate from a 1.8, 2.5,
7 VDD VDD Supply
or 3.3 V supply. A 0.1 µF bypass capacitor should be located very
close to this pin.
Interrupt.
A typical pullup resistor of 1–4 k is used on this pin. This pin can
be pulled up to a supply voltage as high as 3.6 V regardless of the
8 INTR O Open Drain
other supply voltages on pins 7, 11, 15, 16, 20, and 24. The inter-
rupt condition allows the pull up resistor to pull the output up to the
supply voltage.
Output Clock B for Channel 3.
May be a single-ended output or half of a differential output with
9 CLK3B O Multi
CLK3A being the other differential half. If unused, leave this pin
floating.
Output Clock A for Channel 3.
10 CLK3A O Multi
CLK3B being the other differential half. If unused, leave this pin
floating.
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A 0.1 µF
11 VDDO3 VDD Supply
capacitor must be located very close to this pin. If CLK3 is not
used, this pin must be tied to VDD (pin 7, 24).
I2C Serial Clock Input.
This is the serial clock input for the I2C bus. A pullup resistor at this
12 SCL I LVCMOS pin is required. Typical values would be 1–4 k. See the I2C bus
spec for more information. This pin is 3.3 V tolerant regardless of
the other supply voltages on pins 7, 11, 15, 16, 20, 24.
13 CLK2B O Multi
floating.
14 CLK2A O Multi
floating.
162 Rev. 0.6

Si5338
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B.
15 VDDO2 VDD Supply
A 0.1 µF capacitor must be located very close to this pin. If CLK2 is
not used, this pin must be tied to VDD (pin 7, 24).
16 VDDO1 VDD Supply
17 CLK1B O Multi
floating.
18 CLK1A O Multi
floating.
I2C Serial Data.
This is the serial data for the I2C bus. A pullup resistor at this pin is
19 SDA I/O LVCMOS required. Typical values would be 1–4 k. See the I2C bus spec
for more information. This pin is 3.3 V tolerant regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, 24.
20 VDDO0 VDD Supply
21 CLK0B O Multi Output Clock B for Channel 0.
floating.
22 CLK0A O Multi Output Clock A for Channel 0.
floating.
23 GND GND GND Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
24 VDD VDD Supply Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 µF
bypass capacitor should be located very close to this pin.
GND GND GND GND Ground Pad.
PAD This is the large pad in the center of the package. Device
specifications cannot be guaranteed unless the ground pad is
properly connected to a ground plane on the PCB. See Table 20,
“PCB Land Pattern,” on page 167 for ground via requirements.
Rev. 0.6 163

Si5338
8. Device Pinout by Part Number
The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock
frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/
M/Q have a maximum output clock frequency of 200 MHz.
Devices are also orderable according to the pin control functions available on Pins 3 and 4:
 CLKIN—single-ended clock input
 I2C_LSB—determines the LSB bit of the 7-bit I2C address
 FINC—frequency increment pin
 FDEC—frequency decrement pin
 PINC—phase increment pin
 PDEC—phase decrement pin
 FDBK—single-ended feedback input
 OEB—output enable
Table 18. Pin Function by Part Number

Pin # Si5338A: 710 MHz Si5338D: 710 MHz Si5338G: 710 MHz Si5338K: 710 MHz Si5338N: 710 MHz
Si5338B: 350 MHz Si5338E: 350 MHz Si5338H: 350 MHz Si5338L: 350 MHz Si5338P: 350 MHz
Si5338C: 200 MHz Si5338F: 200 MHz Si5338J: 200 MHz Si5338M: 200 MHz Si5338Q: 200 MHz
1 CLKIN1 CLKIN1 CLKIN1 CLKIN1 CLKIN1
2 CLKINB1 CLKINB1 CLKINB1 CLKINB1 CLKINB1
3 CLKIN2 PINC FINC OEB CLKIN2
4 I2C_LSB PDEC FDEC I2C_LSB FDBK3
5 FDBK4 FDBK4 FDBK4 FDBK4 FDBK4
6 FDBKB4 FDBKB4 FDBKB4 FDBKB4 FDBKB4
7 VDD VDD VDD VDD VDD
8 INTR INTR INTR INTR INTR
9 CLK3B CLK3B CLK3B CLK3B CLK3B
10 CLK3A CLK3A CLK3A CLK3A CLK3A
11 VDDO3 VDDO3 VDDO3 VDDO3 VDDO3
12 SCL SCL SCL SCL SCL
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
164 Rev. 0.6

Si5338
Table 18. Pin Function by Part Number (Continued)
Pin # Si5338A: 710 MHz Si5338D: 710 MHz Si5338G: 710 MHz Si5338K: 710 MHz Si5338N: 710 MHz
Si5338B: 350 MHz Si5338E: 350 MHz Si5338H: 350 MHz Si5338L: 350 MHz Si5338P: 350 MHz
Si5338C: 200 MHz Si5338F: 200 MHz Si5338J: 200 MHz Si5338M: 200 MHz Si5338Q: 200 MHz
19 SDA SDA SDA SDA SDA
23 GND GND GND GND GND
24 VDD VDD VDD VDD VDD
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
Rev. 0.6 165

Si5338
9. Package Outline: 24-Lead QFN
Figure 24. 24-Lead Quad Flat No-lead (QFN)
Table 19. Package Dimensions

Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 4.00 BSC.
D2 2.35 2.50 2.65
e 0.50 BSC.
E 4.00 BSC.
E2 2.35 2.50 2.65
L 0.30 0.40 0.50
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
166 Rev. 0.6

Si5338
10. Recommended PCB Layout
Table 20. PCB Land Pattern

Dimension Min Nom Max
P1 2.50 2.55 2.60
P2 2.50 2.55 2.60
X1 0.20 0.25 0.30
Y1 0.75 0.80 0.85
C1 3.90
C2 3.90
E 0.50
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Center pad should be connected to the nearest GND plane.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Rev. 0.6 167

Si5338
11. Ordering Information
Si5338X AXXXXX GMR
Operating Temp Range: -40 to +85 °C

Package: 4 x 4 mm QFN, ROHS6, Pb-free
R = Tape & Reel
(blank) = Tubes
A = Product Revision A
XXXXX = NVM code (optional).
For blank devices, order Si5338X-A-GM(R).
For custom NVM configurations, a unique 5-digit ordering code
will be assigned by the factory. Consult your sales representative
for custom NVM configurations.
Si5338A - 0.16 MHz to 710 MHz I2C_LSB

Si5338B - 0.16 MHz to 350 MHz I2C_LSB
Si5338C - 0.16 MHz to 200 MHz I2C_LSB
Si5338D - 0.16 MHz to 710 MHz Phase Inc/Dec Pin Control
Si5338E - 0.16 MHz to 350 MHz Phase Inc/Dec Pin Control
Si5338F - 0.16 MHz to 200 MHz Phase Inc/Dec Pin Control
Si5338G - 0.16 MHz to 710 MHz Freq Inc/Dec Pin Control
Si5338H - 0.16 MHz to 350 MHz Freq Inc/Dec Pin Control
Si5338J - 0.16 MHz to 200 MHz Freq Inc/Dec Pin Control
Si5338K - 0.16 MHz to 710 MHz OEB Pin Control + I2C_LSB
Si5338L - 0.16 MHz to 350 MHz OEB Pin Control + I2C_LSB
Si5338M - 0.16 MHz to 200 MHz OEB Pin Control + I2C_LSB
Si5338N - 0.16 MHz to 710 MHz Four Inputs (2 Differential, 2 Single-ended)
Si5338P - 0.16 MHz to 350 MHz Four Inputs (2 Differential, 2 Single-ended)
Si5338Q - 0.16 MHz to 200 MHz Four Inputs (2 Differential, 2 Single-ended)
Evaluation Boards
Si5338 EVB Si5338 Evaluation Board
PROG - EVB Si5338 Field Programmer
168 Rev. 0.6

Si5338
DOCUMENT CHANGE LIST Revision 0.5 to 0.55
 Editorial changes to section 3.5 “Configuring the
Revision 0.1 to 0.2 Si5338” to improve clarity on ordering custom
 Updated block diagram to show Rn output divider Si5338 and on configuring "blank" Si5338.
and PLL bypass mode  Added pin numbers to device package drawings.
 Updated pin description to include FDBK±  Updated ordering information to include evaluation
 Updated Table 3. DC Characteristics boards.
 Updated Table 12. Jitter Specifications  Updated first page description and applications
 Added Supply Current vs. Output Frequency  Added JC to specification tables.
 Updated package outline specification  Added GbE RM jitter specification with 1.875–
 Clarified input clock configuration register settings 20 MHz integration band.
 Updated DRV_INVERTn[1:0] settings Revision 0.55 to 0.6
 Added PLL bypass mode
 Changed output duty cycle to 45–55%.
 Added LOS_FDBK description
 Added additional detail to phase increment/  All I2C address now in binary.
decrement and frequency increment/decrement  Changed ordering information to reflect 710 MHz
descriptions limit.
 Clarified output driver powerdown options  Info on POR and soft reset added.
 Clarified entry to self-calibration mode  Updated Figure 14 on page 24.
 Updated ordering guide  Added register section.
 Update programming procedure in “3.5. Configuring
Revision 0.2 to 0.3 the Si5338” to improve robustness.
 Changed minimum output clock frequency from  Updated Figure 9 to include the entire programming
5 MHz to 1 MHz. procedure.
 Updated slew rates.  Added "3.2.1. Loss-of-Signal (LOS) Alarm
 Updated " Features" on page 1. Detectors" on page 17 to show the location of the
 Updated Table 6, “Input and Output Clock LOS detector circuits.
Characteristics,” on page 7.  Updated input circuit diagrams in "3.2. Input Stage"
 Deleted Table 12, “Output Driver Slew Rate Control”. on page 17.
 Update block diagrams with new input circuit
Revision 0.3 to 0.5 diagrams.
 Major editorial changes to all sections to improve
clarity
 Completed electrical specification tables with final
characterization results
 Revised the maximum input and output frequencies
from 700 MHz to 710 MHz
 Improved jitter specifications to reflect updated
characterization results
 Added new Si5338N/P/Q ordering codes
 Added typical application diagrams
 Added an application section to highlight the
flexibility of the Si5338 in various timing functions
 Added a configuration section to clarify configuration
options
Rev. 0.6 169

Si5338
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
170 Rev. 0.6

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Si5338

Applications IN5 5 14 CLK2A

 Ethernet switch/router  Any-frequency clock conversion IN6 6

 Broadcast video/audio timing  Fibre Channel, SAN

Rev. 0.6 9/10 Copyright © 2010 by Silicon Laboratories Si5338

Synthesis Synthesis Output

IN5 ÷P2 VDDO2

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Table 2. Absolute Maximum Ratings

Parameter Symbol Test Condition Value Unit

Parameter Symbol Test Condition Min Typ Max Unit

LVDS, 710 MHz — — 8 mA

HCSL, 250 MHz — — 20 mA

HSTL, 350 MHz — — 19 mA

Table 4. Thermal Characteristics

Parameter Symbol Test Condition Value Unit

Table 5. Performance Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

PLL Acquisition Time tACQ — — 25 ms

PLL Lock Range fLOCK 5000 — — ppm

PLL Loop Bandwidth fBW — 1.6 — MHz

MultiSynth Frequency fRES Output frequency < Fvco/8 0 0 1 ppb

POR to Output Clock Valid tRDY — — 2 ms

Output-Output Skew tDSKEW Rn divider = 11 — — 100 ps

POR to I2C Ready — — 15 ms

Programmable Initial –45 — +45 ns

Parameter Symbol Test Condition Min Typ Max Unit

Table 6. Input and Output Clock Characteristics

Parameter Symbol Test Condition Min Typ Max Units

Frequency fIN 5 — 710 MHz

Differential Voltage VPP 710 MHz input 0.4 — 2.4 VPP

Parameter Symbol Test Condition Min Typ Max Units

Input Impedance RIN 10 — — k

Input Capacitance CIN — 3.5 — pF

Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)

Frequency fIN CMOS 5 — 200 MHz

Input Voltage VI –0.1 — 3.63 V

Input Voltage Swing 200 MHz 0.8 — VDD+10% Vpp

Rise/Fall Time tR/tF 20%–80% — — 2 ns

Duty Cycle2,3 DC < 4 ns tr/tf 40 — 60 %

Input Capacitance CIN — 2.0 — pF

Output Clocks (Differential)

LVPECL, LVDS 367 — 473.33 MHz

HCSL 0.16 — 250 MHz

VOC common mode — VDDO–1.45 V — V

VOC common mode 1.125 1.2 1.275 V

VOC common mode 0.8 0.875 0.95 V

Rise/Fall Time tR/tF 20%–80% — — 450 ps

Parameter Symbol Test Condition Min Typ Max Units

Output Clocks (Single-Ended)

CMOS 0.16 — 200 MHz

CMOS 20%–80% tR/tF 2 pF load — 0.45 0.85 ns

VOH SSTL-3 VDDOx = 2.97 0.45xVDDO+0.41 — — V

VOL to 3.63 V — — 0.45xVDDO–0.41 V

VOH SSTL-2 VDDOx = 2.25 0.5xVDDO+0.41 — — V

VOH SSTL-18 VDDOx = 1.71 0.5xVDDO+0.34 — V

VOL to 1.98 V — — 0.5xVDDO–0.34 V

Table 7. Control Pins