Si4464 Datasheet High-Performance, Low-Current Transceiver

S i 4 4 6 4 / 6 3 / 6 1/60
H I G H - P ERFORMANCE , L O W -C U R R E N T T RANSCEIVER
Features
Frequency range = 1191050 MHz Power supply = 1.8 to 3.6 V
Receive sensitivity = 126 dBm Excellent selectivity performance
Modulation 60 dB adjacent channel
(G)FSK, 4(G)FSK, (G)MSK 75 dB blocking at 1 MHz
OOK Antenna diversity and T/R switch control

Max output power Highly configurable packet handler
+20 dBm (Si4464/63) TX and RX 64 byte FIFOs
+16 dBm (Si4461) Auto frequency control (AFC)
+13 dBm (Si4460) Automatic gain control (AGC)
PA support for +27 or +30 dBm Low BOM
Low active power consumption Low battery detector
10/13 mA RX Temperature sensor
18 mA TX at +10 dBm (Si4460) 20-Pin QFN package
Ultra low current powerdown modes IEEE 802.15.4g compliant Pin Assignments
30 nA shutdown, 50 nA standby FCC Part 90 Mask D, FCC part 15.247,
GPIO3
GPIO2
15,231, 15,249, ARIB T-108, T-96, T-67,
XOUT
Data rate = 100 bps to 1 Mbps
GND
XIN
Fast wake and hop times RCR STD-30, China regulatory
ETSI Class-I Operation with SAW SDN 1 20 19 18 17 16
RXp 2 15 nSEL
Applications
RXn 3 GND 14 SDI
Smart metering (802.15.4g & MBus) Remote keyless entry PAD
TX 4 13 SDO
Remote control Home automation
NC 5 12 SCLK
Home security and alarm Industrial control
Telemetry Sensor networks 6 7 8 9 10 11 nIRQ
Garage and gate openers Health monitors VDD
GPIO0
GPIO1
TXRamp
VDD
Electronic shelf labels
Description
Patents pending
Silicon Laboratories' Si446x devices are high-performance, low-current
transceivers covering the sub-GHz frequency bands from 119 to 1050 MHz. The
radios are part of the EZRadioPRO family, which includes a complete line of
transmitters, receivers, and transceivers covering a wide range of applications. All
parts offer outstanding sensitivity of 126 dBm while achieving extremely low
active and standby current consumption. The Si4463/61/60 offers frequency
coverage in all major bands. The Si4464 offers frequency coverage in bands not
covered by Si4463/61/60. Typically, these are non-standard frequencies or
licensed frequency bands. The Si446x includes optimal phase noise, blocking,
and selectivity performance for narrow band and licensed band applications, such
as FCC Part90 and 169 MHz wireless Mbus. The 60 dB adjacent channel
selectivity with 12.5 kHz channel spacing ensures robust receive operation in
harsh RF conditions, which is particularly important for narrow band operation.
The Si4464/63 offers exceptional output power of up to +20 dBm with outstanding
TX efficiency. The high output power and sensitivity results in an industry-leading
link budget of 146 dB allowing extended ranges and highly robust communication
links. The Si4460 active mode TX current consumption of 18 mA at +10 dBm and
RX current of 10 mA coupled with extremely low standby current and fast wake
times ensure extended battery life in the most demanding applications. The
Si4464/63 can achieve up to +27 dBm output power with built-in ramping control
of a low-cost external FET. The devices can meet worldwide regulatory standards:
FCC, ETSI, and ARIB. All devices are designed to be compliant with 802.15.4g
and WMbus smart metering standards. The devices are highly flexible and can be
configured via the Wireless Development Suite (WDS) available on the Silicon
Labs web site.
Rev 1.2 1/16 Copyright 2016 by Silicon Laboratories Si4464/63/62/61/60

Si4464/63/61/60
Functional Block Diagram
GPIO3 GPIO2 XIN XOUT
Loop
PFD / CP
Filter
VCO
FBDIV Frac-N Div 30 MHz XO
LO Bootup
TX DIV
Gen OSC
SDN IF
RF
PKDET PKDET
nSEL
SPI Interface
MODEM
Controller
RXP FIFO SDI
LNA PGA ADC SDO
RXN Packet
Handler SCLK
nIRQ
PowerRamp LDOs
TX PA
Cntl POR Digital
Logic
LBD
PA
32K LP
LDO
OSC
VDD TXRAMP VDD GPIO0 GPIO1
Product Freq. Range Max Output TX Current RX Current Narrow Band Image Cal
Power Support
Si4464 Banded +20 dBm 915 MHz: 85 mA 10.6/13.6 mA
119960 MHz
Si4463 Major bands +20 dBm 169 MHz: 70 mA 10/13 mA

142-1050 MHz 915 MHz: 85 mA
Si4461 Major bands +16 dBm +13 dBm: 29 mA 10/13 mA

142-1050 MHz +14 dBm: 33 mA
Si4460 Major bands +13 dBm +10 dBm: 18 mA 10/13 mA

142-1050 MHz +11 dBm: 20 mA
2 Rev 1.2
Si4464/63/61/60
TABLE O F C ONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2. Fast Response Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4. Application Programming Interface (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4. Modulation and Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1. MODEM_MOD_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2. Modulation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3. Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1. RX Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2. RX Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.4. Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8. Auxiliary Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1. Wake-up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2. Low Duty Cycle Mode (Auto RX Wake-Up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8.3. Temperature, Battery Voltage, and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.5. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9. Pin Descriptions: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11. Package Outline: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
12. PCB Land Pattern: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13.1. Si4464/63/61/60 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Rev 1.2 3
Si4464/63/61/60
1. Electrical Specifications
Table 1. DC Characteristics1
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage VDD 1.8 3.3 3.6 V
Range
Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator, 30 nA
and Low Power Digital Regulator OFF
IStandby Register values maintained and RC 50 nA
oscillator/WUT OFF
ISleepRC RC Oscillator/WUT ON and all register values main- 900 nA
tained, and all other blocks OFF
ISleepXO Sleep current using an external 32 kHz crystal.2 1.7 A
ISensor Low battery detector ON, register values maintained, 1 A
-LBD and all other blocks OFF
IReady Crystal Oscillator and Main Digital Regulator ON, 1.8 mA
all other blocks OFF
TUNE Mode Current ITune_RX RX Tune, High Performance Mode 7.2 mA
ITune_TX TX Tune, High Performance Mode 8 mA
RX Mode Current IRXH High Performance Mode 13.7 mA
IRXL Low Power Mode2 10.7 mA
TX Mode Current ITX_+20 +20 dBm output power, class-E match, 915 MHz, 85 mA
(Si4464/63) 3.3 V
+20 dBm output power, class-E match, 460 MHz, 75 mA
3.3 V
+20 dBm output power, square-wave match, 70 mA
169 MHz, 3.3 V
TX Mode Current ITX_+16 +16 dBm output power, class-E match, 868 MHz, 43 mA
(Si4461) 3.3 V2
ITX_+14 +14 dBm output power, Switched-current match, 37 mA
868 MHz, 3.3 V2
ITX_+13 +13 dBm output power, switched-current match, 29 mA
868 MHz, 3.3 V2
TX Mode Current ITX_+10 +10 dBm output power, Class-E match, 868 MHz, 18 mA
(Si4460) 3.3 V2
Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 14.
2. Guaranteed by qualification. Qualification test conditions are listed in the Qualification Test Conditions section in "1.1.
Definition of Test Conditions" on page 14.
4 Rev 1.2
Si4464/63/61/60
Table 2. Synthesizer AC Electrical Characteristics1

Synthesizer Frequency FSYN 850 1050 MHz
Range (Si4463/61/60)
420 525 MHz
284 350 MHz
142 175 MHz
Synthesizer Frequency FSYN 705 960 MHz

Range (Si4464)
353 639 MHz
177 319 MHz
119 159 MHz
Synthesizer Frequency FRES-960 8501050 MHz 28.6 Hz

Resolution3
FRES-525 420525 MHz 14.3 Hz
FRES-350 283350 MHz 9.5 Hz
FRES-175 142175 MHz 4.7 Hz
Synthesizer Frequency FRES-960 705960 MHz 28.6 Hz

Resolution (Si4464)3
FRES-639 470639 MHz 19.1 Hz
FRES-479 353479 MHz 14.3 Hz
FRES-319 235319 MHz 9.5 Hz
FRES-239 177239 MHz 7.1 Hz
FRES-159 119159 MHz 4.7 Hz
Synthesizer Settling Time4 tLOCK Measured from exiting Ready mode with 50 s
XOSC running to any frequency.
Including VCO Calibration.
Phase Noise4 L(fM) F = 10 kHz, 460 MHz, High Perf Mode 106 dBc/Hz
F = 100 kHz, 460 MHz, High Perf Mode 110 dBc/Hz
F = 1 MHz, 460 MHz, High Perf Mode 123 dBc/Hz
F = 10 MHz, 460 MHz, High Perf Mode 130 dBc/Hz
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the Production Test Conditions section in "1.1. Definition of Test Conditions" on page 14.
2. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
3. Default API setting for modulation deviation resolution is double the typical value specified.
4. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Rev 1.2 5
Si4464/63/61/60
Table 3. Receiver AC Electrical Characteristics1
RX Frequency FRX 850 1050 MHz
Range (Si4463/61/60) 420 525 MHz
284 350 MHz
142 175 MHz
RX Frequency FRX 705 960 MHz
Range (Si4464)
353 639 MHz
177 319 MHz
119 159 MHz
Notes:
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
Si4464.
3. Guaranteed by qualification. BER is specified for the 450470 MHz band. Qualification test conditions are listed in the
"Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
4. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
in the 450470 MHz band.
5. Guaranteed by bench characterization.
6 Rev 1.2
Si4464/63/61/60
Table 3. Receiver AC Electrical Characteristics1 (Continued)
RX Sensitivity PRX_0.5 (BER < 0.1%) 126 dBm
(500 bps, GFSK, BT = 0.5,
f = 250Hz)3
PRX_40 (BER < 0.1%) 110 dBm
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)3
PRX_100 (BER < 0.1%) 106 dBm
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)1
PRX_125 (BER < 0.1%) 105 dBm
(125 kbps, GFSK, BT = 0.5,
f = 62.5 kHz)3
PRX_500 (BER < 0.1%) 97 dBm
(500 kbps, GFSK, BT = 0.5,
f = 250 kHz)3
PRX_9.6 (PER 1%) 110 dBm
(9.6 kbps, 4GFSK, BT = 0.5,
f = kHz)3,4
PRX_1M (PER 1%) 88 dBm
(1 Mbps, 4GFSK, BT = 0.5,
inner deviation = 83.3 kHz)3,4
PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz BW, 110 dBm
OOK, PN15 data)3
(BER < 0.1%, 40 kbps, 350 kHz BW, 104 dBm
OOK, PN15 data)3
(BER < 0.1%, 120 kbps, 350 kHz BW, 99 dBm
OOK, PN15 data)3
RX Channel Bandwidth5 BW 1.1 850 kHz
BER Variation vs Power PRX_RES Up to +5 dBm Input Level 0 0.1 ppm
Level3
RSSI Resolution RESRSSI 0.5 dB
Notes:
Si4464.
Rev 1.2 7
Si4464/63/61/60
Table 3. Receiver AC Electrical Characteristics1 (Continued)
1-Ch Offset Selectivity, C/I1-CH Desired Ref Signal 3 dB above sensitiv- 60 dB
169 MHz3 ity, BER < 0.1%. Interferer is CW, and
1-Ch Offset Selectivity, C/I1-CH desired is modulated with 2.4 kbps 58 dB
450 MHz3 F = 1.2 kHz GFSK with BT = 0.5, RX
channel BW = 4.8 kHz,
1-Ch Offset Selectivity, C/I1-CH channel spacing = 12.5 kHz 53 dB
868 / 915 MHz3
Blocking 1 MHz Offset3 1MBLOCK Desired Ref Signal 3 dB above sensitiv- 75 dB
ity, BER = 0.1%. Interferer is CW, and
Blocking 8 MHz Offset3 8MBLOCK
desired is modulated with 2.4 kbps,
84 dB
F = 1.2 kHz GFSK with BT = 0.5,
RX channel BW = 4.8 kHz
Image Rejection3 ImREJ No image rejection calibration. Rejec- 35 dB
tion at the image frequency.
IF = 468 kHz
With image rejection calibration in 55 dB
Si446x. Rejection at the image fre-
quency. IF = 468 kHz
Notes:
Si4464.
8 Rev 1.2
Si4464/63/61/60
Table 4. Transmitter AC Electrical Characteristics1

TX Frequency
850 1050 MHz
Range (Si4463/61/60)
420 525 MHz

FTX
284 350 MHz
142 175 MHz
705 960 MHz
353 639 MHz

TX Frequency
FTX
Range (Si4464) 177 319 MHz
119 159 MHz
(G)FSK Data Rate3,4 DRFSK 0.1 500 kbps
4(G)FSK Data Rate3,4 DR4FSK 0.2 1000 kbps
OOK Data Rate3,4 DROOK 0.1 120 kbps

Modulation Deviation f960 8501050 MHz 1.5 MHz
Range3
f525 420525 MHz 750 kHz
f350 283350 MHz 500 kHz
f175 142175 MHz 250 kHz

Modulation Deviation f960 1.5 MHz
705960 MHz
Range (Si4464)3
f639 1 MHz
470639 MHz
f479 750 kHz
353479 MHz
f319 500 kHz
235319 MHz
f239 375 kHz
177239 MHz
f159 250 kHz
119159 MHz
Notes:
Si4464.
4. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
6. Output power is dependent on matching components and board layout.
Rev 1.2 9
Si4464/63/61/60
Table 4. Transmitter AC Electrical Characteristics1 (Continued)
Modulation Deviation FRES-960 8501050 MHz 28.6 Hz
Resolution2,5
FRES-525 420525 MHz 14.3 Hz
FRES-350 283350 MHz 9.5 Hz
FRES-175 142175 MHz 4.7 Hz

Modulation Deviation FRES-960 28.6 Hz
705960 MHz
Resolution (Si4464)3
FRES-639 19.1 Hz
470639 MHz
FRES-479 14.3 Hz
353479 MHz
FRES-319 9.5 Hz
235319 MHz
FRES-239 7.1 Hz
177239 MHz
FRES-159 4.7 Hz
119159 MHz
Output Power Range
PTX 20 +20 dBm
(Si4464/63)6
Output Power Range
PTX61 40 +16 dBm
(Si4461)6
Output Power Range
PTX60 40 +13 dBm
(Si4460)6
TX RF Output Steps3 PRF_OUT
Using switched current match within
0.1 dB
6 dB of max power
TX RF Output Level3
PRF_TEMP 40 to +85 C 1 dB
Variation vs. Temperature
TX RF Output Level
Variation vs. Frequency3 PRF_FREQ Measured across 902928 MHz 0.5 dB
Transmit Modulation Gaussian Filtering Bandwith Time

Filtering3 B*T 0.5
Product
Notes:
Si4464.
4. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
6. Output power is dependent on matching components and board layout.
10 Rev 1.2
Si4464/63/61/60
Table 5. Auxiliary Block Specifications1

Temperature Sensor TSS 4.5 ADC
Sensitivity2 Codes/
C
Low Battery Detector LBDRES 50 mV
Resolution
Microcontroller Clock FMC Configurable to Fxtal or Fxtal 32.768K Fxtal Hz
Output Frequency Range3 divided by 2, 3, 7.5, 10, 15, or
30 where Fxtal is the reference
XTAL frequency. In addition,
32.768 kHz is also supported.
Temperature Sensor TEMPCT Programmable setting 3 ms
Conversion2
XTAL Range4 XTALRange 25 32 MHz
30 MHz XTAL Start-Up Time t30M Using XTAL and board layout in 250 s
reference design. Start-up time
will vary with XTAL type and
board layout.
30 MHz XTAL Cap 30MRES
70 fF
Resolution2
32 kHz XTAL Start-Up Time2 t32k 2 sec
32 kHz Accuracy using 32KRCRES 2500 ppm
Internal RC Oscillator2
POR Reset Time tPOR 5 ms
Notes:
3. Microcontroller clock frequency tested in production at 1 MHz, 30 MHz and 32.768 kHz. Other frequencies tested in
bench characterization.
4. XTAL Range tested in production using an external clock source (similar to using a TCXO).
Rev 1.2 11
Si4464/63/61/60
Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ, SDN)1
2,3
Rise Time TRISE 0.1 x VDD to 0.9 x VDD, 2.3 ns
CL = 10 pF,
DRV<1:0> = HH
Fall Time3,4 TFALL 0.9 x VDD to 0.1 x VDD, 2 ns
CL = 10 pF,
DRV<1:0> = HH
Input Capacitance CIN 2 pF
Logic High Level Input Voltage VIH VDD x 0.7 V
Logic Low Level Input Voltage VIL VDD x 0.3 V
Input Current IIN 0<VIN< VDD 10 10 A
Input Current If Pullup is Activated IINP VIL = 0 V 1 10 A
Drive Strength for Output Low IOmaxLL DRV[1:0] = LL3 6.66 mA
Level 3
IOmaxLH DRV[1:0] = LH 5.03 mA
3
IOmaxHL DRV[1:0] = HL 3.16 mA
IOmaxHH DRV[1:0] = HH3 1.13 mA
3
Drive Strength for Output High IOmaxLL DRV[1:0] = LL 5.75 mA
Level 3
IOmaxLH DRV[1:0] = LH 4.37 mA
IOmaxHL DRV[1:0] = HL3 2.73 mA
3
Drive Strength for Output High IOmaxLL DRV[1:0] = LL 2.53 mA
Level for GPIO0
IOmaxLH DRV[1:0] = LH3 2.21 mA
3
IOmaxHL DRV[1:0] = HL 1.7 mA
Logic High Level Output Voltage VOH DRV[1:0] = HL VDD x 0.8 V
Logic Low Level Output Voltage VOL DRV[1:0] = HL VDD x 0.2 V
Notes:
1. All specifications guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test
Conditions" section in "1.1. Definition of Test Conditions" on page 14.
2. 8 ns is typical for GPIO0 rise time.
3. Assuming VDD = 3.3 V, drive strength is specified at Voh (min) = 2.64 V and Vol(max) = 0.66 V at room temperature.
4. 2.4 ns is typical for GPIO0 fall time.
12 Rev 1.2
Si4464/63/61/60
Table 7. Absolute Maximum Ratings

Parameter Value Unit
VDD to GND 0.3, +3.6 V
Instantaneous VRF-peak to GND on TX Output Pin 0.3, +8.0 V
Sustained VRF-peak to GND on TX Output Pin 0.3, +6.5 V
Voltage on Digital Control Inputs 0.3, VDD + 0.3 V
Voltage on Analog Inputs 0.3, VDD + 0.3 V
RX Input Power +10 dBm
Operating Ambient Temperature Range TA 40 to +85 C
Thermal Impedance JA 30 C/W
Junction Temperature TJ +125 C
Storage Temperature Range TSTG 55 to +125 C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX
matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device.
Rev 1.2 13
Si4464/63/61/60
1.1. Definition of Test Conditions
Production Test Conditions:
TA = +25 C.
VDD = +3.3 VDC.
TX output power measured at 915 MHz.
External reference signal (XOUT) = 1.0 VPP at 30 MHz, centered around 0.8 VDC.
Production test schematic (unless noted otherwise).
All TX output levels are referred to the pins of the Si4464/63/61/60 (not the output of the RF module).
All RX input levels are referred to the input of a tuned balun connected to the RX input pins of the
Si4464/63/61/60.
Qualification Test Conditions:
TA = 40 to +85 C (Typical TA = 25 C).
VDD = +1.8 to +3.6 VDC (Typical VDD = 3.3 VDC).
Using TX/RX Split Antenna reference design or production test schematic.
All RF input and output levels referred to the pins of the Si4464/63/61/60 (not the RF module).
14 Rev 1.2
Si4464/63/61/60
2. Functional Description
The Si446x devices are high-performance, low-current, wireless ISM transceivers that cover the sub-GHz bands.
The wide operating voltage range of 1.83.6 V and low current consumption make the Si446x an ideal solution for
battery powered applications. The Si446x operates as a time division duplexing (TDD) transceiver where the
device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert
the 2/4-level FSK/GFSK or OOK modulated receive signal to a low IF frequency. Following a programmable gain
amplifier (PGA) the signal is converted to the digital domain by a high performance ADC allowing filtering,
demodulation, slicing, and packet handling to be performed in the built-in DSP increasing the receivers
performance and flexibility versus analog based architectures. The demodulated signal is output to the system
MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and
receiver do not operate at the same time. The LO is generated by an integrated VCO and Fractional-N PLL
synthesizer. The synthesizer is designed to support configurable data rates from 100 bps to 1 Mbps. The
Si4463/61/60 operate in the frequency bands of 142175, 283350, 420525, and 8501050 MHz with a
maximum frequency accuracy step size of 28.6 Hz. The Si4464 offers frequency coverage in bands not supported
by Si4463/61/60. The transmit FSK data is modulated directly into the data stream and can be shaped by a
Gaussian low-pass filter to reduce unwanted spectral content.
The Si4464/63 contains a power amplifier (PA) that supports output power up to +20 dBm with very high efficiency,
consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power amplifier can also be
used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size
constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve
comparable performance. The Si4461 supplies output power up to +16 dBm. The Si4460 is designed to support
single coin cell operation with current consumption below 18 mA for +10 dBm output power. Two match topologies
are available for the Si4461 and Si4460, class-E and switched-current. Class-E matching provides optimal current
consumption, while switched-current matching demonstrates the best performance over varying battery voltage
and temperature with slightly higher current consumption. The PA is single-ended to allow for easy antenna
matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted
spectral spreading. The Si446x family supports frequency hopping, TX/RX switch control, and antenna diversity
switch control to extend the link range and improve performance. Built-in antenna diversity and support for
frequency hopping can be used to further extend range and enhance performance. Antenna diversity is completely
integrated into the Si446x and can improve the system link budget by 810 dB, resulting in substantial range
increases under adverse environmental conditions. A highly configurable packet handler allows for autonomous
encoding/decoding of nearly any packet structure. Additional system features, such as an automatic wake-up
timer, low battery detector, 64 byte TX/RX FIFOs, and preamble detection, reduce overall current consumption and
allows for the use of lower-cost system MCUs. An integrated temperature sensor, power-on-reset (POR), and
GPIOs further reduce overall system cost and size. The Si446x is designed to work with an MCU, crystal, and a
few passive components to create a very low-cost system.
The application shown in Figure 1 is designed for a system with a TX/RX direct-tie configuration without the use of
a TX/RX switch. Most applications with output power less than 17 dBm will use this configuration. Figure 2
demonstrates an application for +20 dBm using an external T/R-switch.
Rev 1.2 15
Si4464/63/61/60
30 MHz
GPIO2
GPIO3
XOUT
GND
XIN
C6
Microcontroller
20 19 18 17 16
SDN nSEL GP1
1 15
RXp SDI GP2
L5 2 14
C2
L4 L3 RXn SDO GP3
3 Si4461 13
L2 TX SCLK GP4
4 12
NC nIRQ GP5
C4 C1 5 11
C5 C3 6 7 8 9 10
L1
VDD
TXRAMP
GPIO0
GPIO1
VDD
VDD
C7 C8 C9
100 p 100 n 1u
Figure 1. Si4461 Direct-Tie Application Example
30 MHz
GPIO2
GPIO3
XOUT
GND
XIN
C7
Microcontroller
20 19 18 17 16
SDN nSEL GP1
1 15
RXp SDI GP2
L5 2 14
C6
L4 RXn SDO GP3
3 Si4463 13
L3 L2 TX SCLK GP4
4 12
NC nIRQ GP5
C4 C1 5 11
C5 6 7 8 9 10
C3 C2 L1
VDD
TXRAMP
GPIO0
GPIO1
VDD
VDD
Figure 2. Si4463 Single Antenna with RF Switch Example
16 Rev 1.2
Si4464/63/61/60
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si446x communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI,
SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters
are demonstrated in Table 8. The host MCU writes data over the SDI pin and can read data from the device on the
SDO output pin. Figure 3 demonstrates an SPI write command. The nSEL pin should go low to initiate the SPI
command. The first byte of SDI data will be one of the firmware commands followed by n bytes of parameter data
which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the
center of the SDI data.
Table 8. Serial Interface Timing Parameters

Symbol Parameter Min (ns) Diagram
tCH Clock high time 40
tCL Clock low time 40

SCLK
tDS Data setup time 20
tSS tCL tCH tDS tDH tDD tSH tDE
tDH Data hold time 20
SDI
tDD Output data delay time 20
tEN Output enable time 20
tDE Output disable time 50 SDO
tSS Select setup time 20 tEN tSW
tSH Select hold time 50 nSEL
tSW Select high period 80
nSEL
SDO
SDI FW Command Param Byte 0 Param Byte n
SCLK
Figure 3. SPI Write Command

The Si446x contains an internal MCU which controls all the internal functions of the radio. For SPI read commands
a typical MCU flow of checking clear-to-send (CTS) is used to make sure the internal MCU has executed the
command and prepared the data to be output over the SDO pin. Figure 4 demonstrates the general flow of an SPI
read command. Once the CTS value reads FFh then the read data is ready to be clocked out to the host MCU. The
typical time for a valid FFh CTS reading is 20 s. Figure 5 demonstrates the remaining read cycle after CTS is set
to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU should process the
SDO data on the rising edge of SCLK.
Rev 1.2 17
Si4464/63/61/60
Firmware Flow
0xFF Retrieve
Send Command Read CTS CTS Value
Response
0x00
NSEL
SDO CTS
SDI ReadCmdBuff
SCK
Figure 4. SPI Read CommandCheck CTS Value
NSEL
SDO Response Byte 0 Response Byte n
SDI
SCK
Figure 5. SPI Read CommandClock Out Read Data
18 Rev 1.2
Si4464/63/61/60
3.2. Fast Response Registers
The fast response registers are registers that can be read immediately without the requirement to monitor and
check CTS. There are four fast response registers that can be programmed for a specific function. The fast
response registers can be read through API commands, 0x50 for Fast Response A, 0x51 for Fast Response B,
0x53 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can be configured by the
FRR_CTL_X_MODE properties.
The fast response registers may be read in a burst fashion. After the initial 16 clock cycles, each additional eight
clock cycles will clock out the contents of the next fast response register in a circular fashion. The value of the
FRRs will not be updated unless NSEL is toggled.
3.3. Operating Modes and Timing
The primary states of the Si446x are shown in Figure 6. The shutdown state completely shuts down the radio to
minimize current consumption. Standby/Sleep, SPI Active, Ready, TX Tune, and RX tune are available to optimize
the current consumption and response time to RX/TX for a given application. API commands START_RX,
START_TX, and CHANGE_STATE control the operating state with the exception of shutdown which is controlled
by SDN, pin 1. Table 9 shows each of the operating modes with the time required to reach either RX or TX mode as
well as the current consumption of each mode. The times in Table 9 are measured from the rising edge of nSEL
until the chip is in the desired state. Note that these times are indicative of state transition timing but are not
guaranteed and should only be used as a reference data point. An automatic sequencer will put the chip into RX or
TX from any state. It is not necessary to manually step through the states. To simplify the diagram it is not shown
but any of the lower power states can be returned to automatically after RX or TX.
Figure 6. State Machine Diagram
Rev 1.2 19
Si4464/63/61/60
Table 9. Operating State Response Time and Current Consumption*

Response Time to Current in State
State/Mode
TX RX /Mode
Shutdown State 15 ms 15 ms 30 nA
Standby State 440 s 440 s 50 nA
Sleep State 440 s 440 s 900 nA
SPI Active State 340 s 340 s 1.35 mA
Ready State 126 s 122 s 1.8 mA
TX Tune State 58 s 8 mA
RX Tune State 74 s 7.2 mA
TX State 138 s 18 mA @ +10 dBm
RX State 130 s 75 s 10 or 13 mA
*Note: TXRX and RXTX state transition timing can be reduced to 70 s if using Zero-IF mode.
Figure 7 shows the POR timing and voltage requirements. The power consumption (battery life) depends on the
duty cycle of the application or how often the part is in either Rx or Tx state. In most applications the utilization of
the standby state will be most advantageous for battery life but for very low duty cycle applications shutdown will
have an advantage. For the fastest timing the next state can be selected in the START_RX or START_TX API
commands to minimize SPI transactions and internal MCU processing.
3.3.1. Power on Reset (POR)
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this
process, VDD must ramp within 1ms and must remain applied to the device for at least 10ms. If VDD is removed,
then it must stay below 0.15V for at least 10ms before being applied again. Please see Figure x and Table x for
details.
VDD
VR RH
VR RL
Time
tSR tPORH
Figure 7. POR Timing Diagram
20 Rev 1.2
Si4464/63/61/60
Table 10. POR Timing
Variable Description Min Typ Max Units
tPORH High time for VDD to fully settle POR circuit 10 ms
tPORL Low time for VDD to enable POR 10 ms
VRRH Voltage for successful POR 90%*Vdd V
VRRL Starting Voltage for successful POR 0 150 mV
tSR Slew rate of VDD for successful POR 1 ms
3.3.2. Shutdown State

The shutdown state is the lowest current consumption state of the device with nominally less than 30 nA of current
consumption. The shutdown state may be entered by driving the SDN pin (Pin 1) high. The SDN pin should be held
low in all states except the shutdown state. In the shutdown state, the contents of the registers are lost and there is
no SPI access. When coming out of the shutdown state a power on reset (POR) will be initiated along with the
internal calibrations. After the POR the POWER_UP command is required to initialize the radio. The SDN pin
needs to be held high for at least 10us before driving low again so that internal capacitors can discharge. Not
holding the SDN high for this period of time may cause the POR to be missed and the device to boot up incorrectly.
If POR timing and voltage requirements cannot be met, it is highly recommended that SDN be controlled using the
host processor rather than tying it to GND on the board.
3.3.3. Standby State
Standby state has the lowest current consumption with the exception of shutdown but has much faster response
time to RX or TX mode. In most cases standby should be used as the low power state. In this state the register
values are maintained with all other blocks disabled. The SPI is accessible during this mode but any SPI event,
including FIFO R/W, will enable an internal boot oscillator and automatically move the part to SPI active state. After
an SPI event the host will need to re-command the device back to standby through the Change State API
command to achieve the 50 nA current consumption. If an interrupt has occurred (i.e., the nIRQ pin = 0) the
interrupt registers must be read to achieve the minimum current consumption of this mode.
3.3.4. Sleep State
Sleep state is the same as standby state but the wake-up-timer and a 32 kHz clock source are enabled. The
source of the 32 kHz clock can either be an internal 32 kHz RC oscillator which is periodically calibrated or a
32 kHz oscillator using an external XTAL.The SPI is accessible during this mode but an SPI event will enable an
internal boot oscillator and automatically move the part to SPI active mode. After an SPI event the host will need to
re-command the device back to sleep. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers
must be read to achieve the minimum current consumption of this mode.
3.3.5. SPI Active State
In SPI active state the SPI and a boot up oscillator are enabled. After SPI transactions during either standby or
sleep the device will not automatically return to these states. A Change State API command will be required to
return to either the standby or sleep modes.
3.3.6. Ready State
Ready state is designed to give a fast transition time to TX or RX state with reasonable current consumption. In this
mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode by eliminating
the crystal start-up time.
3.3.7. TX State
The TX state may be entered from any of the state with the Start TX or Change State API commands. A built-in
sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to
ramping up the PA. The following sequence of events will occur automatically when going from standby to TX state.
1. Enable internal LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
Rev 1.2 21
Si4464/63/61/60
3. Enable PLL.
4. Calibrate VCO/PLL.
5. Wait until PLL settles to required transmit frequency (controlled by an internal timer).
6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit packet.
Steps in this sequence may be eliminated depending on which state the chip is configured to prior to commanding
to TX. By default, the VCO and PLL are calibrated every time the PLL is enabled. When the START_TX API
command is utilized the next state may be defined to ensure optimal timing and turnaround.
Figure 8 shows an example of the commands and timing for the START_TX command. CTS will go high as soon
as the sequencer puts the part into TX state. As the sequencer is stepping through the events listed above, CTS
will be low and no new commands or property changes are allowed. If the Fast Response (FRR) or nIRQ is used to
monitor the current state there will be slight delay caused by the internal hardware from when the event actually
occurs to when the transition occurs on the FRR or nIRQ. The time from entering TX state to when the FRR will
update is 5 s and the time to when the nIRQ will transition is 13 s. If a GPIO is programmed for TX state or used
as control for a transmit/receive switch (TR switch) there is no delay.
CTS
NSEL
SDI START_TX
Current State YYY State Tx State TXCOMPLETE_STATE
FRR YYY State Tx State TXCOMPLETE_STATE
nIRQ
GPIOx TX state
Figure 8. Start_TX Commands and Timing

3.3.8. RX State
The RX state may be entered from any of the other states by using the Start RX or Change State API command.
A built-in sequencer takes care of all the actions required to transition between states. The following sequence of
events will occur automatically to get the chip into RX mode when going from standby to RX state:
1. Enable the digital LDO and the analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO
5. Wait until PLL settles to required receive frequency (controlled by an internal timer).
6. Enable receiver circuits: LNA, mixers, and ADC.
7. Enable receive mode in the digital modem.
Depending on the configuration of the radio, all or some of the following functions will be performed automatically
by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional)
including sync word, header check, and CRC. Similar to the TX state, the next state after RX may be defined in the
Start RX API command. The START_RX commands and timing will be equivalent to the timing shown in Figure 8.
22 Rev 1.2
Si4464/63/61/60
3.4. Application Programming Interface (API)
An application programming interface (API), which the host MCU will communicate with, is embedded inside the
device. The API is divided into two sections, commands and properties. The commands are used to control the
chip and retrieve its status. The properties are general configurations which will change infrequently. The API
descriptions can be found inAN625: Si446x API Descriptions.
3.5. Interrupts
The Si446x is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) occur.
The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output signal
will then be reset until the next change in status is detected.
The interrupts sources are grouped into three groups: packet handler, chip status, and modem. The individual
interrupts in these groups can be enabled/disabled in the interrupt property registers, 0101, 0102, and 0103. An
interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as
the individual interrupts in API property 0100.
Number Command Summary

Returns the interrupt statuspacket handler, modem,
0x20 GET_INT_STATUS
and chip
0x21 GET_PH_STATUS Returns the packet handler status.
0x22 GET_MODEM_STATUS Returns the modem status byte.
0x23 GET_CHIP_STATUS Returns the chip status.
Number Property Default Summary

Enables interrupt groups for PH, Modem, and
0x0100 INT_CTL_ENABLE 0x04
Chip.
0x0101 INT_CTL_PH_ENABLE 0x00 Packet handler interrupt enable property.
0x0102 INT_CTL_MODEM_ENABLE 0x00 Modem interrupt enable property.
0x0103 INT_CTL_CHIP_ENABLE 0x04 Chip interrupt enable property.
Once an interrupt event occurs and the nIRQ pin is low there are two ways to read and clear the interrupts. All of
the interrupts may be read and cleared in the GET_INT_STATUS API command. By default all interrupts will be
cleared once read. If only specific interrupts want to be read in the fastest possible method the individual interrupt
groups (Packet Handler, Chip Status, Modem) may be read and cleared by the GET_MODEM_STATUS,
GET_PH_STATUS (packet handler), and GET_CHIP_STATUS API commands.
The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled. The
status results are provided after the interrupts and can be read with the same commands as the interrupts. The
status bits will give the current state of the function whether the interrupt is enabled or not.
The fast response registers can also give information about the interrupt groups but reading the fast response
registers will not clear the interrupt and reset the nIRQ pin.
Rev 1.2 23
Si4464/63/61/60
3.6. GPIO
Four general purpose IO pins are available to utilize in the application. The GPIO are configured by the
GPIO_PIN_CFG command in address 13h. For a complete list of the GPIO options please see the API guide.
GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have more
susceptibility to generating spurious in the synthesizer than pins 0 and 1. The drive strength of the GPIOs can be
adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By default the drive strength is set
to minimum. The default configuration for the GPIOs and the state during SDN is shown below in Table 11.The
state of the IO during shutdown is also shown inTable 11. As indicated previously in Table 6, GPIO 0 has lower
drive strength than the other GPIOs.
Table 11. GPIOs

Pin SDN State POR Default
GPIO0 0 POR
GPIO1 0 CTS
GPIO2 0 POR
GPIO3 0 POR
nIRQ resistive VDD pull-up nIRQ
SDO resistive VDD pull-up SDO
SDI High Z SDI
24 Rev 1.2
Si4464/63/61/60
4. Modulation and Hardware Configuration Options
The Si446x supports different modulation options and can be used in various configurations to tailor the device to
any specific application or legacy system for drop in replacement. The modulation and configuration options are set
in API property, MODEM_MOD_TYPE.
4.1. MODEM_MOD_TYPE
Summary: Modulation Type
Purpose:
This property selects between OOK, FSK, 4FSK and GFSK modulation, modulation source, and tx direct mode
control.
The modulator must be configured for one mode through the entire packet. If portions of the packet alternate
between FSK and 4FSK modes, the modem should be programmed to 4FSK mode.
Property: 0x2000
Default: 0x02
Fields:
TX_DIRECT_MODE_TYPE - default:0
0 = Direct mode operates in synchronous mode, applies to TX only.
1 = Direct mode operates in asynchronous mode, applies to TX only. GFSK is not supported.
TX_DIRECT_MODE_GPIO[1:0] - default:0x0
0 = TX direct mode uses gpio0 as data source, applies to TX only.
MOD_SOURCE[1:0] - default:0x0
0 = Modulation source is packet handler fifo
1 = Modulation source is direct mode pin
2 = Modulation source is pseudo-random generator
MOD_TYPE[2:0] - default:0x2
0 = CW
1 = OOK
2 = 2FSK
3 = 2GFSK
4 = 4FSK
5 = 4GFSK
Register View
MODEM_MOD_TYPE
7 6 5 4 3 2 1 0
TX_DIRECT_MODE_TYPE TX_DIRECT_MODE_GPIO[1:0] MOD_SOURCE[1:0] MOD_TYPE[2:0]
0 0x0 0x0 0x2
Rev 1.2 25
Si4464/63/61/60
4.2. Modulation Types
The Si446x supports five different modulation options: Gaussian frequency shift keying (GFSK), frequency-shift
keying (FSK), four-level GFSK (4GFSK), four-level FSK (4FSK), and on-off keying (OOK). Minimum shift keying
(MSK) can also be created by using GFSK settings. GFSK is the recommended modulation type as it provides the
best performance and cleanest modulation spectrum. The modulation type is set by the MOD_TYPE[2:0]
registers in the MODEM_MOD_TYPE API property. A continuous-wave (CW) carrier may also be selected for RF
evaluation purposes. The modulation source may also be selected to be a pseudo-random source for evaluation
purposes.
4.3. Hardware Configuration Options
There are different receive demodulator options to optimize the performance and mutually-exclusive options for
how the RX/TX data is transferred from the host MCU to the RF device.
4.3.1. Receive Demodulator Options
There are multiple demodulators integrated into the device to optimize the performance for different applications,
modulation formats, and packet structures. The calculator built into WDS will choose the optimal demodulator
based on the input criteria.
4.3.1.1. Synchronous Demodulator
The synchronous demodulator's internal frequency error estimator acquires the frequency error based on a
101010 preamble structure. The bit clock recovery circuit locks to the incoming data stream within four transactions
of a 10 or 01 bit stream. The synchronous demodulator gives optimal performance for 2- or 4-level FSK or
GFSK modulation that has a modulation index less than 2.
4.3.1.2. Asynchronous Demodulator
The asynchronous demodulator should be used OOK modulation and for FSK/GFSK/4GFSK under one or more of
the following conditions:
Modulation index > 2
Non-standard preamble (not 1010101... pattern)
When the modulation index exceeds 2, the asynchronous demodulator has better sensitivity compared to the
synchronous demodulator. An internal deglitch circuit provides a glitch-free data output and a data clock signal to
simplify the interface to the host. There is no requirement to perform deglitching in the host MCU. The
asynchronous demodulator will typically be utilized for legacy systems and will have many performance benefits
over devices used in legacy designs. Unlike the Si4432/31 solution for non-standard packet structures, there is no
requirement to perform deglitching on the data in the host MCU. Glitch-free data is output from Si446x devices, and
a sample clock for the asynchronous data can also be supplied to the host MCU; so, oversampling or bit clock
recovery is not required by the host MCU. There are multiple detector options in the asynchronous demodulator
block, which will be selected based upon the options entered into the WDS calculator. The asynchronous
demodulator's internal frequency error estimator is able to acquire the frequency error based on any preamble
structure.
4.3.2. RX/TX Data Interface With MCU
There are two different options for transferring the data from the RF device to the host MCU. FIFO mode uses the
SPI interface to transfer the data, while direct mode transfers the data in real time over GPIO.
4.3.2.1. FIFO Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is
accessed by writing Command 66h followed directly by the data/clk that the host wants to write into the TX FIFO.
The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data the host would
like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin.
In TX mode, if the packet handler is enabled, the data bytes stored in FIFO memory are packaged together with
other fields and bytes of information to construct the final transmit packet structure. These other potential fields
include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX
mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
properties. If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into
FIFO memory; no other fields (such as Preamble or Sync word) will be automatically added to the bytes stored in
26 Rev 1.2
Si4464/63/61/60
FIFO memory. For further information on the configuration of the FIFOs for a specific application or packet size,
see "6. Data Handling and Packet Handler" on page 39. In RX mode, only the bytes of the received packet
structure that are considered to be data bytes are stored in FIFO memory. Which bytes of the received packet are
considered data bytes is determined by the Automatic Packet Handler (if enabled) in conjunction with the Packet
Handler configuration. If the Automatic Packet Handler is disabled, all bytes following the Sync word are
considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not
desired, the preamble detection threshold and Sync word still need to be programmed so that the RX Modem
knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the received data
may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can
be quite useful during application development. When in FIFO mode, the chip will automatically exit the TX or RX
State when either the PACKET_SENT or PACKET_RX interrupt occurs. The chip will return to the IDLE state
programmed in the argument of the START TX or START RX API command, TXCOMPLETE_STATE[3:0] or
RXVALID_STATE[3:0]. For example, the chip may be placed into TX mode by sending the START TX command
and by writing the 30h to the TXCOMPLETE_STATE[3:0] argument. The chip will transmit all of the contents of the
FIFO, and the ipksent interrupt will occur. When this event occurs, the chip will return to the ready state as defined
by TXCOMPLETE_STATE[3:0] = 30h.
4.3.2.2. Direct Mode
For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct mode is provided, which bypasses the FIFOs entirely. In TX
Direct mode, the TX modulation data is applied to an input pin of the chip and processed in real time (i.e., not
stored in a register for transmission at a later time). Any of the GPIOs may be configured for use as the TX Data
input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK). To achieve direct mode, the GPIO must be configured in
the GPIO_PIN_CFG API command as well as the MODEM_MOD_TYPE API property. For GFSK,
TX_DIRECT_MODE_TYPE must be set to Synchronous. For 2FSK or OOK, the type can be set to asynchronous
or synchronous. The MOD_SOURCE[1:0] should be set to 01h for are all direct mode configurations. In RX Direct
mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO pins. The
microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC.
4.4. Preamble Length
The preamble length requirement is only relevant if using the synchronous demodulator. If the asynchronous
demodulator is being used, then there is no requirement for a conventional 101010 pattern.
The preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a
valid preamble. The preamble threshold should be adjusted depending on the nature of the application. The
required preamble length threshold depends on when receive mode is entered in relation to the start of the
transmitted packet and the length of the transmit preamble. With a shorter than recommended preamble detection
threshold, the probability of false detection is directly related to how long the receiver operates on noise before the
transmit preamble is received. False detection on noise may cause the actual packet to be missed. The preamble
detection threshold may be adjusted in the modem calculator by modifying the PM detection threshold in the RX
parameters tab in the radio control panel. For most applications with a preamble length longer than 32 bits, the
default value of 20 is recommended for the preamble detection threshold. A shorter Preamble Detection Threshold
may be chosen if occasional false detections may be tolerated. When antenna diversity is enabled, a 20- bit
preamble detection threshold is recommended. When the receiver is synchronously enabled just before the start of
the packet, a shorter preamble detection threshold may be used. Table 12 demonstrates the recommended
preamble detection threshold and preamble length for various modes.
Rev 1.2 27
Si4464/63/61/60
Table 12. Recommended Preamble Length

Mode AFC Antenna Preamble Type Recommended Recommended
Diversity Preamble Length Preamble Detection
Threshold
(G)FSK Disabled Disabled Standard 4 Bytes 20 bits
(G)FSK Enabled Disabled Standard 5 Bytes 20 bits
(G)FSK Disabled Disabled Non-standard 2 Bytes 0 bits
(G)FSK Enabled Non-standard Not Supported
(G)FSK Disabled Enabled Standard 7 Bytes 24 bits
(G)FSK Enabled Enabled Standard 8 Bytes 24 bits
4(G)FSK Disabled Disabled Standard 40 symbols 16 symbols
4(G)FSK Enabled Disabled Standard 48 symbols 16 symbols
4(G)FSK Non-standard Not Supported
OOK Disabled Disabled Standard 4 Bytes 20 bits
OOK Disabled Disabled Non-standard 2 Bytes 0 bits
OOK Enabled Not Supported
Notes:
1. The recommended preamble length and preamble detection thresholds listed above are to achieve 0% PER. They may
be shortened when occasional packet errors are tolerable.
2. All recommended preamble lengths and detection thresholds include AGC and BCR settling times.
3. Standard preamble type should be set for an alternating data sequence at the max data rate (10101010)
4. Non-standard preamble type can be set for any preamble type including 10101010...
5. When preamble detection threshold = 0, sync word needs to be 3 Bytes to avoid false syncs. When only a 2 Byte sync
word is available the sync word detection can be extended by including the last preamble Byte into the RX sync word
setting.
28 Rev 1.2
Si4464/63/61/60
5. Internal Functional Blocks
The following sections provide an overview to the key internal blocks and features.
5.1. RX Chain
The internal low-noise amplifier (LNA) is designed to be a wide-band LNA that can be matched with three external
discrete components to cover any common range of frequencies in the sub-GHz band. The LNA has extremely low
noise to suppress the noise of the following stages and achieve optimal sensitivity; so, no external gain or front-end
modules are necessary. The LNA has gain control, which is controlled by the internal automatic gain control (AGC)
algorithm. The LNA is followed by an I-Q mixer, filter, programmable gain amplifier (PGA), and ADC. The I-Q
mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic
range of the ADC. The ADC rejects out-of-band blockers and converts the signal to the digital domain where
filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and
PGA for use in the AGC algorithm.
The RX and TX pins maybe directly tied externally for output powers less than +17 dBm, see the direct-tie
reference designs on the Silicon Labs web site for more details.
5.1.1. RX Chain Architecture
It is possible to operate the RX chain in different architecture configurations: fixed-IF, zero-IF, scaled-IF, and
modulated IF. There are trade-offs between the architectures in terms of sensitivity, selectivity, and image rejection.
Fixed-IF is the default configuration and is recommended for most applications. With 35 dB native image rejection
and autonomous image calibration to achieve 55 dB, the fixed-IF solution gives the best performance for most
applications. Fixed-IF obtains the best sensitivity, but it has the effect of degraded selectivity at the image frequency.
An autonomous image rejection calibration is included in Si446x devices and described in more detail in "5.2.3.
Image Rejection and Calibration" on page 31. For fixed-IF and zero-IF, the sensitivity is degraded for data rates less
than 100 kbps or bandwidths less than 200 kHz. The reduction in sensitivity is caused by increased flicker noise as
dc is approached. The benefit of zero-IF is that there is no image frequency; so, there is no degradation in the
selectivity curve, but it has the worst sensitivity. Scaled-IF is a trade-off between fixed-IF and zero-IF. In the
scaled-IF architecture, the image frequency is placed or hidden in the adjacent channel where it only slightly
degrades the typical adjacent channel selectivity. The scaled-IF approach has better sensitivity than zero-IF but still
some degradation in selectivity due to the image. In scaled-IF mode, the image frequency is directly proportional to
the channel bandwidth selected. Figure 9 demonstrates the trade-off in sensitivity between the different architecture
options.
1% PER sensitivity vs. data rate (h=1)

-95
-100
Sensitivity (dBm)
-105
Fixed IF
Scaled IF
-110
Zero IF
-115
-120
1 10 100
Data rate (kbps)
Figure 9. RX Architecture vs. Data Rate
Rev 1.2 29
Si4464/63/61/60
5.2. RX Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the
digital domain, which allows for flexibility in optimizing the device for particular applications. The digital modem
performs the following functions:
Channel selection filter
TX modulation
RX demodulation
Automatic Gain Control (AGC)
Preamble detection
Invalid preamble detection
Radio signal strength indicator (RSSI)
Automatic frequency compensation (AFC)
Image Rejection Calibration
Packet handling including EZMAC features
Cyclic redundancy check (CRC)
The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly
configurable. Supported modulation types are GFSK, FSK, 4GFSK, 4FSK, GMSK, and OOK. The channel filter
can be configured to support bandwidths ranging from 850 down to 1.1 kHz. A large variety of data rates are
supported ranging from 100 bps up to 1 Mbps. The configurable preamble detector is used with the synchronous
demodulator to improve the reliability of the sync-word detection. Preamble detection can be skipped using only
sync detection, which is a valuable feature of the asynchronous demodulator when very short preambles are used
in protocols, such as MBus. The received signal strength indicator (RSSI) provides a measure of the signal
strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high-resolution RSSI enables
accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before
talk (LBT) functionality. A comprehensive programmable packet handler including key features of Silicon Labs
EZMAC is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh
networks. The extensive programmability of the packet header allows for advanced packet filtering, which, in turn
enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be
corrupted by noise and interference, so it is important to know if the received data is free of errors. A cyclic
redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and
appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have
occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for
a simpler and cheaper microcontroller. The digital modem includes the TX modulator, which converts the TX data
bits into the corresponding stream of digital modulation values to be summed with the fractional input to the
sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A
Gaussian filter is implemented to support GFSK and 4GFSK, considerably reducing the energy in adjacent
channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to
other values.
5.2.1. Automatic Gain Control (AGC)
The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The
AGC occurs within a single bit or in less than 2 s. Peak detectors at the output of the LNA and PGA allow for
optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity performance.
5.2.2. Auto Frequency Correction (AFC)
Frequency mistuning caused by crystal inaccuracies can be compensated for by enabling the digital automatic
frequency control (AFC) in receive mode. There are two types of integrated frequency compensation: modem
frequency compensation, and AFC by adjusting the PLL frequency. With AFC disabled, the modem compensation
can correct for frequency offsets up to 0.25 times the IF bandwidth. When the AFC is enabled, the received signal
will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range of
frequency offsets up to 0.35 times the IF bandwidth. When AFC is enabled, the preamble length needs to be long
enough to settle the AFC. As shown in Table 12 on page 28, an additional byte of preamble is typically required to
settle the AFC.
30 Rev 1.2
Si4464/63/61/60
5.2.3. Image Rejection and Calibration
Since the receiver utilizes a low-IF architecture, the selectivity will be affected by the image frequency. The IF
frequency is 468.75 kHz (Fxtal/64), and the image frequency will be at 937.5 kHz below the RF frequency. The
native image rejection of the Si446x family is 35 dB. Image rejection calibration is available in the Si446x to
improve the image rejection to more than 55 dB. The calibration is initiated with the IRCAL API command. The
calibration uses an internal signal source, so no external signal generator is required. The initial calibration takes
250 ms, and periodic re-calibration takes 100 ms. Re-calibration should be initiated when the temperature has
changed more than 30 C.
5.2.4. Received Signal Strength Indicator
The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the
receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the
desired or undesired in-band signal power. There are two different methods for reading the RSSI value and several
different options for configuring the RSSI value that is returned. The fastest method for reading the RSSI is to
configure one of the four fast response registers (FRR) to return a latched RSSI value. The latched RSSI value is
measured once per packet and is latched at a configurable amount of time after RX mode is entered. The fast
response registers can be read in 16 SPI clock cycles with no requirement to wait for CTS. The RSSI value may
also be read out of the GET_MODEM_STATUS command. In this command, both the current RSSI and the latched
RSSI are available. The current RSSI value represents the signal strength at the instant in time the
GET_MODEM_STATUS command is processed and may be read multiple times per packet. Reading the RSSI in
the GET_MODEM_STATUS command takes longer than reading the RSSI out of the fast response register. After
the initial command, it will take 33 s for CTS to be set and then the four or five bytes of SPI clock cycles to read
out the respective current or latched RSSI values.
The RSSI configuration options are set in the MODEM_RSSI_CONTROL API property. The latched RSSI value
may be latched and stored based on the following events: preamble detection, sync detection, or a configurable
number of bit times measured after the start of RX mode (minimum of 4 bit times). The requirement for four bit
times is determined by the processing delay and settling through the modem and digital channel filter. In
MODEM_RSSI_CONTROL, the RSSI may be defined to update every bit period or to be averaged and updated
every four bit periods. If RSSI averaging over four bits is enabled, the latched RSSI value will be delayed to a
minimum of 7 bits after the start of RX mode to allow for the averaging. The latched RSSI values are cleared when
entering RX mode so they may be read after the packet is received or after dropping back to standby mode. If the
RSSI value has been cleared by the start of RX but not latched yet, a value of 0 will be returned if it is attempted to
be read.
The RSSI value read by the API could be translated to dBm by the following linear equation:
RSSI (in dBm) = (RSSI_value /2) RSSIcal
RSSIcal in the above formula depends on the matching network, modem settings, and external LNA gain (if
present). The RSSIcal value can be obtained by a simple calibration with a signal generator connected at the
antenna input. Without external LNA, the value of RSSIcal is around 130 30.
During packet reception, it may be useful to detect whether a secondary interfering signal (desired or undesired)
arrives. To detect this event, a feature for RSSI jump detection is available. If the RSSI level changes by a
programmable amount during the reception of a packet, an interrupt or GPIO can be configured to notify the host.
The level of RSSI increase or decrease (jump) is programmable through the MODEM_RSSI_JUMP_THRESH API
property. If an RSSI jump is detected, the modem may be programmed to automatically reset so that it may lock
onto the new stronger signal. The chip may also be configured to automatically reset the receiver upon jump
detection in order to acquire the new signal. The configuration and options for RSSI jump detection are
programmed in the MODEM_RSSI_CONTROL2 API property. By default, RSSI jump detection is not enabled.
Rev 1.2 31
Si4464/63/61/60
The RSSI values and curves may be offset by the MODEM_RSSI_COMP API property. The default value of 7h32
corresponds to no RSSI offset. Setting a value less than 7h32 corresponds to a negative offset, and a value higher
than 7h32 corresponds to a positive offset. The offset value is in 1 dB steps. For example, setting a value of 7h3A
corresponds to a positive offset of 8 dB.
Clear channel assessment (CCA) or RSSI threshold detection is also available. An RSSI threshold may be set in
the MODEM_RSSI_THRESH API property. If the RSSI value is above this threshold, an interrupt or GPIO may
notify the host. Both the latched version and asynchronous version of this threshold are available on any of the
GPIOs. Automatic fast hopping based on RSSI is available. See 5.3.1.2. Automatic RX Hopping and Hop Table.
5.3. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over the bands from 142175,
283350, 420525, and 8501050 MHz for the Si4460/61/63. The Si4464 offers frequency coverage in bands that
are not covered by Si4463/1/0. Using a synthesizer has many advantages; it provides flexibility in choosing data
rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in
the digital domain through the fractional divider, which results in very precise accuracy and control over the
transmit deviation. The frequency resolution in the 8501050 MHz band is 28.6 Hz with more resolution in the
other bands. The nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz
may be used. The modem configuration calculator in WDS will automatically account for the XTAL frequency being
used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed
by a configurable divider, which will divide the signal down to the desired output frequency band.
5.3.1. Synthesizer Frequency Control
The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will
automatically provide these settings, but the synthesizer equation is shown below for convenience. The APIs for
setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and
FREQ_CONTROL_FRAC0.
fc_frac- 2 freq_xo
RF_channel = fc_inte + -----------------
19
----------------------------- Hz
2 outdiv
Note: The fc_frac/219 value in the above formula has to be a number between 1 and 2.
Table 13. Output Divider (Outdiv) Values for the Si4460/61/63

Outdiv Lower (MHz) Upper (MHz)
24 142 175
12 284 350
8 420 525
4 850 1050
Table 14. Output Divider (Outdiv) for the Si4464

Outdiv Lower (MHz) Upper (MHz)
24 119 159
16 177 239
12 235 319
8 353 479
6 470 639
4 705 960
32 Rev 1.2
Si4464/63/61/60
5.3.1.1. EZ Frequency Programming
In applications that utilize multiple frequencies or channels, it may not be desirable to write four API registers each
time a frequency change is required. EZ frequency programming is provided so that only a single register write
(channel number) is required to change frequency. A base frequency is first set by first programming the integer
and fractional components of the synthesizer. This base frequency will correspond to channel 0. Next, a channel
step size is programmed into the FREQ_CONTROL_CHANNEL_STEP_SIZE_1 and
FREQ_CONTROL_CHANNEL_STEP_SIZE_0 API registers. The resulting frequency will be:
RF Frequency = Base Frequency + Channel Stepsi ze
The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for EZ
frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to
900 MHz with the INTE and FRAC API registers, and a CHANNEL number of 5 is programmed during the
START_TX command, the resulting frequency will be 905 MHz. If no CHANNEL argument is written as part of the
START_RX/TX command, it will default to the previous value. The initial value of CHANNEL is 0; so, if no
CHANNEL value is written, it will result in the programmed base frequency.
5.3.1.2. Automatic RX Hopping and Hop Table
The transceiver supports an automatic hopping feature that can be fully configured through the API. This is
intended for RX hopping where the device has to hop from channel to channel and look for packets. Once the
device is put into the RX state, it automatically starts hopping through the hop table if the feature is enabled.
The hop table can hold up to 64 entries and is maintained in firmware. Each entry is a channel number; so, the hop
table can hold up to 64 channels. The number of entries in the table is set by RX HOP TABLE_SIZE API. The
specified channels correspond to the EZ frequency programming method for programming the frequency. The
receiver starts at the base channel and hops in sequence from the top of the hop table to the bottom. The table will
wrap around to the base channel once it reaches the end of the table. An entry of 0xFF in the table indicates that
the entry should be skipped. The device will hop to the next non 0xFF entry.
There are three conditions that can be used to determine whether to continue hopping or to stay on a particular
channel. These conditions are:
RSSI threshold
Preamble timeout (invalid preamble pattern)
Sync word timeout (invalid or no sync word detected after preamble)
These conditions can be used individually, or they can be enabled all together by configuring the
RX_HOP_CONTROL API. However, the firmware will make a decision on whether or not to hop based on the first
condition that is met.
The RSSI that is monitored is the current RSSI value. This is compared to the threshold, and, if it is above the
threshold value, it will stay on the channel. If the RSSI is below the threshold, it will continue hopping. There is no
averaging of RSSI done during the automatic hopping from channel to channel. Since the preamble timeout and
the sync word timeout are features that require packet handling, the RSSI threshold is the only condition that can
be used if the user is in direct or RAW mode where packet handling features are not used.
Note that the RSSI threshold is not an absolute RSSI value; instead, it is a relative value and should be verified on
the bench to find an optimal threshold for the application.
The turnaround time from RX to RX on a different channel using this method is 115 s. The time spent in receive
mode will be determined by the configuration of the hop conditions. Manual RX hopping will have the fastest
turn-around time but will require more overhead and management by the host MCU.
The following are example steps for using Auto Hop:
1. Set the base frequency (inte + frac) and channel step size.
2. Define the number of entries in the hop table (RX_HOP_TABLE_SIZE).
3. Write the channels to the hop table (RX_HOP_TABLE_ENTRY_n)
4. Configure the hop condition and enable auto hopping- RSSI, preamble, or sync (RX_HOP_CONTROL).
5. Set preamble and sync parameters if enabled.
Rev 1.2 33
Si4464/63/61/60
6. Program the RSSI threshold property in the modem using MODEM_RSSI_THRESH.
7. Set the preamble threshold using PREAMBLE_CONFIG_STD_1.
8. Program the preamble timeout property using PREAMBLE_CONFIG_STD_2.
9. Set the sync detection parameters if enabled.
10. If needed, use GPIO_PIN_CFG to configure a GPIO to toggle on hop and hop table wrap.
11. Use the START_RX API with channel number set to the first valid entry in the hop table (i.e., the first non
0xFF entry).
12. Device should now be in auto hop mode.
5.3.1.3. Manual RX Hopping
The RX_HOP command provides the fastest method for hopping from RX to RX but it requires more overhead and
management by the host MCU. Using the RX_HOP command, the turn-around time is 75 s. The timing is faster
with this method than Start_RX or RX hopping because one of the calculations required for the synthesizer
calibrations is offloaded to the host and must be calculated/stored by the host, VCO_CNT0. For information about
using fast manual hopping, contact customer support.
5.4. Transmitter (TX)
The Si4464/63 contains an integrated +20 dBm transmitter or power amplifier that is capable of transmitting from
20 to +20 dBm. The output power steps are less than 0.25 dB within 6 dB of max power but become larger and
more non-linear close to minimum output power. The Si4464/63 PA is designed to provide the highest efficiency
and lowest current consumption possible. The Si4461 PA is capable of transmitting from 40 to +16 dBm. The
Si4461 PA can be optimized for either optimum current consumption (Class E) or for fine output power steps and
performance over voltage and temperature (switched-current). Switched-current matching will have fine output
power steps and more constant output power over VDD, but it will have higher current consumption than the
class-E matching. The class E will have the most efficient current consumption, but it will have more coarse output
power steps and variation across VDD. The Si4460 is designed to supply +10 dBm output power for less than
20 mA for applications that require operation from a single coin cell battery. The Si4460 can also operate with
either class-E or switched current matching and output up to +13 dBm Tx power. All PA options are single-ended to
allow for easy antenna matching and low BOM cost. Automatic ramp-up and ramp-down is automatically
performed to reduce unwanted spectral spreading.
Chips TXRAMP pin is disabled by default to save current in cases where on-chip PA will be able to drive the
antenna. In cases where on-chip PA will drive the external PA, and the external PA needs a ramping signal,
TXRAMP is the signal to use. To enable TXRAMP, set the API Property PA_MODE[7] = 1. TXRAMP will start to
ramp up, and ramp down at the SAME time as the internal on-chip PA ramps up/down.
The ramping speed is programmed by TC[3:0] in the PA_RAMP_EX API property, which has the following
characteristics:
TC Ramp Time (s)

0.0 2.0
1.0 2.1
2.0 2.2
3.0 2.4
4.0 2.6
5.0 2.8
6.0 3.1
7.0 3.4
8.0 3.7
34 Rev 1.2
Si4464/63/61/60
9.0 4.1
10.0 4.5
11.0 5.0
12.0 6.0
13.0 8.0
14.0 10.0
15.0 20.0
The ramping profile is close to a linear ramping profile with smoothed out corner when approaching Vhi and Vlo.
The TXRAMP pin can source up to 1 mA without voltage drooping. The TXRAMP pins sinking capability is
equivalent to a 10 k pull-down resistor.
Vhi = 3 V when Vdd > 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be
smaller also.
Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10uA need to be sunk into the chip, Vlo will be
10 A x 10k = 100 mV.
Number Command Summary

0x2200 PA_MODE Sets PA type.
0x2201 PA_PWR_LVL Adjust TX power in fine steps.
Adjust TX power in coarse steps
0x2202 PA_BIAS_CLKDUTY and optimizes for different
match configurations.
Changes the ramp up/down time
0x2203 PA_TC
of the PA.
5.4.1. Si4464/63: +20 dBm PA

The +20 dBm configuration utilizes a class-E matching configuration. Typical performance for the 900 MHz band
for output power steps, voltage, and temperature are shown in Figures 1012. The output power is changed in 128
steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer
to the PA Matching application note.
TX Power vs. PA_PWR_LVL

25
20
15
TX Power(dBm)
10
5
0
-5
-10
-15
-20
-25
-30
-35
0 10 20 30 40 50 60 70 80 90 100 110 120
PA_PWR_LVL
Figure 10. +20 dBm TX Power vs. PA_PWR_LVL
Rev 1.2 35
Si4464/63/61/60
TX Power vs. PA_PWR_LVL

25
20
15
TX Power(dBm)
10
5
0
-5
-10
-15
-20
-25
-30
-35
0 10 20 30 40 50 60 70 80 90 100 110 120
PA_PWR_LVL
Figure 11. +20 dBm TX Power vs. VDD
TX Power vs Temp
20.5
20
TX Power (dBm)
19.5
19
18.5
18
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (C)
Figure 12. +20 dBm TX Power vs. Temp
36 Rev 1.2
Si4464/63/61/60
5.4.2. Si4461 +16 dBm PA
The Si4461 PA can utilize different matches to optimize the performance for 16, 14, 13 dBm, or a lower power. A
class-E match is recommended for 16 dBm to maximize the efficiency and battery life. For 13 and 14 dBm, a
switched current match is recommended to provide optimal performance over VDD and temperature variation.
Typical performance for the 900 MHz band for output power steps, voltage, and temperature are shown in Figures
13 and 14. The output power is changed in 128 steps through the PA_PWR_LVL API. For detailed matching
values, BOM, and performance at other frequencies, refer to AN627: Si4460/61 Low-Power PA Matching.
Figure 13. +13 dBm TX Power vs. PA_PWR_LVL
Figure 14. +13 dBm TX Power vs. Supply Voltage (VDD)
Rev 1.2 37
Si4464/63/61/60
5.5. Crystal Oscillator
The Si446x includes an integrated crystal oscillator with a fast start-up time of less than 250 s. The design is
differential with the required crystal load capacitance integrated on-chip to minimize the number of external
components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is
designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30 MHz is used, the POWER_UP API
boot command must be modified. The WDS calculator crystal frequency field must also be changed to reflect the
frequency being used. The crystal load capacitance can be digitally programmed to accommodate crystals with
various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal
load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is
11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for
crystal production tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in
Figure 15.
Figure 15. Capacitor Bank Frequency Offset Characteristics

Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
A TCXO or external signal source can easily be used in place of a conventional XTAL and should be connected to
the XIN pin. The incoming clock signal is recommended to have a peak-to-peak swing in the range of 600 mV to
1.4 V and ac-coupled to the XIN pin. If the peak-to-peak swing of the TCXO exceeds 1.4 V peak-to-peak, then dc
coupling to the XIN pin should be used. The maximum allowed swing on XIN is 1.8 V peak-to-peak.
The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the
POWER_UP command should be invoked with the TCXO option whenever external drive is used.
38 Rev 1.2
Si4464/63/61/60
6. Data Handling and Packet Handler
6.1. RX and TX FIFOs
Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 16. Writing to
command Register 66h loads data into the TX FIFO, and reading from command Register 77h reads data from the
RX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the TX_FIFO_EMPTY
property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty threshold. If more data
is not loaded into the FIFO, the chip automatically exits the TX state after the PACKET_SENT interrupt occurs. The
RX FIFO has one programmable threshold, which is programmed by setting the RX_FIFO_FULL property. When
the incoming RX data crosses the Almost Full Threshold, an interrupt will be generated to the microcontroller via
the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. The RX Almost Full Threshold
indication implies that the host can read at least the threshold number of bytes from the RX FIFO at that time. Both
the TX and RX FIFOs may be cleared or reset with the FIFO_RESET command.
TX FIFO RX FIFO
RX FIFO Almost
Full Threshold
TX FIFO Almost
Empty Threshold
Figure 16. TX and RX FIFOs

6.2. Packet Handler
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. The usual
fields for network communication, such as preamble, synchronization word, headers, packet length, and CRC, can
be configured to be automatically added to the data payload. The fields needed for packet generation normally
change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload
in TX mode and automatically checking them in RX mode greatly reduces the amount of communication between
the microcontroller and Si446x. It also greatly reduces the required computational power of the microcontroller. The
general packet structure is shown in Figure 17. Any or all of the fields can be enabled and checked by the internal
packet handler.
Pkt Len gth or Data
Header or Data
C RC Field 1 (op t)
C RC Field 2 (op t)
C RC Field 3 (op t)
C RC Field 4 (op t)
C RC Field 5 (op t)
Sync Word
Field 3 (opt)
Field 4 (opt)
Field 5 (opt)
F ield 2 (o pt)
Field 1
Data
Data
Data
Preamble
1-255 Bytes 1-4 Bytes Con fig Config Con fig Con fig Con fig
0, 2, o r 4 0, 2, o r 4 0, 2, o r 4 0, 2, or 4 0, 2, or 4
Bytes Bytes B ytes Bytes Bytes
Figure 17. Packet Handler Structure
Rev 1.2 39
Si4464/63/61/60
The fields are highly programmable and can be used to check any kind of pattern in a packet structure. The
general functions of the packet handler include the following:
Detection/validation of Preamble quality in RX mode (PREAMBLE_VALID signal)
Detection of Sync word in RX mode (SYNC_OK signal)
Detection of valid packets in RX mode (PKT_VALID signal)
Detection of CRC errors in RX mode (CRC_ERR signal)
Data de-whitening and/or Manchester decoding (if enabled) in RX mode
Match/Header checking in RX mode
Storage of Data Field bytes into FIFO memory in RX mode
Construction of Preamble field in TX mode
Construction of Sync field in TX mode
Construction of Data Field from FIFO memory in TX mode
Construction of CRC field (if enabled) in TX mode
Data whitening and/or Manchester encoding (if enabled) in TX mode
For details on how to configure the packet handler, see AN626: Packet Handler Operation for Si446x RFICs.
40 Rev 1.2
Si4464/63/61/60
7. RX Modem Configuration
The Si446x can easily be configured for different data rate, deviation, frequency, etc. by using the WDS settings
calculator, which generates an initialization file for use by the host MCU.
8. Auxiliary Blocks
8.1. Wake-up Timer and 32 kHz Clock Source
The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The
wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL.
The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG
property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the
GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated
on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The microcontroller will then
need to verify the interrupt by reading the chip interrupt status either via GET_INT_STATUS or a fast response
register. The formula for calculating the Wake-Up Period is as follows:
WUT_R
42
WUT = WUT_M ----------------------------- ms
32 768
The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator
is automatically calibrated during the POWER_UP command and exits from the Shutdown state. To enable the
recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration
period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the
32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted accordingly. The calibration
needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD
results in a lower average current consumption. The 32 kHz XTAL accuracy is comprised of both the XTAL
parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging +
XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is
typically less than 10 ppm.
Rev 1.2 41
Si4464/63/61/60
Table 15. WUT Specific Commands and Properties

API Properties Description Requirements/Notes
GLOBAL_WUT_CONFIG GLOBAL WUT configuration WUT_ENEnable/disable wake up timer.
WUT_LBD_ENEnable/disable low battery detect
measurement on WUT interval.
WUT_LDC_EN:
0 = Disable low duty cycle operation.
1 = RX LDC operation
treated as wake up START_RX
WUT state is used
2 = TX LDC operation
treated as wakeup START_TX
WUT state is used
CAL_ENEnable calibration of the 32 kHz RC
oscillator
WUT_CAL_PERIOD[2:0]Sets calibration period.
GLOBAL_WUT_M_15_8 Sets HW WUT_M[15:8] WUT_MParameter to set the actual wakeup time.
See equation above.
GLOBAL_ WUT_M_7_0 Sets HW WUT_M[7:0] WUT_MParameter to set the actual wakeup time.
See equation above.
GLOBAL_WUT_R Sets WUT_R[4:0] WUT_RParameter to set the actual wakeup time.
Sets WUT_SLEEP to choose See equation above.
WUT state WUT_SLEEP:
0 = Go to ready state after WUT
1 = Go to sleep state after WUT
GLOBAL_WUT_LDC Sets FW internal WUT_LDC WUT_LDCParameter to set the actual wakeup
time. See equation in "8.2. Low Duty Cycle Mode
(Auto RX Wake-Up)" on page 43.
Table 16. WUT Related API Commands and Properties

Command/Property Description Requirements/Notes
WUT Interrupt Enable
CHIP_INT_STATUS_ENEnables chip status
INT_CTL_ENABLE Interrupt enable property
interrupt.
INT_CTL_CHIP_ENABLE Chip interrupt enable property WUT_ENEnables WUT interrupt.
32 kHz Clock Source Selection
CLK_32K_SEL[2:0]Configuring the source of
GLOBAL_CLK_CFG Clock configuration options WUT.
WUT Interrupt Output
Host can enable interrupt on GPIOx_MODE[5:0] = 14 and
GPIO_PIN_CFG NIRQ_MODE[5:0] = 39.
WUT expire
RX/TX Operation
START RX/TX when wake up
START_RX/TX START = 1.
timer expire
42 Rev 1.2
Si4464/63/61/60
8.2. Low Duty Cycle Mode (Auto RX Wake-Up)
The low duty cycle (LDC) mode is implemented to automatically wake-up the receiver to check if a valid signal is
available or to enable the transmitter to send a packet. It allows low average current polling operation by the Si446x
for which the wake-up timer (WUT) is used. RX and TX LDC operation must be set via the
GLOBAL_WUT_CONFIG property when setting up the WUT. The LDC wake-up period is determined by the
following formula:
WUT_R
42
LDC = WUT_LDC ----------------------------- ms
32 768
where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must be set in
conjunction with the LDC mode duration; for the relevant API properties, see the wake-up timer (WUT) section.
Figure 18. RX and TX LDC Sequences

The basic operation of RX LDC mode is shown in Figure 19. The receiver periodically wakes itself up to work on
RX_STATE during LDC mode duration. If a valid preamble is not detected, a receive error is detected, or an entire
packet is not received, the receiver returns to the WUT state (i.e., ready or sleep) at the end of LDC mode duration
and remains in that mode until the beginning of the next wake-up period. If a valid preamble or sync word is
detected, the receiver delays the LDC mode duration to receive the entire packet. If a packet is not received during
two LDC mode durations, the receiver returns to the WUT state at the last LDC mode duration until the beginning
of the next wake-up period.
Figure 19. Low Duty Cycle Mode for RX

In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If a
packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After
transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up time
expires.
Rev 1.2 43
Si4464/63/61/60
8.3. Temperature, Battery Voltage, and Auxiliary ADC
The Si446x family contains an integrated auxiliary ADC for measuring internal battery voltage, an internal
temperature sensor, or an external component over a GPIO. The ADC utilizes a SAR architecture and achieves
11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input
voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first
sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or
temp. The temperature sensor accuracy at 25 C is typically 2 C.
Command Stream
GET_ADC_READING 7 6 5 4 3 2 1 0
Command
CMD 0x14
ADC_EN 0 0 0 TEMPERATURE_EN BATTERY_VOLTAGE_EN ADC_GPIO_EN ADC_GPIO_PIN[1:0]
ADC_CFG UDTIME[3:0] GPIO_ATT[3:0]
Reply Stream
GET_ADC_READING Reply 7 6 5 4 3 2 1 0
CTS CTS[7:0]
GPIO_ADC GPIO_ADC[15:8]
GPIO_ADC GPIO_ADC[7:0]
BATTERY_ADC BATTERY_ADC[15:8]
BATTERY_ADC BATTERY_ADC[7:0]
TEMP_ADC TEMP_ADC[15:8]
TEMP_ADC TEMP_ADC[7:0]
RESERVED Reserved
RESERVED Reserved
Parameters
TEMPERATURE_EN
0 = Do not perform ADC conversion of temperature. This will read 0 value in reply TEMPERATURE.
1 = Perform ADC conversion of temperature. This results in TEMP_ADC.
Temp (C) = TEMP_ADC[15:0] x 568/2560 297
BATTERY_VOLTAGE_EN
0 = Don't do ADC conversion of battery voltage, will read 0 value in reply BATTERY_ADC
1 = Do ADC conversion of battery voltage, results in BATTERY_ADC. Vbatt = 3*BATTERY_ADC/1280
ADC_GPIO_EN
0 = Don't do ADC conversion on GPIO, will read 0 value in reply
1 = Do ADC conversion of GPIO, results in GPIO_ADC. Vgpio = GPIO_ADC/GPIO_ADC_DIV where
GPIO_ADC_DIV is defined by GPIO_ATT selection.
ADC_GPIO_PIN[1:0] - Select GPIOx pin. The pin must be set as input.
0 = Measure voltage of GPIO0
UDTIME[7:4] - ADC conversion Time = SYS_CLK / 12 / 2^(UDTIME + 1). Defaults to 0xC if ADC_CFG is 0.
44 Rev 1.2
Si4464/63/61/60
Selecting shorter conversion times will result in lower ADC resolution and longer times will result in higher ADC
resolution.
GPIO_ATT[3:0] - Sets attenuation of gpio input voltage when vgpio measured. Defaults to 0xC if ADC_CFG is 0.
0x0 = ADC range 0 to 0.8V. GPIO_ADC_DIV = 2560
0x4 = ADC range 0 to 1.6V. GPIO_ADC_DIV = 1280
0x8 = ADC range 0 to 2.4V. GPIO_ADC_DIV = 853.33
0x9 = ADC range 0 to 3.6V. GPIO_ADC_DIV = 426.66
0xC = ADC range 0 to 3.2V. GPIO_ADC_DIV = 640
Response
GPIO_ADC[15:0] - ADC value of voltage on GPIO
BATTERY_ADC[15:0] - ADC value of battery voltage
TEMP_ADC[15:0] - ADC value of temperature sensor voltage
RESERVED[7:0] - RESERVED FOR FUTURE USE
RESERVED[7:0] - RESERVED FOR FUTURE USE
8.4. Low Battery Detector

The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not
available unless the WUT is enabled, but the host MCU can manually check the battery voltage anytime with the
auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will
be compared against the threshold each time the WUT expires. The threshold for the LBD function is set in
GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of
1.5 V up to 3.05 V. The accuracy of the LBD is 3%. The LBD notification can be configured as an interrupt on the
nIRQ pin or enabled as a direct function on one of the GPIOs.
8.5. Antenna Diversity
To mitigate the problem of frequency-selective fading due to multipath propagation, some transceiver systems use
a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX
mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the
preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of
that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports
antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an
external SPDT RF switch (such as a PIN diode or GaAs switch) are available on the GPIOx pins. The operation of
these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The
antdiv[2:0] bits are found in the MODEM_ANT_DIV_CONTROL API property descriptions and enable the antenna
diversity mode. The GPIO pins are capable of sourcing up to 5 mA of current; so, it may be used directly to
forward-bias a PIN diode if desired. The antenna diversity algorithm will automatically toggle back and forth
between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna
selection is 8 bytes.
Rev 1.2 45
Si4464/63/61/60
9. Pin Descriptions: Si4464/63/61/60
GPIO3
GPIO2
XOUT
GND
XIN
SDN 1 20 19 18 17 16
RXp 2 15 nSEL
RXn 3 GND 14 SDI
TX 4 PAD 13 SDO
NC 5 12 SCLK
6 7 8 9 10 11 nIRQ
VDD
GPIO0
GPIO1
TXRamp
VDD
Pin Pin Name I/0 Description
Shutdown Input Pin.
0VDD V digital input. SDN should be = 0 in all modes except Shutdown mode.
1 SDN I
When SDN = 1, the chip will be completely shut down, and the contents of the
registers will be lost.
2 RXp I Differential RF Input Pins of the LNA.
3 RXn I See application schematic for example matching network.
Transmit Output Pin.

4 TX O The PA output is an open-drain connection, so the L-C match must supply
VDD (+3.3 VDC nominal) to this pin.
5 NC No Connect. Not connected internally to any circuitry.
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.

6 VDD VDD
The recommended VDD supply voltage is +3.3 V.
Programmable Bias Output with Ramp Capability for External FET PA.
7 TXRAMP O
See "5.4. Transmitter (TX)" on page 34.
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.

8 VDD VDD
The recommended VDD supply voltage is +3.3 V.
9 GPIO0 I/O General Purpose Digital I/O.

May be configured through the registers to perform various functions including:
10 GPIO1 I/O Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, TRSW, AntDiversity control, etc.
General Microcontroller Interrupt Status Output.

When the Si4463/61 exhibits any one of the interrupt events, the nIRQ pin will
11 nIRQ O be set low = 0. The Microcontroller can then determine the state of the inter-
rupt by reading the interrupt status. No external resistor pull-up is required, but
it may be desirable if multiple interrupt lines are connected.
46 Rev 1.2
Si4464/63/61/60
Pin Pin Name I/0 Description
Serial Clock Input.

12 SCLK I 0VDD V digital input. This pin provides the serial data clock function for the
4-line serial data bus. Data is clocked into the Si4463/61 on positive edge tran-
sitions.
0VDD V Digital Output.

13 SDO O
Provides a serial readback function of the internal control registers.
Serial Data Input.

14 SDI I 0VDD V digital input. This pin provides the serial data stream for the 4-line
serial data bus.
Serial Interface Select Input.

15 nSEL I 0VDD V digital input. This pin provides the Select/Enable function for the
4-line serial data bus.
Crystal Oscillator Output.

16 XOUT O Connect to an external 25 to 32 MHz crystal, or leave floating when driving
with an external source on XIN.
Crystal Oscillator Input.

17 XIN I
Connect to an external 25 to 32 MHz crystal, or connect to an external source.
18 GND GND Connect to PCB ground.
19 GPIO2 I/O General Purpose Digital I/O.

May be configured through the registers to perform various functions, including
20 GPIO3 I/O Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, TRSW, AntDiversity control, etc.
The exposed metal paddle on the bottom of the Si446x supplies the RF and cir-
cuit ground(s) for the entire chip. It is very important that a good solder connec-
PKG PADDLE_GND GND tion is made between this exposed metal paddle and the ground plane of the
PCB underlying the Si446x.
Rev 1.2 47
Si4464/63/61/60
10. Ordering Information
Part Number1,2 Description Package Type Operating

Temperature
QFN-20
Si4464-Bxx-FM ISM EZRadioPRO Transceiver 40 to 85 C
Pb-free
QFN-20
Pb-free
QFN-20
Pb-free
QFN-20
Pb-free
Notes:
1. Add an (R) at the end of the device part number to denote tape and reel option.
2. For Bxx, the first x indicates the ROM version, and the second x indicates the FW version in OTP.
48 Rev 1.2
Si4464/63/61/60
11. Package Outline: Si4464/63/61/60
Figure 20 illustrates the package details for the Si446x. Table 17 lists the values for the dimensions shown in the
illustration.
2X
bbb C A
D D2
B Pin 1 (Laser) e
20
20x L
E2
E
2X
aaa C
20x b
ccc C ddd C A B
A1
eee C
SEATING PLANE
C
A3
Figure 20. 20-Pin Quad Flat No-Lead (QFN)
Rev 1.2 49
Si4464/63/61/60
Table 17. Package Dimensions

Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
D 4.00 BSC
D2 2.45 2.60 2.75
e 0.50 BSC
E 4.00 BSC
E2 2.45 2.60 2.75
L 0.30 0.40 0.50
aaa 0.15
bbb 0.15
ccc 0.10
ddd 0.10
eee 0.08
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
Variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
50 Rev 1.2
Si4464/63/61/60
12. PCB Land Pattern: Si4464/63/61/60
Figure 21 illustrates the PCB land pattern details for the Si446x. Table 18 lists the values for the dimensions shown
in the illustration.
Figure 21. PCB Land Pattern
Rev 1.2 51
Si4464/63/61/60
Table 18. PCB Land Pattern Dimensions

Symbol Millimeters
Min Max
C1 3.90 4.00
C2 3.90 4.00
E 0.50 REF
X1 0.20 0.30
X2 2.55 2.65
Y1 0.65 0.75
Y2 2.55 2.65
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 m minimum, all
the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for the
perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for small body components.
52 Rev 1.2
Si4464/63/61/60
13. Top Marking
13.1. Si4464/63/61/60 Top Marking
13.2. Top Marking Explanation
Mark Method YAG Laser

44641B = Si4464 Rev 1B1
44631B = Si4463 Rev 1B1
Line 1 Marking Part Number
44611B = Si4461 Rev 1B1
44601B = Si4460 Rev 1B1
Line 2 Marking TTTTT = Internal Code Internal tracking code.2
YY = Year Assigned by the Assembly House. Corresponds to the last
Line 3 Marking significant digit of the year and workweek of the mold date.
WW = Workweek
Notes:
1. The first letter after the part number is part of the ROM revision. The last letter indicates the firmware
revision.
2. The first letter of this line is part of the ROM revision.
Rev 1.2 53
Si4464/63/61/60
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 1.0
Updated Table 3 on page 6.
Updated Figure 13 on page 37.
Replaced Table 12 on page 28.
Updated "11. Package Outline: Si4464/63/61/60" on
page 49.
Updated RX Mode Current in Table 1 on page 4.
Updated Synthesizer Frequency Range in Table 2
on page 5.
Updated RX Frequency Range and RX Sensitivity in
Table 3 on page 6.
Updated TX Frequency Range in Table 4 on page 9.
Updated Temperature Sensor Sensitivity in Table 5
on page 11.
Updated Drive Strength in Table 6 on page 12.
Updated Figure 1 and Figure 2 on page 16.
Updated "3.2. Fast Response Registers" on page
19.
Updated Figure 9 on page 29.
Updated "5.2.4. Received Signal Strength Indicator"
on page 31.
Updated "5.4. Transmitter (TX)" on page 34.
Updated "8.3. Temperature, Battery Voltage, and
Auxiliary ADC" on page 44.
Updated "9. Pin Descriptions: Si4464/63/61/60" on
page 46.
Updated "11. Package Outline: Si4464/63/61/60" on
page 49.
Updated all instances of frequency range for
Si4463/61/60 and Si4464, primarily in the electrical
specifications Tables.
Removed emissions and harmonics specifications
from the electrical specifications.
Updated Tables 13 and 14 to reflect frequency
coverage.
Updated sections 5.2.3 and 5.2.4.
Updated 13.1. Si4464/63/61/60 Top Marking.
Updated 9. Pin Descriptions: Si4464/63/61/60 for
pins 16 and 17.
54 Rev 1.2
Si4464/63/61/60
NOTES:
Rev 1.2 55
Si4464/63/61/60
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, ana-
log-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering
team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-
ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-
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S i 4 4 6 4 / 6 3 / 6 1/60

(G)FSK, 4(G)FSK, (G)MSK 75 dB blocking at 1 MHz

OOK Antenna diversity and T/R switch control

Rev 1.2 1/16 Copyright 2016 by Silicon Laboratories Si4464/63/62/61/60

GPIO3 GPIO2 XIN XOUT

VDD TXRAMP VDD GPIO0 GPIO1

Si4463 Major bands +20 dBm 169 MHz: 70 mA 10/13 mA

Si4461 Major bands +16 dBm +13 dBm: 29 mA 10/13 mA

Si4460 Major bands +13 dBm +10 dBm: 18 mA 10/13 mA

Table 2. Synthesizer AC Electrical Characteristics1

284 350 MHz

142 175 MHz

Synthesizer Frequency FSYN 705 960 MHz

177 319 MHz

119 159 MHz

Synthesizer Frequency FRES-960 8501050 MHz 28.6 Hz

FRES-350 283350 MHz 9.5 Hz

FRES-175 142175 MHz 4.7 Hz

Synthesizer Frequency FRES-960 705960 MHz 28.6 Hz

FRES-479 353479 MHz 14.3 Hz

FRES-319 235319 MHz 9.5 Hz

FRES-239 177239 MHz 7.1 Hz

FRES-159 119159 MHz 4.7 Hz

177 319 MHz

119 159 MHz

Table 4. Transmitter AC Electrical Characteristics1

420 525 MHz

142 175 MHz

705 960 MHz

353 639 MHz

119 159 MHz

(G)FSK Data Rate3,4 DRFSK 0.1 500 kbps

4(G)FSK Data Rate3,4 DR4FSK 0.2 1000 kbps

OOK Data Rate3,4 DROOK 0.1 120 kbps

f350 283350 MHz 500 kHz

f175 142175 MHz 250 kHz

FRES-350 283350 MHz 9.5 Hz

FRES-175 142175 MHz 4.7 Hz

Transmit Modulation Gaussian Filtering Bandwith Time

Table 5. Auxiliary Block Specifications1

Table 7. Absolute Maximum Ratings

Figure 1. Si4461 Direct-Tie Application Example

Figure 2. Si4463 Single Antenna with RF Switch Example

Table 8. Serial Interface Timing Parameters

tCH Clock high time 40

tCL Clock low time 40

tEN Output enable time 20

tDE Output disable time 50 SDO

tSS Select setup time 20 tEN tSW

tSH Select hold time 50 nSEL

tSW Select high period 80

SDI FW Command Param Byte 0 Param Byte n

Figure 3. SPI Write Command

Figure 4. SPI Read CommandCheck CTS Value

SDO Response Byte 0 Response Byte n

Figure 5. SPI Read CommandClock Out Read Data

Figure 6. State Machine Diagram

Table 9. Operating State Response Time and Current Consumption*

Figure 7. POR Timing Diagram