MC74F160A

SYNCHRONOUS PRESETTABLE MC74F162A

BCD DECADE COUNTER
The MC74F160A and MC74F162A are high-speed synchronous decade
counters operating in the BCD (8421) sequence. They are synchronously pre-
settable for application in programmable dividers and have two types of Count SYNCHRONOUS PRESETTABLE
Enable inputs plus a Terminal Count output for versatility in forming synchro- BCD DECADE COUNTER
nous multistage counters. The MC74F160A has an asynchronous Master Re-
set input that overrides all other inputs and forces the outputs LOW. The FAST SHOTTKY TTL
MC74F162A has a Synchronous Reset input that overrides counting and par-
allel loading and allows the outputs to be simultaneously reset on the rising
edge of the clock.
• Synchronous Counting and Loading
• High-Speed Synchronous Expansion J SUFFIX
• Typical Count Rate of 120 MHz CERAMIC
CASE 620-09
CONNECTION DIAGRAM 16
1
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9

N SUFFIX
PLASTIC
16 CASE 648-08
1

1 2 3 4 5 6 7 8
*R CP P0 P1 P2 P3 CEP GND D SUFFIX
SOIC
*MR for MC74F160A 16
1 CASE 751B-03
*SR for MC74F162A

FUNCTION TABLE
ORDERING INFORMATION
SR PE CET CEP ACTION ON THE RISING CLOCK EDGE ( )
MC74FXXXAJ Ceramic
L X X X Reset (Clear) MC74FXXXAN Plastic
MC74FXXXAD SOIC
H L X X Load (Pn º Qn)
H H H H Count (Increment)
H H L X No Change (Hold)
LOGIC SYMBOL
H H X L No Change (Hold)
H = HIGH Voltage Level; L = LOW Voltage Level; X = Don’t Care
9 3 4 5 6

PE P0 P1 P2 P3
7 CEP
STATE DIAGRAM
10 CET TC 15
0 1 2 3 4 2 CP
*R Q0 Q1 Q2 Q3
15 5
1 14 13 12 11
14 6

13 7 VCC = PIN 16
GND = PIN 8
12 11 10 9 8 *MR for MC74F160A
*SR for MC74F162A

FAST AND LS TTL DATA

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 MC74F160A • MC74F162A

LOGIC DIAGRAM

P0 P1 P2 P3
PE
MC74F160A MC74F162A

CEP
CET

MC74F162A
TC
ONLY

CP
CP CP

MC74F160A D CP D
ONLY CD Q Q
Q0 DETAIL A DETAIL A DETAIL A
Q0

DETAIL A
MR (MC74F160A)

SR (MC74F162A)
Q0 Q1 Q2 Q3

NOTE:
This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

FUNCTIONAL DESCRIPTION

The MC74F160A and MC74F162A count modulo-10 in the MR overrides all other inputs and asynchronously forces all
BCD (8421) sequence. From state 9 (HLLH) they increment outputs LOW. A LOW signal on SR overrides counting and
to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel loading and allows all outputs to go LOW on the next
parallel through a clock buffer. Thus, all changes of the Q out- rising edge of CP. A LOW signal on PE overrides counting and
puts (except due to Master Reset of the MC74F160A) occur allows information on the Parallel Data (Pn) inputs to be
as a result of, and synchronous with, the LOW-to-HIGH transi- loaded into the flip-flops on the next rising edge of CP. With
tion of the CP input signal. The circuits have four fundamental PE and MR (MC74F160A) or SR (MC74F162A) HIGH, CEP
modes of operation, in order of precedence: asynchronous re- and CET permit counting when both are HIGH. Conversely, a
set (MC74F160A), synchronous reset (MC74F162A), paral- LOW signal on either CEP or CET inhibits counting.
lel load, count-up and hold. Five control inputs — Master Re- The MC74F160A and MC74F162A use D-type edge-trig-
set (MR, MC74F160A), Synchronous Reset (SR, gered flip-flops and changing the SR, PE, CEP, and CET in-
MC74F162A), Parallel Enable (PE), Count Enable Parallel puts when the CP is in either state does not cause errors, pro-
(CEP) and Count Enable Trickle (CET) — determine the mode vided that the recommended setup and hold times, with
of operation, as shown in the Function Table. A LOW signal on respect to the rising edge of CP, are observed.

FAST AND LS TTL DATA

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 MC74F160A • MC74F162A

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 74 4.5 5.0 5.5 V
TA Operating Ambient Temperature Range 74 0 25 70 °C
IOH Output Current — High 74 –1.0 mA
IOL Output Current — Low 74 20 mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs

VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for
All Inputs

VIK Input Clamp Diode Voltage –1.2 V VCC = MIN, IIN = – 18 mA

VOH Output HIGH Voltage 74 2.5 3.4 V IOH = –1.0 mA VCC = 4.50 V
74 2.7 3.4 V IOH = –1.0 mA VCC = 4.75 V
VOL Output LOW Voltage 0.35 0.5 V IOL = 20 mA VCC = MIN
IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
Input LOW Current
IIL MR, Data, CEP, Clock –0.6 mA VCC = MAX, VIN = 0.5 V
PE, CET, SR –1.2
IOS Output Short Circuit Current (Note 2) –60 – 150 mA VCC = MAX, VOUT = 0 V
ICC Power Supply Current 37 55 mA VCC = MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

The Terminal Count (TC) output is HIGH when CET is HIGH MC74F162A decade counters, the TC output is fully decoded
and the counter is in state 9. To implement synchronous multi- and can only be HIGH in state 9. If a decade counter is preset
stage counters, the TC outputs can be used with the CEP and to an illegal state, or assumes an illegal state when power is
CET inputs in two different ways. Please refer to the applied, it will return to the normal sequence within two
MC74F568 data sheet. The TC output is subject to decoding counts, as shown in the State Diagram.
spikes due to internal race conditions and is therefore not rec- Logic Equations:
ommended for use as a clock or asynchronous reset for Count Enable = CEP • CET • PE
flip-flops, counters, or registers. In the MC74F160A and TC = Q0 • Q1 • Q2 • Q3 • CET

FAST AND LS TTL DATA

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 MC74F160A • MC74F162A

AC CHARACTERISTICS
74F 74F
TA = +25°C TA = 0°C to 70°C
VCC = +5.0 V VCC = 5.0 V ± 10%
CL = 50 pF CL = 50 pF
Symbol Parameter Min Max Min Max Unit
fmax Maximum Count Frequency 100 90 MHz
tPLH Propagation Delay, Count 3.5 7.5 3.5 8.5
tPHL CP to Qn (PE Input HIGH) 3.5 10 3.5 11 ns
tPLH Propagation Delay 3.5 8.5 3.5 9.5
tPHL CP to Qn (PE Input LOW) 4.0 8.5 4.0 9.5
tPLH Propagation Delay 5.0 14 5.0 15 ns
tPHL CP to TC 4.5 14 4.5 15
tPLH Propagation Delay 2.5 7.5 2.5 8.5 ns
tPHL CET to TC 2.5 7.5 2.5 8.5
tPHL Propagation Delay 5.5 12 5.5 13 ns
MR to Qn (MC74F160A)
tPHL Propagation Delay 4.5 10.5 4.5 11.5 ns
MR to TC (MC74F160A)

AC OPERATING REQUIREMENTS
74F 74F
TA = +25°C TA = 0°C to 70°C
VCC = +5.0 V VCC = 5.0 V ± 10%
CL = 50 pF CL = 50 pF
Symbol Parameter Min Max Min Max Unit
ts(H) Setup Time, HIGH or LOW 5.0 5.0
ts(L) Pn to CP 5.0 5.0 ns
th(H) Hold Time, HIGH or LOW 2.0 2.0
th(L) Pn to CP 2.0 2.0
ts(H) Setup Time, HIGH or LOW 11 11.5
ts(L) PE or SR to CP 8.5 9.5 ns
th(H) Hold Time, HIGH or LOW 2.0 2.0
th(L) PE or SR to CP 0 0
ts(H) Setup Time, HIGH or LOW 11 11.5
ts(L) CEP or CET to CP 5.0 5.0 ns
th(H) Hold Time, HIGH or LOW 0 0
tH(L) CEP or CET to CP 0 0
tw(H) Clock Pulse Width (Load) 5.0 5.0 ns
tw(L) HIGH or LOW 5.0 5.0
tw(H) Clock Pulse Width (Count) 4.0 4.0 ns
tw(L) HIGH or LOW 6.0 7.0
tw(L) MR Pulse Width, LOW 5.0 5.0
(MC74F160A) ns

trec Recovery Time, MR to CP (MC74F160A) 6.0 6.0

FAST AND LS TTL DATA

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