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Beginning FPGA Programming - Partie39

This document discusses sequential logic and 4-bit up counters in VHDL. It describes using arithmetic operators and type conversions in VHDL. It provides an example of a 4-bit up counter design using sequential and concurrent statements. It also provides a test bench example to test the 4-bit up counter design.

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ali alilou
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
35 views

Beginning FPGA Programming - Partie39

This document discusses sequential logic and 4-bit up counters in VHDL. It describes using arithmetic operators and type conversions in VHDL. It provides an example of a 4-bit up counter design using sequential and concurrent statements. It also provides a test bench example to test the 4-bit up counter design.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 10 ■ Sequential Logic: IF This, THEN That

Figure 10-8.  Signed and unsigned signal examples

10.1.3.2 Arithmetic Operation
The second is a new way to do adding. The reason for using the ieee.numeric_std package is that we can
directly using add (+), subtract (-), multiplication (*), and divide (/) arithmetic operators. In Listing 10-7, we
are using the adder (+) to increment the counter value, which is the same as the 4-bit full adder in Chapter
8 without the complicated full adder VHDL files. You only need to use one line of VHDL code. Another
good reason is that you can easily overload a signed or an unsigned value with an integer value. Figure 10-9
provides simple rules for signed and unsigned value overloading.

Figure 10-9.  VHDL ieee.numeric_std overloading examples

In the example in Listing 10-7, we use one overloading in the following code:

counter_reg <= counter_reg + 1;

On every rising edge of the clock where enable is equal to 1 (High) this overloading code will get run.
It means increment by one.

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Chapter 10 ■ Sequential Logic: IF This, THEN That

10.1.3.3 4-Bit Up Counter Simulation


Let’s run ModelSim to simulate this counter. You can follow these steps to do so:
1.
Create a new project (refer to Chapter 4)
2.
Create a new VHDL file in the Quartus, copy Listing 10-7, and save as
counter_4bit.vhd
3.
Set the new added file (counter_4bit.vhd) as Top-Level Entity (shortcut: Ctrl +
Shift + V)
4.
Start compilation (Shortcut: Ctrl + L)
5.
Click Tools ➤ Run Simulation Tool ➤ RTL Simulation from the Quartus Prime
Menu
6.
In ModelSim run the following script in the Transcript window
a. vsim work.counter_4bit
b. add wave -position insertpoint sim:/counter_4bit/*
c. force -freeze sim:/counter_4bit/CLOCK 1 0, 0 {50 ps} -r 100
d. force -freeze sim:/counter_4bit/RESET 0 0
e. force -freeze sim:/counter_4bit/ENABLE 0 0
f. run 25 ps
g. force -freeze sim:/counter_4bit/RESET 1 0
h. run 100 ps
i. force -freeze sim:/counter_4bit/RESET 0 0
j. run 100 ps
k. force -freeze sim:/counter_4bit/ENABLE 1 0
l. run 200 ps
m. force -freeze sim:/counter_4bit/ENABLE 0 0
n. run 100 ps
o. force -freeze sim:/counter_4bit/ENABLE 1 0
p. run 1600 ps

7.
After step 6 (a-p), the ModelSim Wave window should show Figure  10-10 as the
result. If both the COUNTER and counter_reg value did not show as Hexadecimal
and unsigned number, then right-click on the waveform signal name. It will pop
up a menu on the left-hand side ➤ Radix ➤ click the Radix you would like to
show (like COUNTER use hexadecimal and counter_reg uses unsigned).

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Chapter 10 ■ Sequential Logic: IF This, THEN That

Figure 10-10.  4-bit counter simulation result

10.1.3.4 Type Conversion Between Types


The third thing is using type conversion in the last line of the Listing 10-7. It is converting an unsigned type
(counter_reg) to std_logic_vector (COUNTER). VHDL depends on overloaded operators and conversions.
You need to use conversion when you go between the following types:
• signed & unsigned (1 bit) <=> std_logic
• signed & unsigned <=> std_logic_vector
• signed & unsigned <=> integer
• std_logic_vector <=> integer
There are two types of VHDL built-in conversion function in the ieee.numeric_std package: the
automatic type and conversion by typecasting.

10.1.3.4.1 Automatic Type Conversion


It only happens between std_logic (1 bit) and signed/unsigned (1 bit). Figure 10-11 shows an example.

Figure 10-11.  Example of automatic type conversion

10.1.3.4.2 Typecasting Conversion
You can use typecasting to convert equal-size arrays of unsigned/signed and std_logic_vector. Figure 10-12
shows an example.

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Chapter 10 ■ Sequential Logic: IF This, THEN That

Figure 10-12.  Example of typecasting conversion

10.1.3.5 Mixed with Sequential Statements and Concurrent Statement


Design
This 4-bit up counter example is mixed with sequential statements (the counter_p process) and the last type
conversion concurrent assignment statement. You can see a lot more of this kind of design in Chapter 11. It
is a very common way to develop sequential (synchronous) designs for FPGA. Figure 10-13 shows a block
diagram of it.

Figure 10-13.  The standard form of a sequential design

Most of the synchronous sequential designs use combinational logic and one or more flip-flops. It looks
like Figure 10-13. The sequential design has a set of inputs (Listing 10-7 has ENABLE and Reset as input) and
generates a set of outputs (Listing 10-7 has COUNTER).
The output values of flip-flops are defined as state (Listing 10-7). Figure 10-13 shows that the flip-flop
outputs (state) depend on the combination of input and current state of every clock (Listing 10-7 is the rising
edge of the CLOCK) such that the state changes from one to another (Listing 10-7 the counter value).
The output of the sequential design is a function of the current state and input. Listing 10-7 shows
that the output COUNTER only depends on the current state (counter_reg). Remember that the output of a
sequential design MUST depend on current state and it does not necessarily need to depend on input. The
green arrow in Figure 10-13 does not necessarily exist, if the outputs are only depend on inputs after one
clock cycle. This concept is important for Chapter 11, which covers Finite State Machines (FSM).

10.2 More Than Sequential Logic—Sequential Statements


The IF statement is not the only sequential statement in VHDL. In VHDL, WAIT and AFTER are sequential
statements too! You will only use them in test bench VHDL design. Test bench is a file for testing your actual
FPGA digital design. Test bench is NOT FPGA dependent. It doesn’t need to follow any rules from the FPGA
hardware. You can use the FULL set of VHDL code. WAIT and AFTER are part of the VHDL for test bench VHDL.

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Chapter 10 ■ Sequential Logic: IF This, THEN That

Let’s create a simple test bench VHDL file to test the 4-bit up counter design. Listing 10-8 shows the
test bench VHDL file. Please save this file as counter_4bit_vhd_tst.vht (.vht stand for VHDL test bench)
under the <counter 4-bit project folder>/simulation/modelsim and run “vcom -work work counter_4bit_
vhd_tst.vht” in ModelSim Transcript.

Listing 10-8.  4-Bit Counter Test bench VHDL Code


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY counter_4bit_vhd_tst IS
END counter_4bit_vhd_tst;
ARCHITECTURE counter_4bit_tb OF counter_4bit_vhd_tst IS

-- signals
SIGNAL CLOCK : STD_LOGIC := '1';
SIGNAL COUNTER : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ENABLE : STD_LOGIC;
SIGNAL RESET : STD_LOGIC;
COMPONENT counter_4bit
PORT (
CLOCK : IN STD_LOGIC;
COUNTER : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
ENABLE : IN STD_LOGIC;
RESET : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : counter_4bit
PORT MAP (
-- list connections between master ports and signals
CLOCK => CLOCK,
COUNTER => COUNTER,
ENABLE => ENABLE,
RESET => RESET
);

-- CLOCK --
CLOCK <= not CLOCK AFTER 50 ps;

reset_p : PROCESS
BEGIN
-- code that executes only once
RESET <= '0';
WAIT FOR 25 ps;
RESET <= '1';
WAIT FOR 100 ps;
RESET <= '0';
WAIT; -- RESET stay Low forever
END PROCESS reset_p;

enable_p : PROCESS

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