Document Information For:: 5339157TST 5339157TST

Document Information for: 5339157TST
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Name 5339157TST
Revision 1
State Release
ECO 2089615
Description Voltage Regulator Box
Originator 305003310_nobuhiro__yoshizawa
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2. 5339157TST_s1_r1.doc
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305006072_yong andy__wang Approved 08/26/2009 02:01:30 AM GMT
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Approved Document - 5339157TST_r1.pdf Page 1 of 19

GE Healthcare 5339157TST
REVISION: 1 TITLE: Voltage Regulator Box
PROJECT CODE: Signa SV Test Specification
MADE BY/DATE: T.Tsuchiya 17-AUG-2009 SHEET 1 OF 18
REVISION CONTROL INFORMATION
DOC REV: 1 ECR/ECO# 2089615 DATE: 17-AUG-2009

NAME SHEET NO. ACTION
Tomotoshi Tsuchiya ALL Created for initial release.

Table of Contents
1. Scope ............................................................................................................................................................................ 4
2. Referenced Documents................................................................................................................................................. 4
2.1 GEHC Documents............................................................................................................................................... 4
2.1.1 Voltage regulator Related Documents............................................................................................................ 4
2.1.2 Common GE Healthcare Documents ............................................................................................................. 4
3. Theory of Operation ...................................................................................................................................................... 4
4. Precautions ................................................................................................................................................................... 5
5. Test Requirements ........................................................................................................................................................ 5
5.1 Required Test Equipment ................................................................................................................................... 5
5.1.1 Power Supply Requirements for Regulator Box ............................................................................................. 5
5.1.2 Other Equipment............................................................................................................................................. 6
5.2 In-Process Tests ................................................................................................................................................. 6
5.2.1 Isolation verification between chassis and power/GND plane........................................................................ 6
5.2.2 Conduction Check for 10V_A power plane..................................................................................................... 6
5.3 Input Voltage Verification (Lower Input Condition).............................................................................................. 7
5.3.1 Input Voltage measurement/adjustment......................................................................................................... 7
5.3.2 INPUT_VOLTAGE_PRESENCE interface ..................................................................................................... 7
5.4 OUTPUT Voltage and current Verification (Lower input condition) .................................................................... 7
5.4.1 Output Voltage and Corresponding Current ................................................................................................... 7
5.4.2 OUTPUT_VOLTAGE_PRESENCE interface ................................................................................................. 8

5.4.3 REGULATED_POWER_GOOD interface ...................................................................................................... 9
5.4.4 Regulated Power cut off interface................................................................................................................... 9
5.4.5 Regulated Output Voltages with Load Interface (Lower Input Condition) .................................................... 10
5.5 Input Voltage Verification (Higher Input Condition)........................................................................................... 11
5.5.1 Input Voltage measurement/adjustment....................................................................................................... 11
5.5.2 INPUT_VOLTAGE_PRESENCE interface ................................................................................................... 11
5.6 Regulated OUTPUT Voltage and current Verification (Higher input condition) ................................................ 12
5.6.1 Regulated Output Voltages with Load Interface (Higher Input Condition).................................................... 12
5.7 Stress Testing ................................................................................................................................................... 13
5.8 DC Ripple Test .................................................................................................................................................. 14
6. Quality Requirements.................................................................................................................................................. 15
7. Final Assembly ............................................................................................................................................................ 16
8. Glossary ...................................................................................................................................................................... 16
9. Appendix...................................................................................................................................................................... 17
9.1 J1 Connector (Stacked 37 pin Sub-D Right Angle Sockt Connector)............................................................... 17
9.2 J2 Connector (Stacked 37 pin Sub-D Right Angle Plug Connector)................................................................. 18

List of Tables
Table 1: Power Supply Requirements.................................................................................................................................. 5

Table 2: Isolation between chassis and power/GND plane.................................................................................................. 6
Table 3: Conduction Check for 10V Power Plane ................................................................................................................ 6
Table 4: Input Voltage Test Points ....................................................................................................................................... 7
Table 5: INPUT_VOLTAGE_PRESENCE Interface............................................................................................................. 7
Table 6: Output Voltage Description for 8ch configuration................................................................................................... 8
Table 7: Output Voltage Description for 16ch configuration................................................................................................. 8
Table 8: OUTPUT_VOLTAGE_PRESENCE Interface......................................................................................................... 8
Table 9: REGULATED_POWER_GOOD Interface.............................................................................................................. 9
Table 10: REGULATED_POWER_GOOD signal Interface ................................................................................................. 9
Table 11: Reference voltage for POEWR_GOOD circuit ..................................................................................................... 9
Table 12: Regulated Power Cut Off Interface ...................................................................................................................... 9
Table 13: REGULATED_POWER_NOT_GOOD signal Interface...................................................................................... 10
Table 14: Regulated Output Voltage and Currents at 0% Load......................................................................................... 10
Table 15: Regulated Output Voltage and Currents at 100% Load for 8ch configuration ................................................... 10
Table 16: Regulated Output Voltage and Currents at 100% Load for 16ch configuration ................................................. 11
Table 17: Input Voltage Test Points ................................................................................................................................... 11
Table 18: INPUT_VOLTAGE_PRESENCE Interface......................................................................................................... 11
Table 19: Regulated Output Voltage and Currents at 0% Load......................................................................................... 12

Table 20: Regulated Output Voltage and Currents at 100% Load for 8ch configuration ................................................... 12
Table 21: Regulated Output Voltage and Currents at 100% Load for 16ch configuration ................................................. 13
Table 22: Output Voltage and Currents for Stress Testing ................................................................................................ 13
Table 23: Output DC Ripple Test Points ............................................................................................................................ 14
Table 24 Yield Parameters ................................................................................................................................................. 15
Table 25 Glossary .............................................................................................................................................................. 16
Table 26: J1 Connector ...................................................................................................................................................... 17
Table 27: J2 Connector ...................................................................................................................................................... 18

1. SCOPE
This document defines the test requirements for the Voltage Regulator Box Module. It identifies the goals of
functional tests.
The Voltage Regulator Box is located in the Scan Room on the side of the magnet assembly. The Voltage
Regulator Box is not backward compatible to any previous MR systems. It must be used in conjunction with the
Signa SV architecture.
2. REFERENCED DOCUMENTS
The following documents form a part of this specification to the extent specified herein. In the event of conflict
between documents referenced here and contents of this document, this document is considered a superseding
requirement. All reference documents are not included in this document.
2.1 GEHC DOCUMENTS

2.1.1 VOLTAGE REGULATOR RELATED DOCUMENTS

5334150SCH Voltage Regulator Assy Schematic
5334150ADW Voltage Regulator Assembly Drawing
5334150HDD Voltage Regulator Assy Hardware Design Document
5334150TST Voltage Regulator Assy Test Specification
5339157ADW Voltage Regulator Box Assembly Drawing
5325520SCH 16CH Mega Switch for 1.5T Schematic

5325520-3SCH 8CH Mega Switch for 1.5T Schematic
5325520HDD Mega Switch Hardware Design Document
5325520TST Mega Switch for 1.5T Test Specification
5250072SCH RRx Board Schematic

5250072HDD RRx Board Hardware Design Document
5250072-2HDD 8-Channel RRx Board Hardware Description Document
5300180SCH MNS Upconverter Board Schematic

5189655HDD MNS Upconverter module - 1.5T Hardware Description Document
2.1.2 COMMON GE HEALTHCARE DOCUMENTS

2204822GSP Standard Practice for Material Acceptance Documentation Methods
2152903TST General Specification for In-circuit Testing
2100268PRE Global Packaging Requirements
DOC0053537 Supplier Change Request
3. THEORY OF OPERATION
The Voltage Regulator Box’s main function is to receive four kinds of power from DC Power Supply in system
cabinet, then is to provide five kinds of regulated power to Mega Switch and RRx, and is to provide one kind of non-
regulated power to MNS up-converter via Mega Switch.
The Voltage Regulator Box monitors all voltages of regulated output power if output voltage is normal or abnormal.
If the regulated voltage is abnormal, the Voltage Regulator Box will shut the output down. Then the Voltage
Regulator Box indicates abnormal condition by sending TTL signal to Mega Switch, and by putting the LED (Light
Emitting Diode) off on the PWA.

4. PRECAUTIONS
When the Voltage Regulator Box is powered on, the seven FETs (Field-Effect Transistors) and the nine axial lead
type resistors, which are identified on the PWA as Q4, Q9-Q14, R9, R15, R23, R38, R53, R68, R88, R93 and R96,
will generate the heat in condition with the load.
The Voltage Regulator Box is thermal designed by both of natural air-cooling and thermal conduction to base metal
plate via PCB, thermal pad and metal enclosure of the Voltage Regulator Box.
The Voltage Regulator Box is designed to be mounted on the metal base plate wall. The metal base plate is
important, because the heat will be released to the plate. The base plate, which the Voltage Regulator Box will be
fixed during the functional test, should have enough thermal capacity. If needs, air cooling behind the base plate is
acceptable.
5. TEST REQUIREMENTS
Each 5334150, Voltage Regulator PWA must be functionally tested after being assembled (5339157 Voltage
Regulator Box), with the exception of the following parts on the assembly, which should not be installed until
functional test is completed and the Voltage Regulator Box has passed all required testing:
• Reg Box Outer Panel (5338415), including related eight screws
The sequence of the functional tests must follow the order of the section headings as listed in this document. The
individual test within a test section do not need to follow the order as listed. For example, Section 5.3.1 must
precede Section 5.3.2, which then must precede Section 5.4. However, the tests within Section 5.3.2 can be run
out of order – i.e.Test ID 5.3.2.005, then 5.3.2.015, then 5.3.2.010, and then 5.3.2.020.
5.1 REQUIRED TEST EQUIPMENT

5.1.1 POWER SUPPLY REQUIREMENTS FOR REGULATOR BOX
There shall be two DB37 connectors used to supply power to the Voltage Regulator Box. Connectors for being
supplied power on the Voltage Regulator Box are J1-1 and J1-2. Refer to “9. Appendix” for pin assignment of the
connectors.
Table 1 lists the nominal input voltages and corresponding current requirements needed to power the Voltage
Regulator Box up with full load*.
* ”full load” for the Voltage Regulator Box assumes one 16ch Mega Switch, one 16ch RRx and one MNS upconverter
8ch Mega Switch and 8ch RRx configuration are existed, their power consumption is lower than with “full load”.
But the Voltage Regulator Box is compatible both for 8ch and 16ch configurations with or without MNS upconverter.
So the rating of required power supply for this testing are below.
Voltage Supply Maximum Current Maximum Voltage Test Point on PWA

(V) (A) Ripple Tolerance (mVpp) (reference)
+10.0 ~ +11.0 0.1 ** 1% TP21
+7.35 ~ +9.50 16.0 1% TP22
+5.00 ~ +6.10 3.5 1% TP23
-8.90 ~ -7.35 0.1 1% TP24
Table 1: Power Supply Requirements
** Regarding Maximum current for +10.0~+11.0V, actual rated current is 1.0A. But this voltage is only passed through without any
voltage regulation circuit from input connectors to output connectors of the Regulator Box. So a test for this voltage line in this TST
is measurement of resistance between input and output, and check the LED’s function. The rated current of 0.1A is current only for
checking LED’s function.

5.1.2 OTHER EQUIPMENT
• Digital Multi-Meter (DMM)

• Oscilloscope
• The Voltage Regulator Box Test Fixture (dummy load: supplier design ownership)
5.2 IN-PROCESS TESTS

5.2.1 ISOLATION VERIFICATION BETWEEN CHASSIS AND POWER/GND PLANE
Before turning the Voltage Regulator Box on, verify that all isolation between the chassis and test point.
Expected resistance measurements are shown in the test table below. (see Table 2 below).
LSL USL
Test ID Test Point Description
(Mega ohms) (Mega ohms)
5.2.1.005 TP21 +10.0 ~ +11.0V power plane 1.0 N/A
5.2.1.010 TP22 +7.35 ~ +9.50V input plane 1.0 N/A
5.2.1.015 TP23 +5.00 ~ +6.10 input plane 1.0 N/A
5.2.1.020 TP24 -8.90 ~ -7.35 input plane 1.0 N/A

5.2.1.025 TP1 +6.85V_A output plane 1.0 N/A
5.2.1.030 TP2 +5.4V_A output plane 1.0 N/A
5.2.1.035 TP3 +5.4V_D output plane 1.0 N/A
5.2.1.040 TP4 +3.4V_D output plane 1.0 N/A
5.2.1.045 TP5 -6.85V_A output plane 1.0 N/A
5.2.1.050 TP7 +6.85V_A regulated power plane 1.0 N/A
5.2.1.055 TP19 +5.4V_A regulated power plane 1.0 N/A
5.2.1.060 TP16 +5.4V_D regulated power plane 1.0 N/A
5.2.1.065 TP9 +3.4V_D regulated power plane 1.0 N/A
5.2.1.070 TP18 Ground plane on PWA 1.0 N/A
Table 2: Isolation between chassis and power/GND plane

5.2.2 CONDUCTION CHECK FOR 10V_A POWER PLANE
+10.0V power is supplied from J1-1 and J1-2, then pass the power to J2-1 and J2-2 via 10V_A power plane.
Before turning the Voltage Regulator Box on, verify that all conduction between the following pins.
Expected resistance measurements are shown in the test table below. (see Table 3 below).
LSL USL
Test ID Pin #1 Pin #2 Description
(ohms) (ohms)
5.2.2.005 J1-1, pin 1 J2-1, pin 1 Conduction check between connectors 0.00 0.30
5.2.2.010 J1-2, pin 1 J2-2, pin 1 Conduction check between connectors 0.00 0.30
Table 3: Conduction Check for 10V Power Plane

5.3 INPUT VOLTAGE VERIFICATION (LOWER INPUT CONDITION)

5.3.1 INPUT VOLTAGE MEASUREMENT/ADJUSTMENT
Turn the Voltage Regulator Box on without load, then verify that all input voltage supplies are present on the
Voltage Regulator Box at test points. If need, adjust the input voltage. (see Table 4 below).
Test ID Name Test Point LSL Voltage (V) USL Voltage (V)
5.3.1.005 10V_A TP21 10.00 10.50
5.3.1.010 7V35_9V50 TP22 7.35 8.00
5.3.1.015 5V00_6V10 TP23 5.00 5.50
5.3.1.020 N7V35_N8V90 TP24 -8.00 -7.35
Table 4: Input Voltage Test Points
5.3.2 INPUT_VOLTAGE_PRESENCE INTERFACE
• Verify that all input voltages by checking their INPUT_VOLTAGE_PRESENCE LED. Assign a Pass rating if
the LED is lit in green for each INPUT_VOLTAGE_PRESENCE signal as indicated in Table 5 below
Test ID Description LED Expected Result

5.3.2.005 +10V ~ +11V Power ON DS12 Pass
5.3.2.010 +7.35V ~ +9.50v Power ON DS13 Pass
5.3.2.015 +5.00V ~ +6.10V Power ON DS14 Pass
5.3.2.020 -8.90V ~ -7.35V Power ON DS15 Pass
Table 5: INPUT_VOLTAGE_PRESENCE Interface
5.4 OUTPUT VOLTAGE AND CURRENT VERIFICATION (LOWER INPUT CONDITION)

5.4.1 OUTPUT VOLTAGE AND CORRESPONDING CURRENT
The Voltage Regulator Box provides power of various voltage levels to Mega Switch, RRx and MNS up-converter.
In addition Mega Switch and RRx have 16ch configuration and 8ch configuration.
Connectors for supplying power on the Voltage Regulator Box are J2-1 and J2-2. Refer to “9. Appendix” for pin
assignment of the connectors.

Table 6 below lists those output voltages and their corresponding rated current for 8ch configuration.
Table 7 below lists those output voltages and their corresponding rated current for 16ch configuration.
The table will be used for informational purposes later in this test document.
Typical Test Rated

Power Name Description LSL Voltage (V) USL Voltage (V)
Voltage Point Current
6.85V_A +6.85V Analog Power output (regulated) +6.85V TP1 6.50 7.20 4.5A
5.4V_D +5.4V Digital Power output (regulated) +5.4V TP3 5.10 5.70 3.0A
N6.85V_A -6.85V Analog Power output (regulated) -6.85V TP5 -7.20 -6.50 0.10A
Table 6: Output Voltage Description for 8ch configuration
Typical Test Rated

Power Name Description LSL Voltage (V) USL Voltage (V)
Voltage Point Current
N6.85V_A -6.85V Analog Power output (regulated) -6.85V TP5 -7.20 -6.50 0.10A
Table 7: Output Voltage Description for 16ch configuration
5.4.2 OUTPUT_VOLTAGE_PRESENCE INTERFACE
• Verify that all regulated and non-regulated output voltages by checking their
OUTPUT_VOLTAGE_PRESENCE LED. Assign a Pass rating if the LED is lit in green for each
OUTPUT_VOLTAGE_PRESENCE signal as indicated in Table 8 below

5.4.2.005 +10V Analog Power ON DS1 Pass
5.4.2.010 +6.85V Analog Power ON DS2 Pass
5.4.2.015 +5.4V Analog Power ON DS3 Pass
5.4.2.020 +5.4V Digital Power ON DS4 Pass
5.4.2.025 +3.4V Digital Power ON DS5 Pass
5.4.2.030 -6.85V Analog Power ON DS6 Pass
Table 8: OUTPUT_VOLTAGE_PRESENCE Interface

5.4.3 REGULATED_POWER_GOOD INTERFACE
• Verify that all regulated output power is good by checking their POWER_GOOD_SIGNAL LED. Assign a
Pass rating if the LED is lit in green for each POWER_GOOD signal as indicated in Table 9 below

5.4.3.005 +6.85V Analog Power GOOD DS7 Pass
5.4.3.010 +5.4V Analog Power GOOD DS8 Pass
5.4.3.015 +5.4V Digital Power GOOD DS9 Pass
5.4.3.020 +3.4V Digital Power GOOD DS10 Pass
5.4.3.025 -6.85V Analog Power GOOD DS11 Pass
Table 9: REGULATED_POWER_GOOD Interface
• Verify that REG_BOX_PG signal is TTL high level at pin19 both of J2-1 and J2-2 as indicated in Table 10
below
LSL Voltage USL Voltage

Test ID Signal Description
(V) (V)
5.4.3.030 REG_BOX_PG (J2-1, 19pin) Regulator Box Power GOOD 2.20 3.30
5.4.3.035 REG_BOX_PG (J2-2, 19pin) Regulator Box Power GOOD 2.20 3.30
Table 10: REGULATED_POWER_GOOD signal Interface
• Verify that 2.048V reference voltage listed in Table 11 below and record voltage level.
LSL Voltage USL Voltage

Test ID Voltage Name Test Point
(V) (V)
5.4.3.040 2.048V_Ref TP8 2.028 2.068
Table 11: Reference voltage for POEWR_GOOD circuit
5.4.4 REGULATED POWER CUT OFF INTERFACE

• Verify that each regulated output power is cut off by checking their POWER_GOOD_SIGNAL and
OUTPUT_VOLTAGE_PRESENCE LED while in condition as indicated in Table 12 below. Assign a Pass
rating if the LED is lit OFF while in condition as indicated in Table 12 below
Test ID Condition Description LED Expected Result

TP11 is connected to GND Simulating DS2 Pass
5.4.4.005
+6.85V Analog Power NOT GOOD DS7
5.4.4.010
+5.4V Analog Power NOT GOOD DS8
5.4.4.015
+5.4V Digital Power NOT GOOD DS9
5.4.4.020
+3.4V Digital Power NOT GOOD DS10
5.4.4.025
-6.85V Analog Power NOT GOOD
Table 12: Regulated Power Cut Off Interface
Note: Voltage of -6.85V Analog Power is monitored. But cut off function for output does NOT exist.
So DS6 keeps to be lit during Test ID 5.4.4.025.

• Verify that REG_BOX_PG signal is TTL low level at pin19 both of J2-1 and J2-2 in condition as indicated in
Table 13 below.
LSL USL
Test ID Signal Condition Description
Voltage (V) Voltage (V)
REG_BOX_PG TP11 is connected Simulating +6.85V Analog 0.00 0.40
5.4.4.030
(J2-1, 19pin) to GND Power NOT GOOD
REG_BOX_PG TP12 is connected Simulating +5.4V Analog 0.00 0.40
5.4.4.035
REG_BOX_PG TP13 is connected Simulating +5.4V Digital 0.00 0.40
5.4.4.040
REG_BOX_PG TP14 is connected Simulating +3.4V Digital 0.00 0.40
5.4.4.045
REG_BOX_PG TP15 is connected Simulating -6.85V Analog 0.00 0.40
5.4.4.050
Table 13: REGULATED_POWER_NOT_GOOD signal Interface
• Turn the Voltage Regulator Box off.

5.4.5 REGULATED OUTPUT VOLTAGES WITH LOAD INTERFACE (LOWER INPUT CONDITION)
• Connect a current load, then set 0% load condition on all the regulated output voltages listed in Table 14
below
• Turn the Voltage Regulator Box on, then record all output voltage levels and their corresponding currents.
Voltage Voltage Test LSL USL LSL USL

Test ID
Name Point Voltage (V) Voltage (V) Current (A) Current (A)
5.4.5.005.V TP1 6.50 7.20 -- --
6.85V_A
5.4.5.005.A -- -- 0.000 0.030
5.4.5.010.V TP2 5.10 5.70 -- --
5.4V_A
5.4.5.010.A -- -- 0.000 0.030
5.4.5.015.V TP3 5.10 5.70 -- --
5.4V_D
5.4.5.015.A -- -- 0.000 0.030
5.4.5.020.V TP4 3.20 3.60 -- --
3.4V_D
5.4.5.020.A -- -- 0.000 0.030

5.4.5.025.V TP5 -7.20 -6.50 -- --
N6.85V_A
5.4.5.025.A -- -- 0.000 0.030
Table 14: Regulated Output Voltage and Currents at 0% Load
• Set a 100% current load for 8ch configuration on all regulated the output voltages listed in Table 15 below
and record all output voltage levels and their corresponding currents.

Test ID
5.4.5.055.V TP1 6.50 7.20 -- --
6.85V_A
5.4.5.055.A -- -- 4.36 4.64
5.4.5.060.V TP2 5.10 5.70 -- --
5.4V_A
5.4.5.060.A -- -- 2.42 2.58
5.4.5.065.V TP3 5.10 5.70 -- --
5.4V_D
5.4.5.065.A -- -- 2.91 3.09
5.4.5.070.V TP4 3.20 3.60 -- --
3.4V_D
5.4.5.070.A -- -- 3.39 3.61
5.4.5.075.V TP5 -7.20 -6.50 -- --
N6.85V_A
5.4.5.075.A -- -- 0.090 0.110
Table 15: Regulated Output Voltage and Currents at 100% Load for 8ch configuration

• Set a 100% current load for 16ch configuration on all the regulated output voltages listed in Table 16 below

Test ID
5.4.5.105.V TP1 6.50 7.20 -- --
6.85V_A
5.4.5.105.A -- -- 7.76 8.24
5.4.5.110.V TP2 5.10 5.70 -- --
5.4V_A
5.4.5.110.A -- -- 4.85 5.15
5.4.5.115.V TP3 5.10 5.70 -- --
5.4V_D
5.4.5.115.A -- -- 2.91 3.09
5.4.5.120.V TP4 3.20 3.60 -- --
3.4V_D
5.4.5.120.A -- -- 3.39 3.61
5.4.5.125.V TP5 -7.20 -6.50 -- --
N6.85V_A
5.4.5.125.A -- -- 0.090 0.110
• Set a 0% current condition on all the regulated output voltages listed in Table 14 above.
5.5 INPUT VOLTAGE VERIFICATION (HIGHER INPUT CONDITION)

5.5.1 INPUT VOLTAGE MEASUREMENT/ADJUSTMENT
Verify that all input voltage supplies are present on the Voltage Regulator Box at test points.
If need, adjust the input voltage. (see Table 17 below).
Test ID Name Test Point LSL Voltage (V) USL Voltage (V)
5.5.1.005 10V_A TP21 10.50 11.00
5.5.1.010 7V35_9V50 TP22 8.85 9.50
5.5.1.015 5V00_6V10 TP23 5.60 6.10
5.5.1.020 N7V35_N8V90 TP24 -8.90 -8.25
Table 17: Input Voltage Test Points
5.5.2 INPUT_VOLTAGE_PRESENCE INTERFACE
• Verify that all input voltages by checking their INPUT_VOLTAGE_PRESENCE LED. Assign a Pass rating if
the LED is lit in green for each INPUT_VOLTAGE_PRESENCE signal as indicated in Table 18 below

5.5.2.005 +10V ~ +11V Power ON DS12 Pass
5.5.2.010 +7.35V ~ +9.50v Power ON DS13 Pass
5.5.2.015 +5.00V ~ +6.10V Power ON DS14 Pass
5.5.2.020 -8.90V ~ -7.35V Power ON DS15 Pass
Table 18: INPUT_VOLTAGE_PRESENCE Interface

5.6 REGULATED OUTPUT VOLTAGE AND CURRENT VERIFICATION (HIGHER INPUT

CONDITION)
5.6.1 REGULATED OUTPUT VOLTAGES WITH LOAD INTERFACE (HIGHER INPUT CONDITION)
• Set a 0% current load on all the regulated output voltages listed in Table 19 below and record all output
voltage levels and their corresponding currents.

Test ID
5.6.1.005.V TP1 6.50 7.20 -- --
6.85V_A
5.6.1.005.A -- -- 0.000 0.030
5.6.1.010.V TP2 5.10 5.70 -- --
5.4V_A
5.6.1.010.A -- -- 0.000 0.030
5.6.1.015.V TP3 5.10 5.70 -- --
5.4V_D
5.6.1.015.A -- -- 0.000 0.030
5.6.1.020.V TP4 3.20 3.60 -- --
3.4V_D
5.6.1.020.A -- -- 0.000 0.030
5.6.1.025.V TP5 -7.20 -6.50 -- --
N6.85V_A
5.6.1.025.A -- -- 0.000 0.030
Table 19: Regulated Output Voltage and Currents at 0% Load

Test ID
5.6.1.055.V TP1 6.50 7.20 -- --
6.85V_A
5.6.1.055.A -- -- 4.36 4.64
5.6.1.060.V TP2 5.10 5.70 -- --
5.4V_A
5.6.1.060.A -- -- 2.42 2.58
5.6.1.065.V TP3 5.10 5.70 -- --
5.4V_D
5.6.1.065.A -- -- 2.91 3.09
5.6.1.070.V TP4 3.20 3.60 -- --
3.4V_D
5.6.1.070.A -- -- 3.39 3.61
5.6.1.075.V TP5 -7.20 -6.50 -- --

N6.85V_A
5.6.1.075.A -- -- 0.090 0.110


Test ID
5.6.1.105.V TP1 6.50 7.20 -- --
6.85V_A
5.6.1.105.A -- -- 7.76 8.24
5.6.1.110.V TP2 5.10 5.70 -- --
5.4V_A
5.6.1.110.A -- -- 4.85 5.15
5.6.1.115.V TP3 5.10 5.70 -- --
5.4V_D
5.6.1.115.A -- -- 2.91 3.09
5.6.1.120.V TP4 3.20 3.60 -- --
3.4V_D
5.6.1.120.A -- -- 3.39 3.61
5.6.1.125.V TP5 -7.20 -6.50 -- --
N6.85V_A
5.6.1.125.A -- -- 0.090 0.110
• Turn the Voltage Regulator Box off.

5.7 STRESS TESTING
• Wait 30 minutes at least after turning the Voltage Regulator Box off.
• Turn the Voltage Regulator Box on, then set a 100% current load for 16ch configuration on all the regulated
output voltages listed in Table 22 below and record all output voltage levels and their corresponding
currents.
• For 60 minutes, log voltage and current levels every ten minutes.
• In table below, XX = Minute 010 to Minute 060
Voltage LSL USL LSL USL

Test ID Voltage Name
Test Point Voltage (V) Voltage (V) Current (A) Current (A)
5.7.0.1XX.V TP1 6.50 7.20 -- --
6.85V_A
5.7.0.1XX.A -- -- 7.76 8.24
5.7.0.2XX.V TP2 5.10 5.70 -- --
5.4V_A
5.7.0.2XX.A -- -- 4.85 5.15
5.7.0.3XX.V TP3 5.10 5.70 -- --
5.4V_D
5.7.0.3XX.A -- -- 2.91 3.09
5.7.0.4XX.V TP4 3.20 3.60 -- --
3.4V_D
5.7.0.4XX.A -- -- 3.39 3.61
5.7.0.5XX.V TP5 -7.20 -6.50 -- --
N6.85V_A
5.7.0.5XX.A -- -- 0.090 0.110
Table 22: Output Voltage and Currents for Stress Testing

5.8 DC RIPPLE TEST

The Voltage Regulator Box outputs several DC voltages to power up Mega Switch, RRx and MNS up-converter.
Those regulated DC voltages must have a peak-to-peak voltage ripple that does not exceed 1% or 50mV of the
regulated voltage.
• Set a 100% current load for 16ch configuration on all the regulated output voltages.
• Observe the output DC voltage and measure the DC ripple using the oscilloscope.
Ripple LSL Output DC USL Output DC

TEST ID Voltage Name
Test Point Ripple (mV) Ripple (mV)
5.8.0.005 6.85V_A TP1 0.0 68.5
5.8.0.010 5.4V_A TP2 0.0 54.0
5.8.0.015 5.4V_D TP3 0.0 54.0
5.8.0.020 3.4V_D TP4 0.0 50.0
5.8.0.025 N6.85V_A TP5 0.0 68.5
5.8.0.030 2.048V_Ref TP8 0.0 50.0
Table 23: Output DC Ripple Test Points
• Turn the Voltage Regulator Box off

• Disconnect a current load on all the regulated output.

6. QUALITY REQUIREMENTS
The manufacturer is responsible to provide product within specification limits set forth by this document and to
maintain control of their manufacturing processes. This control maintenance will be documented with
manufacturer-provided data. This data will aid both the manufacturer and GEHC in understanding quality risks,
product cost drivers, product delivery probabilities, and product yields.
Discrete and continuous data for all tests required in this document shall be collected and retained by the
manufacturer per the PMQR until GEHC notifies the manufacturer that the product life has ended and/or GEHC
requests the records. This shall include any pass/fail decisions made on individual tests and on the test as a
whole. GEHC shall have access to all test and repair data upon request.
The following yield parameters are to be recorded for every test lot. All failures encountered during the first test
opportunity must be included in FPY, including but not limited to operator errors, test equipment errors, test errors
during debug and intermittent failures.
Description Required Target

Functional Test 1st Pass Yield (FPY) > 90%
Table 24 Yield Parameters

Yield parameters which fall below the requirements shall require the manufacturer to implement a written corrective
action plan to raise the yield to the requirement. The manufacturer is expected to drive up the functional test yields
to the required targets by improving the in-circuit or other prior test coverage.
Out Of Box (OOB) failures will require the manufacturer to perform a root cause analysis on the part and put in
place a corrective action plan. The manufacturer will work with the GEHC team to eliminate any and all OOB and
infant failures of their product.
The manufacturer shall initially qualify each test process as acceptable before using to test production units.
Production units may be used in the qualification process. Use the following sequence for qualification. First, the
manufacturer shall demonstrate 100% test coverage against the requirements specified in this document.
Exceptions to ICT coverage may be accepted without deviation at the discretion of GEHC, provided there is
documented rationale for each exception made. Any exception that has not been accepted by GEHC must have
corrective actions taken and reported back to GEHC.
Second, the manufacturer shall perform a gage R&R study on a minimum of 5 units run 3 times each. All
parameters in this document shall require less than 10% GR&R to be acceptable. Parameters above 10% may be
accepted without deviation at the discretion of GEHC, provided there is documented rationale for each exception
made. Any parameter above 10% GR&R that has not been accepted by GEHC must have corrective actions taken
and reported back to GEHC. The GR&R study must then be repeated on the failing parameters to prove they are
below 10% GR&R. Discrete parameters must give the same result on all runs to be accepted. ICT may be run as
a discrete test per 2152903TST.
Third, the manufacturer shall perform a capability study on a minimum of 5 units. This may be accomplished using
Scorecard Template 2222300TDR. Capability will be deemed acceptable if all continuous test parameters have a
Zst>3.5 or Cpk>1.17. Exceptions to capability goals may be accepted without deviation at the discretion of GEHC,
provided there is documented rationale for each exception made. Passing product may be shipped after the initial
test qualification, but any exception that has not been accepted by GEHC must have corrective actions taken and
reported back to GEHC.

7. FINAL ASSEMBLY
After the Voltage Regulator Box passes all functional tests, all remaining parts must be installed for the UUT.
8. GLOSSARY
Term Definition
ADW Assembly Drawing
AOI Automated Optical Inspection
AXI Automated X-ray Inspection
FET Field-Effect Transistors
FP Flying Probe
FPY First Pass Yield
GE General Electric company
GEHC GE Healthcare
GR&R Gage Repeatability and Reproducibility
HDD Hardware Description Document
ICT In Circuit Test

LED Light Emitting Diode
LSL Lower Specification Limit
MR Magnetic Resonance
OOB Out Of Box
PMQR Purchased Material Quality Requirements
PCB Printed Circuit Board
PWA Printed Wiring Assembly
RRx Remote Receiver Board
SV Super Value
TST Test Specification
USL Upper Specification Limit
UUT Unit Under Test
Table 25 Glossary

9. APPENDIX
9.1 J1 CONNECTOR (STACKED 37 PIN SUB-D RIGHT ANGLE SOCKT CONNECTOR)
J1 is a stacked sub-D connector. The pin assignments of top and bottom connectors are completely the same to
each other to avoid the hazard in case of wrong attachment. In the table below, prefix of “T” means “Top”, prefix
of “B” means “Bottom”. On the Box chassis the top connector is printed as J1-1, the bottom connector is printed
as J1-2
Pin # Mnemonic I/O Description Pin # Mnemonic I/O Description

T1 10V_A I +10V Analog T20 AGND Analog Ground
T2 7V35_9V50_IN I +7.35V T21 AGND Analog Ground

T15 N7V35_N8V90 I -7.35V T34 AGND Analog Ground
T19 No Connection
B1 10V_A I +10V Analog B20 AGND Analog Ground
B2 7V35_9V50_IN I +7.35V B21 AGND Analog Ground

B15 N7V35_N8V90 I -7.35V B34 AGND Analog Ground
B19 No Connection
Table 26: J1 Connector

9.2 J2 CONNECTOR (STACKED 37 PIN SUB-D RIGHT ANGLE PLUG CONNECTOR)

J2 is a stacked sub-D connector. The pin assignments of top and bottom connectors are completely the same to
each other to avoid the hazard in case of wrong attachment. In the table below, prefix of “T” means “Top”, prefix
of “B” means “Bottom”. On the Box chassis the top connector is printed as J2-1, the bottom connector is printed
as J2-2.

T1 10V_A O +10V Analog T20 AGND Analog Ground
T2 6V85_A O +6.85V Analog T21 AGND Analog Ground
T8 N6V85_A O - 6.85V Analog T27 AGND Analog Ground

T13 5V4_D O +5.4V Digital T32 AGND Analog Ground
T19 RegBox_PG O Regulator Box
Power Good
B1 10V_A O +10V Analog B20 AGND Analog Ground
B2 6V85_A O +6.85V Analog B21 AGND Analog Ground

B8 N6V85_A O - 6.85V Analog B27 AGND Analog Ground
B13 5V4_D O +5.4V Digital B32 AGND Analog Ground
B19 RegBox_PG O Regulator Box
Power Good
Table 27: J2 Connector

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Type Drawing Print

Person Action Date and Time

This page is generated automatically by the GEHC MyWorkshop System.

Approved Document - 5339157TST_r1.pdf Page 1 of 19

REVISION CONTROL INFORMATION

DOC REV: 1 ECR/ECO# 2089615 DATE: 17-AUG-2009

Approved Document - 5339157TST_r1.pdf Page 2 of 19

5.4.2 OUTPUT_VOLTAGE_PRESENCE interface ................................................................................................. 8

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Table 1: Power Supply Requirements.................................................................................................................................. 5

Table 19: Regulated Output Voltage and Currents at 0% Load......................................................................................... 12

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2.1 GEHC DOCUMENTS

2.1.1 VOLTAGE REGULATOR RELATED DOCUMENTS

5325520SCH 16CH Mega Switch for 1.5T Schematic

5250072SCH RRx Board Schematic

5300180SCH MNS Upconverter Board Schematic

2.1.2 COMMON GE HEALTHCARE DOCUMENTS

Approved Document - 5339157TST_r1.pdf Page 5 of 19

• Reg Box Outer Panel (5338415), including related eight screws

5.1 REQUIRED TEST EQUIPMENT

Voltage Supply Maximum Current Maximum Voltage Test Point on PWA

Approved Document - 5339157TST_r1.pdf Page 6 of 19

5.1.2 OTHER EQUIPMENT

• Digital Multi-Meter (DMM)

5.2 IN-PROCESS TESTS

5.2.1.020 TP24 -8.90 ~ -7.35 input plane 1.0 N/A

Table 2: Isolation between chassis and power/GND plane

5.2.2 CONDUCTION CHECK FOR 10V_A POWER PLANE

Table 3: Conduction Check for 10V Power Plane

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5.3 INPUT VOLTAGE VERIFICATION (LOWER INPUT CONDITION)

5.3.2 INPUT_VOLTAGE_PRESENCE INTERFACE

Test ID Description LED Expected Result

5.4 OUTPUT VOLTAGE AND CURRENT VERIFICATION (LOWER INPUT CONDITION)

Approved Document - 5339157TST_r1.pdf Page 8 of 19

Typical Test Rated

Table 6: Output Voltage Description for 8ch configuration

Typical Test Rated

Table 7: Output Voltage Description for 16ch configuration

5.4.2 OUTPUT_VOLTAGE_PRESENCE INTERFACE

Test ID Description LED Expected Result

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5.4.3 REGULATED_POWER_GOOD INTERFACE

Test ID Description LED Expected Result

LSL Voltage USL Voltage

LSL Voltage USL Voltage

5.4.4 REGULATED POWER CUT OFF INTERFACE

Test ID Condition Description LED Expected Result

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• Turn the Voltage Regulator Box off.

Voltage Voltage Test LSL USL LSL USL

5.4.5.020.A -- -- 0.000 0.030

Voltage Voltage Test LSL USL LSL USL

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Voltage Voltage Test LSL USL LSL USL

5.5 INPUT VOLTAGE VERIFICATION (HIGHER INPUT CONDITION)

Table 17: Input Voltage Test Points

5.5.2 INPUT_VOLTAGE_PRESENCE INTERFACE

Test ID Description LED Expected Result

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