Data Sheet: VT1705 High Definition Audio Codec

Data Sheet
VT1705
High Definition Audio Codec
June 11, 2009

Revision 1.1
Free Datasheet http://www.datasheet4u.com/

Data Sheet i
VT1705 High Definition Audio Codec
Revision History
Rev Date Initial Note

1.0 Mar. 26, 09 TL Initial external release
1.1 Jun. 11, 09 TL Updated descriptions, changed Karaoke Mode and Dynamic
Range Control as optional software features in Section 1 Product
Features
Updated signal descriptions of Pin 14 and Pin 15 in Section 6.2
Corrected register descriptions in Section 8.3.1 Get Parameter
Verb (Verb ID = F00h), 8.6.1 Get Parameter Verb (Verb ID =
F00h), 8.6.6 Amplifier Gain/Mute Verbs (Verb ID = Bh & 3h),
8.10.6 Right Channel Sense (Verb ID = F09h & 709h), 8.10.7 Pin
Widget Configuration Default Verbs (Verb ID = F1Ch &
71Ch-71Fh), 8.11.1 Get Parameter Verb (Verb ID = F00h),
8.17.3 Power State Verbs (Verb ID = F05h & 705h), 8.18.3
Power State Verbs (Verb ID = F05h & 705h), 8.17.4 Pin Widget
Control Verbs (Verb ID = F07h & 707h), and 8.18.4 Pin Widget
Control Verbs (Verb ID = F07h & 707h)
Updated the following Analog Performance Characteristics in
Section 10 Electrical Specification:
− Removed Digital S/N, and added Dynamic Range (-60
dB Full Scale, A-Weight)
− Frequency Response and Transition Band of ADC / DAC
Converters
Updated the description of green symbol in Section 11
Mechanical Specification
Corrected typos throughout the document

Data Sheet ii
Table of Contents
Revision History ........................................................................................................................ i

Table of Contents ..................................................................................................................... ii
List of Figures..........................................................................................................................iii
List of Tables ...........................................................................................................................iii
1 Product Features ................................................................................................................... 1
1.1 Hardware Features ........................................................................................................ 1
1.2 Software Features ......................................................................................................... 2
2 Overview.............................................................................................................................. 3
3 Functional Block Diagram ....................................................................................................... 4
4 Pinout .................................................................................................................................. 5
5 Pin List................................................................................................................................. 6
6 Pin Description...................................................................................................................... 7
6.1 Digital I/O Pins ............................................................................................................. 7
6.2 Analog I/O Pins ............................................................................................................ 7
6.3 Power and Ground ........................................................................................................ 8
6.4 NC Pins (Pins with No Connection) .................................................................................. 8
7 High Definition Audio Link Protocol .......................................................................................... 9
7.1 Link Signaling............................................................................................................... 9
7.2 Signal Definitions .......................................................................................................... 9
7.3 Signaling Topology ...................................................................................................... 11
7.4 Frame Composition ..................................................................................................... 11
7.5 Output Frame ............................................................................................................. 13
7.6 Input Frame ............................................................................................................... 14
7.7 Reset and Initialization ................................................................................................ 15
7.8 Handling Stream Independent Sample Rates .................................................................. 19
7.9 Power Management ..................................................................................................... 20
7.10 Unsolicited Response Behavior Description ................................................................... 20
8 Widget Description .............................................................................................................. 21
8.1 Node ID List ............................................................................................................... 21
8.2 Root Node (Node ID = 00) ........................................................................................... 22
8.3 Audio Function Group (Node ID = 01) ........................................................................... 23
8.4 Audio Analog Output Converter Widget (Node ID = 10h, 11h, 25h) ................................... 27
8.5 Audio Digital Output Converter (S/PDIF TX) Widget (Node ID = 12h, 15h) ......................... 31
8.6 Audio Analog Input Converter Widget (Node ID = 13h, 14h) ............................................ 35
8.7 Mixer Widget (Node ID = 16h)...................................................................................... 40
8.8 Selector Widget SW0 (Node ID = 17h) .......................................................................... 43
8.9 Selector Widget SW1-SW2 (Node ID = 18h, 27h) ........................................................... 45
8.10 Pin Widget PW0 (Node ID = 19h) ................................................................................ 48
8.11 Pin Widget PW3 (Node ID =1Ch)................................................................................. 52
8.12 Pin Widget PW4 (Node ID =1Dh)................................................................................. 57
8.13 Pin Widget PW7 (Node ID =23h) ................................................................................. 63
8.14 Pin Widget PW1, PW2 (Node ID = 1Ah, 1Bh) ................................................................ 67
8.15 Pin Widget PW5 (Node ID = 1Eh) ................................................................................ 73
8.16 Pin Widget PW8 (Node ID = 1Fh) CD Analog Input ........................................................ 79
8.17 Pin Widget PW9 (Node ID = 20h ) S/PDIF TX Pin .......................................................... 82
8.18 Pin Widget PW10 (Node ID = 21h ) HDMI Audio Output Pin ............................................ 85
9 Functional Descriptions ........................................................................................................ 88
9.1 Clock Control.............................................................................................................. 88
9.2 Interpolation / Decimation ........................................................................................... 88
9.3 HPF for ADC DC Removal ............................................................................................. 88
9.4 Audio Jack Detection Circuits........................................................................................ 89
9.5 Internal Loop-back and Peak Detection for Low Cost Production Test ................................. 89
9.6 GPIO Implementation .................................................................................................. 89
10 Electrical Specification........................................................................................................ 90
11 Mechanical Specification ..................................................................................................... 92
12 Application Circuit.............................................................................................................. 93

Data Sheet iii
List of Figures
Figure 1 – VT1705 Functional Block Diagram ............................................................................... 4

Figure 2 – VT1705 Pin Diagram for LQFP-48 (Top View) ................................................................ 5
Figure 3 – High Definition Audio Link Conceptual View .................................................................. 9
Figure 4 – Bit Timing Diagram ................................................................................................. 10
Figure 5 – SYNC and SDO Timing Relative to BITCLK .................................................................. 10
Figure 6 – SDI Timing Relative to BITCLK.................................................................................. 10
Figure 7 – Basic High Definition Audio System ........................................................................... 11
Figure 8 – Frames Demarcation ............................................................................................... 11
Figure 9 – Frame Composition ................................................................................................. 12
Figure 10 – Outbound Stream Tag Format and Transmission ........................................................ 13
Figure 11 – Outbound Frame with Null Field .............................................................................. 13
Figure 12 – Inbound Tag Format and Transmission ..................................................................... 14
Figure 13 – Inbound Frame with No Null Field............................................................................ 14
Figure 14 – Link Reset Entry Sequence ..................................................................................... 15
Figure 15 – Link Reset Exit Sequence ....................................................................................... 15
Figure 16 – Codec Initialization Sequence ................................................................................. 16
Figure 17 – Connect and Turnaround Frames ............................................................................. 17
Figure 18 – Address Frame...................................................................................................... 18
Figure 19 – Jack Detect Circuit ................................................................................................ 89
Figure 20 – VT1705 LQFP-48 Package (7 mm×7 mm) ................................................................ 92
Figure 21 – The System with Front Panel Design ........................................................................ 93
Figure 22 – The System without Front Panel Design ................................................................... 93
Figure 23 – The System with Only One Back Panel Connector Design ........................................... 94
List of Tables
Table 1 – VT1705 Pin List .......................................................................................................... 6

Table 2 – Signal Type Definitions ................................................................................................ 7
Table 3 – High Definition Audio Link Signal Description ................................................................. 9
Table 4 – Sample Rate Supported ............................................................................................ 19
Table 5 – Node ID List ............................................................................................................ 21

Data Sheet 1
1 Product Features
VT1705
High Definition Audio Codec
1.1 Hardware Features
y Compliant with Intel High Definition

y HPF in ADC Path for DC Removal
Audio Specification Rev. 1.0
y Two GPIO (General Purpose Input and
y Exceeds Microsoft Windows Logo Output) Pins for Customized
Application
Program (WLP) Requirements
y Three Stereo Digital-to-analog

y Functionality of Pins:
Converters – Front-panel Headphone, Line Out, Line
– 16-, 20-, 24-bit Resolution In, and Microphone
Pin 14 and Pin 15 (Port E)
– Audio Sampling Rates: 48 kHz, 96 kHz,
Pin 16 and Pin 17 (Port F)
192 kHz, 44.1 kHz, and 88.2 kHz
– Line Out, Line In, and Microphone
– DAC SNR: 100 dB
Pin 21 and Pin 22 (Port B)
Pin 23 and Pin 24 (Port C)
y Two Stereo Analog-to-digital
Converters
– Headphone and Line Out
Pin 35 and Pin 36 (Port D)
– 16-, 20-, 24-bit Resolution
– Line Out
– Audio sampling rates: 48 kHz, 96 kHz,
Pin 39 and Pin 41 (Port A)
192 kHz, and 44.1 kHz
Pin 43 and Pin 44 (Port G)
– ADC SNR: 93 dB
y Optimized Management of Pop
y Two Independent S/PDIF TX Outputs Mitigation
– Two Output Pins; the Second One for
Digital Audio Output to a HDMI y Supports EAPD (External Amplifier
Transmitter Power Down)
– 16-, 20-, 24-bit Resolution
– Audio sampling rates: 48 kHz, 96 kHz, y Power Management and Enhanced
192 kHz, and 44.1 kHz Power Saving Features
y Jack Presence Detection y Power Supply

– Two Jack Detection Pins; Each Detects – Digital: 3.3V
up to Four Jacks Plugging – Analog: 5.0V
– Jack-detect Circuit with Unsolicited – Support 1.5 ~ 3.3V I/O for HD Audio
Response Link
y Analog Microphone y Package

– Software Selectable Boost Gain (10 – Available in 48-Pin LQFP Lead-free and
dB/ 20dB/ 30dB) for Analog RoHS Compliant Package
Microphone Input
– Four Sets of Adjustable Vref-Out Pins
for Microphone Bias
y Three Built-in Headphone Amplifiers
y Front Panel Jack Re-tasking
y Support Smart 5.1 Output and

Mono-out
y High Performance Analog Mixer (for

AA-path)
y High Quality Differential CD Input

Data Sheet 2
1.2 Software Features
y Meets Microsoft WLK1.2 and Conforms

to the Requirements of Windows
Hardware Quality Labs Testing
(WHQL)
y Functions of Speaker Device

– Equalizer (EQ)
– Room Correction (RC)
– Bass Management (BM)
– Environment Modeling (EM)
– Loudness Equalization (LE)
– Speaker Fill (SF)
y General Features for Mic-Array

Application
– Acoustic Echo Cancellation (AEC)
– Noise Suppression (NS)
– Beam Forming (BF)
y Recording Control for Microphone

Input
y Digital Output Control UI
y VIA Driver Support

– Microsoft Windows Vista (32-bit/
64-bit)
– Microsoft Windows XP
– Microsoft Windows Server 2003
– Microsoft Windows 2000
– WinCE 4.2/ 5.0/ 6.0
– Linux (Fedora Core 7, 8 / Suse SLED
Desktop 10SP1 / UBUNTU 7.1 /
Redhat)
y Optional Sound Effects

– QSound 3D Audio Effects
– DTS CONNECT/ DTS Surround
Sensation
– Dolby PCEE Program
– Creative Audio Program
– Third Party Microphone Array
Technology
y Optional Software Features

– Karaoke Mode for Home Entertainment
– Dynamic Range Control with
Adjustable Parameters

Data Sheet 3
2 Overview
The VT1705 is a low power, high-fidelity 6-channel High Definition Audio Codec designed for audio
systems of desktops and notebooks. It integrates three 24-bit stereo digital-to-analog converters (DAC)
and two stereo analog-to-digital converters (ADC), supporting audio sample rates up to 192 kHz. It is
compatible with Intel High Definition Audio specification.
The two independent 16-, 20-, 24-bit S/PDIF TX Output channels of VT1705 support sampling rates of 48
kHz, 96 kHz, 192 kHz, 44.1 kHz, and 88.2 kHz. The second S/PDIF TX Out is dedicated for digital audio
output to a HDMI transmitter. A high quality analog mixer is used to support A-A path. VT1705 can
achieve 100 dB Signal-to-Noise Ratio (SNR) for DACs and 93 dB SNR for ADCs.
The VT1705 features three built-in headphone amplifier and analog microphone with four sets of
adjustable Vref-out pins for microphone bias. The stereo ADCs and microphone array can support
Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technologies. The
VT1705 uses two jack detection pins for presence detection on up to eight audio jacks. This function
allows software to determine if there is a device plugged into the circuit. VT1705 also supports
front-panel jack re-tasking feature that allows flexible con-figurations.
The VT1705 is embedded with software utilities such as environment emulation, EQ, extender, and the
optional sound effects, including QSound, DTS Connect, Dolby1 Digital Live, Dolby PCEE program, and
Creative audio program. VT1705 is available in a 48-Pin LQFP Pb-free and RoHS compliant package.
VT1705 is a high quality HD audio codec that delivers outstanding performance and design flexibility.
1
Supply of this Implementation of Dolby technology does not convey a license nor imply a right under any patent, or
any other industrial or intellectual property right of Dolby Laboratories, to use this Implementation in any finished
end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby
Laboratories.

Data Sheet 4
3 Functional Block Diagram
Figure 1 – VT1705 Functional Block Diagram

Data Sheet 5
4 Pinout
Figure 2 – VT1705 Pin Diagram for LQFP-48 (Top View)

Data Sheet 6
5 Pin List
Table 1 – VT1705 Pin List
Pin Pin Name Pin Pin Name

1 DVDD_CORE 25 AVDD1
2 GPIO0 / S/PDIF_TX1 26 AVSS1
3 GPIO1 27 VREF_FILTER
4 DVSS 28 VREFOUT-B_L
5 SDO 29 VREFOUT-C
6 BITCLK 30 VREFOUT-F
7 DVSS 31 VREFOUT-E
8 SDI 32 VREFOUT-B_R
9 DVDD_IO 33 CAP1
10 SYNC 34 SENSE_B
11 RESETN 35 PORT-D_L (Front Left)
12 PCBEEP 36 PORT-D_R (Front Right)
13 SENSE_A 37 NC
14 PORT-E_L (Front HP Left) 38 AVDD2
15 PORT-E_R (Front HP Right) 39 PORT-A_L (Surround Left)
16 PORT-F_L (Front MIC 1) 40 JDREF
17 PORT-F_R (Front MIC 2) 41 PORT-A_R (Surround Right)
18 CD_L 42 AVSS2
19 CD_GND 43 PORT-G_L (Center / LFE)
20 CD_R 44 PORT-G_R (LFE / Center)
21 PORT-B_L (Mic 1) 45 NC
22 PORT-B_R (Mic 2) 46 NC
23 PORT-C_L (Line in L) 47 EAPD
24 PORT-C_R (Line in R) 48 S/PDIF_TX0

Data Sheet 7
6 Pin Description
Table 2 – Signal Type Definitions

Type Description
I Input. Standard input-only signal.
O Output. Standard active output driver.
IO Input/output. An input/output signal.
P Power.
6.1 Digital I/O Pins

Pin Name Pin # I/O Signal Description
GPIO0 / 2 IO General Purpose Input/Output 0 /
S/PDIF_TX1 The Second S/PDIF Output
GPIO1 3 IO General Purpose Input/Output 1
SDO 5 I Serial Data Input from Controller
BITCLK 6 I 24 MHz Bit Clock from Controller
SDI 8 IO Serial Data Output to Controller
SYNC 10 I Sample SYNC from Controller
RESETN 11 I Hardware Reset from Controller
EAPD 47 O External Amplifier Power-Down
S/PDIF_TX0 48 O The First S/PDIF Output
6.2 Analog I/O Pins

SENSE_A 13 I Jack Detect Pin 1
SENSE_B 34 I Jack Detect Pin 2
PORT-E_L 14 IO Analog I/O. The default setting is output for Front Panel HP Out Left.
PORT-E_R 15 IO Analog I/O. The default setting is output for Front Panel HP Out
Right.
PORT-F_L 16 IO Analog I/O. The default setting is input for Front MIC.
PORT-F_R 17 IO Analog I/O. The default setting is input for Front MIC.
CD-L 18 I CD Input Left Channel
CD-R 20 I CD Input Right Channel
PORT-B_L 21 IO Analog I/O. The default setting is input for MIC1 Left.
PORT-B_R 22 IO Analog I/O. The default setting is input for MIC1 Right.
PORT-C_L 23 IO Analog I/O. The default setting is input for Line-in Left.
PORT-C_R 24 IO Analog I/O. The default setting is input for Line-in Right.
PORT-D_L 35 O Analog Output for Line-out Left
PORT-D_R 36 O Analog Output for Line-out Right
PORT-A_L 39 O Analog Output for Surround-out Left
PORT-A_R 41 O Analog Output for Surround-out Right
PORT-G_L 43 O Analog Output for Center Line Out.
PORT-G_R 44 O Analog Output for LFE (Low-Frequency Effect) Line Out
PCBEEP 12 I PC Beep Signal Input
VREF_FILTER 27 O Reference Voltage Capacitor
VREFOUT-B_L 28 O Reference Voltage Output for Port B Left

Data Sheet 8
VREFOUT-C 29 O Reference Voltage Output for Port C

VREFOUT-F 30 O Reference Voltage Output for Port F
VREFOUT-E 31 O Reference Voltage Output for Port E
VREFOUT-B_R 32 O Reference Voltage Output for Port B Right
CAP1 33 O Optional Capacitor for ADC Reference
JDREF 40 O External Resistor for Jack Detect Circuit
6.3 Power and Ground

DVDD_CORE 1 P Digital Core Power. 3.3V
DVDD_IO 9 P Digital Power for HDA Link. 1.5V~3.3V
DVSS 4 P Digital VSS
DVSS 7 P Digital VSS
CD_GND 19 - CD Ground
AVDD1 25 P Analog VDD
AVDD2 38 P Analog VDD
AVSS1 26 P Analog VSS
AVSS2 42 P Analog VSS
6.4 NC Pins (Pins with No Connection)

NC 37 - No Connection

Data Sheet 9
7 High Definition Audio Link Protocol
7.1 Link Signaling

The link protocol defines the digital serial interface that connects High Definition Audio codec to the audio
controller, and is not compatible with the previous AC97 protocol. The link is controller synchronous,
based on a fixed 24MHz BITCLK and is purely isochronous without any flow control.
Figure 3 – High Definition Audio Link Conceptual View
7.2 Signal Definitions

Table 3 – High Definition Audio Link Signal Description
Signal Name Source Type Description
BITCLK Controller I 24 MHz Clock
SYNC Controller I Global 48 kHz Frame Sync and Outbound Tag Signal.
SDO Controller I Bussed Serial Data Output from Controller.
SDI Codec & IO Point-to-point Serial Data. The controller has a weak pull
controller down.
RESETN Controller I Global Active Low Reset Signal.
BITCLK is the 24 MHz clock sourced from the controller and connecting to all codec on the link.
SYNC marks input and output frame boundaries (Frame Sync) as well as identifying outbound data
streams (stream tags). SYNC is always sourced from the controller and connects to all codec on the link.
SDO is driven by the controller to all codec on the link. Compared with AC97, the SDO is double pumped
with respect to both rising and falling edges of BITCLK in order to increase the bandwidth required for
High Definition Audio link.
SDI is a point-to-point data signal driven by the codec to the controller. Because the bandwidth
requirement is not that high compared with SDO, the data is single pumped with respect to only the rising
edge of BITCLK. The controller is required to implement weak pull-down on all SDI signals.
RESETN is sourced from the controller and connects to all codec on the link. Assertion of RESETN results
in all link interface logic being reset to Default power on state.

Data Sheet 10
The following figure shows the timing diagram of BITCLK, SYNC, SDO and SDI.
Figure 4 – Bit Timing Diagram
Figure 5 – SYNC and SDO Timing Relative to BITCLK
Figure 5 shows that both SYNC and SDO may be toggled with respect to either edge of BITCLK. In
particular, bit cell n+1 is driven by the controller on SDO with respect to clock edge #2, and is sampled
by the codec with respect to the subsequent clock edge, #3, and so forth.
Figure 6 – SDI Timing Relative to BITCLK
Figure 6 shows that SID may only be toggled with respect to the rising edge of BITCLK. In particular, bit
cell n+1 is driven by the codec on SDI with respect to rising clock edge #2 and is sampled by the
controller with respect to the subsequent rising clock edge, #3, and so forth.

Data Sheet 11
7.3 Signaling Topology

The following diagram shows a typical system with one controller and its associated codec.
SDI14
.
.
.
HDAC SDI2
Controller SDI1
SDI0
SDO
SYNC
BCLK
RST#
RST#
BCLK
SYNCH
SDO
SDI
RST#
BCLK
SYNC
SDO
SDI
RST#
BCLK
SYNC
SDO
SDI
RST#
BCLK
SYNC
SDO
SDI
CODEC 0 CODEC 1 CODEC 2 CODEC 14
Figure 7 – Basic High Definition Audio System
7.4 Frame Composition

A frame is defined as a 20.833 µs window of time marked by the falling edge of the Frame Sync marker,
which identifies the start of each frame. The controller is responsible for generating the Frame Sync
marker, which is a high-going pulse on SYNC, exactly four BITCLK in width.
Figure 8 – Frames Demarcation

Data Sheet 12
Both inbound and outbound frames are made up of three major components, specifically:
y A single Command / Response Field
y Zero or more Stream Packets
y A Null Field to fill out the frame
Figure 9 – Frame Composition
Command / Response Field is used for link and codec management. One of these fields appears
exactly once per frame, MSB first, and is always the first field in the frame. It is composed of a 40-bit
Command Field on each outbound frame from the controller and a 36-bit Response Field on each inbound
frame from the codec.
Stream Tag is the label at the beginning of each stream packet that provides the associated stream ID.
All data in one stream packet belongs to a single stream.
Sample Block is a set of one or more samples, the number of which is specified by the “Channels” field
of the Stream Descriptor Format registers. Samples in a given sample block are associated with a single
given stream, have the same sample size, and have the same time reference. And no padding is
permitted between samples.
Ordering of samples within a block is always the same for all blocks in a given stream.
Sample is a set of bits providing a single sample point of a single analog waveform.
Null Field is used to fill up the remainder of the bits in each frame that are not used for Command /
Response or packets. A null field must be transmitted as logical 0’s.

Data Sheet 13
7.5 Output Frame
7.5.1 Stream Tags

Outbound stream tags are 8 bits in length and are transmitted at a double pumped rate as side band
information on SYNC. It is composed of a 4-bit preamble which is signaled as three SDO bit times high
followed by one SDO bit time low. This is immediately followed by a 4-bit Stream ID. Outbound stream
tags are transmitted on SYNC so as to align with the last eight data bits of the preceding stream packet
or Command Field.
Figure 10 – Outbound Stream Tag Format and Transmission
7.5.2 Outbound Frames

Outbound frames start and end between the falling edges of successive Frame Syncs. The first 40 bits are
dedicated for the Command field and are sued to send commands to codec. The controller transmits the
tag for the first outbound packet on SYNC during the last eight bit times of the Command field. The
sample blocks for the first packet are transmitted on SDO immediately following the Command field.
There’s no proscribed order in which the different stream packets are to be transmitted. Controllers are
required to transmit a null field for the remaining bits within an outbound frame when the transmission
of the stream packets completes before the end of the frame.
Figure 11 – Outbound Frame with Null Field

Data Sheet 14
7.6 Input Frame
7.6.1 Stream Tags

An inbound stream tag is 10 bits in length, and is transmitted “in-line” at a single pumped rate on SDI,
immediately preceding the associated inbound sample blocks. It is composed of a 4-bit stream ID,
followed by a 6-bit data length field that provides the length, in bytes, of all sample blocks with the given
stream packet.
Figure 12 – Inbound Tag Format and Transmission
7.6.2 Inbound Frames

Inbound frames start and end between the falling edges of successive Frame Syncs. The first 36 bits of
an inbound frame are dedicated for the Response Field, which codec use for sending responses to
controller commands. The codec transmits the first stream packet on SID immediately following the
Response Field. A stream tag indicating a packet length of zero must immediately follow the last stream
packet to be transmitted. Such a stream tag marks the completion of data transmission within that frame,
and the remaining valid bit positions are set to the null field. In the event there are less than 10 valid bit
positions remaining in the frame after the last stream packet, then no termination tag is transmitted, and
the remaining bits are the null field.
Figure 13 – Inbound Frame with No Null Field

Data Sheet 15
7.7 Reset and Initialization
7.7.1 Link Reset

A link reset is signaled on the link by assertion of the RESETN signal, and results in all Link interface logic
in both codec and controller, including registers, being initialized to their Default state. The controller
drives all SDO and SYNC outputs low when entering or exiting link reset.
A controller may only initiate the link reset entry sequence after completing any currently pending
initialization or state change requests.
Figure 14 – Link Reset Entry Sequence
The sequence when entering link reset is described as the following.
1. The controller synchronously completes the current frame but does not signal Frame Sync
during the last eight SDO bit times.
2. The Controller synchronously asserts RESETN four or more BITCLK cycles after the completion
of the current frame.
3. BITCLK is stopped at a minimum of four clocks after the assertion of RESETN.
In the event of a host bus reset, the above sequence does not complete, and RESETN is asynchronously
asserted immediately and unconditionally.
Regardless of the reason for entering Link Reset, it may be exited only under software control and in a
synchronous manner.
Figure 15 – Link Reset Exit Sequence

Data Sheet 16
The sequence when exiting link reset is described in the following.
1. The controller provides a properly running BITCLK for a minimum of 100 µs (2400 BITCLK cycles
or more) before the de-assertion of RESETN. This allows time for codec PLLs to lock.
2. The RESETN signal is de-asserted.
3. The SYNC commences signaling valid frames on the link with the first Frame Sync that occurs at
a minimum of four BITCLK cycles after the de-assertion of RESETN.
4. Codec must signal an initialization request via SID within the first 25 Frame Syncs relative to the
de-assertion of their respective RESETN signal.
7.7.2 Codec Function Group Reset

A codec function group reset is initiated via the Function_Reset verb and results in all logic within the
targeted function group being driven to its Default or reset state. By Default VT1705 does not signal a
state change and initialization request on SDI after the Function_Reset verb, and still keeps its codec
address previously assigned by the controller. This behavior can be changed by setting a vendor defined
register bit for backward compatible with the High Definition Audio Spec. See the Vendor Defined verbs
in the Audio Function Group for the detail.
7.7.3 Codec Initialization

Immediately following the completion of Link Reset sequence ( or Function_Reset verb, if enabled by the
vendor-defined verb), VT1705 proceeds through a codec initialization sequence, which provides each
codec with a unique address by which it can thereafter be referenced to Commands on the SDO signal.
During this sequence, the controller provides each requesting codec with a unique address using its
attached SDI signals.
Figure 16 – Codec Initialization Sequence
The codec initialization sequence occurs across three contiguous frames immediately following any reset
sequence. During these three frames, the codec is required to ignore all outbound traffic present on SYNC
& SDO. These three frames, labeled as the “Connect Frame”, the “Turnaround Frame”, and the “Address
Frame”, are described in the following sub-section.

Data Sheet 17
7.7.3.1 Connect and Turnaround Frames

In the Connect and Turnaround Frames, the codec signals its request for initialization on SDI and then
releases SDI (turnaround) to be driven by the controller in the subsequent address frame.
Figure 17 – Connect and Turnaround Frames
The codec signals an initialization request by synchronously driving SDI high during last bit clock cycle of
Frame Sync. SDI must be asserted for the entire BITCLK cycle and must be synchronously de-asserted
the same rising edge of BITCLK as the de-assertion of the Frame Sync. The codec are only permitted to
signal an initialization request on a null input frame, a frame in which no response stream or input
streams are being sent.
In the Turnaround Frame, the codec and controllers are required to turn SDI around upon the completion
of the Connect Frame. To do this, the codec actively drives SDI low for one BITCLK cycle immediately
following the de-assertion of SYNC at the end of the Connect Frame. The codec then puts its SDI drivers
in a high impedance state at the end of the first BITCLK cycle in the Turnaround Frame. Four BITCLK
cycles before the end of the Turnaround Frame, SYNC and SID are driven high by the controller. The SDI
remains driven high through the end of the Turnaround Frame in preparation for the subsequent address
frame.

Data Sheet 18
7.7.3.2 Address Frames

During the Address Frame, SDI is a codec input and is driven by the controller beginning in the last four
BITCLK periods (Frame Sync) of the Turnaround Frame. The falling edge of Frame Sync marks the start
of codec address assignment. Address assignment is indicated by the controller holding each SDI high for
the number of BITCLK cycles equal to the numeric ID of that particular SDI. Thus, the unique address of
the codec becomes the ID of its attached SDI.
Figure 18 – Address Frame
The codec counts from zero to fourteen starting on the rising edge of BITCKL following the de-assertion
of Frame Sync, and samples the value of this count for their unique address on the first rising edge of
BITCLK in which SYNC and SDI are both sampled low.
The controller must put its SDI drivers in a high impedance state by the rising edge of the 18th BITCLK of
the address frame but not before driving each SDI low for at least one clock cycle. The SDI then becomes
an input to the controller. Normal link operation starts on the frame following the completion of the
Address Frame, and the codec is required to actively drive a valid response field and to be ready to accept
commands in this and subsequent frames.

Data Sheet 19
7.8 Handling Stream Independent Sample Rates

Unlike AC97, the Link is source synchronous and has no codec initiated flow control, the controller
generates all sample transfer timing.
7.8.1 Codec Sample Rendering Timing

VT1705 supports the all the multiples and submultiples of the base rates of 48 kHz & 44.1 kHz, up to the
maximum rate respectively of the DAC and ADC. For DAC, up to 192 kHz sample rate is supported. For
ADC, the maximum rate is 96 kHz.
Table 4 – Sample Rate Supported

Multiple Base Rate 48 kHz Base Rate 44.1 kHz
1/6 8 kHz
1/4 11.025 kHz
1/3 16 kHz
1/2 22.05 kHz
2/3 32 kHz
1 48 kHz 44.1 kHz
2 96 kHz 88.2 kHz
4 192 kHz 176.4 kHz
7.8.2 Link Sample Delivering Timing

For streams whose sample rate is a natural harmonic of 48 kHz, the timing is relatively straightforward.
The rates in multiple (N) of 48 kHz are containing N sample blocks in one frame. For the rates in
sub-multiple (1/N) of 48 kHz, there must be one sample block transmitted every one in N frames, and the
intervening N-1 frames will contain no sample for this stream.
Since the link frame rate is fixed at 48 kHz, streams using a base rate of 44.1 kHz must have samples
transmitted on a cadence creating the slightly lower aggregate transmission rate to match the slightly
lower rendering rate. For streams running at a sample rate of 44.1 kHz, there’re occasional frames that
will not contain a sample generating the following cadence.
12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
The dashes indicate frames that do not contain a sample block. The cadence repeats continuously
generating exactly 147 sample blocks every 160 frames, and avoids any long term drift between sample
delivery and rendering clock.
Sample rates that are integral multiples of 44.1KHz apply the “12-11” cadence rule just as a 44.1KHz
sample rate would, except that non-empty frames contain multiple ( 2 or 4 ) sample blocks, instead of
just one.
For a sample rate of 22.05 kHz, the transmission pattern becomes:
{12}-*{11}-*{11}-*{12}-*{11}-*{11}-*{12}-*{11}-*{11}-*{12}-*{11}-*{11}-*{11}-
* (repeat)
where
{12} = 1*1*1*1*1*1*1*1*1*1*1*1*
{11} = 1*1*1*1*1*1*1*1*1*1*
and the asterisks * represent a frame in which there is no sample block.
For a sample rate of 11.025 kHz, the transmission pattern becomes:
[12]-***[11]-***[11]-***[12]-***[11]-***[11]-***[12]-***[11]-***[11]-***[12]-***[
11]-***[11]-***[11]-*** (repeat)
where
[12] = 1***1***1***1***1***1***1***1***1***1***1***1***
[11] = 1***1***1***1***1***1***1***1***1***1***
and the asterisks * represent a frame in which there is no sample block.
These framing sequences apply only to the outbound (SDO) data from the controller. Inbound (SDI)
data transmitted by the codec is permitted to deviate for minimizing codec buffer management.

Data Sheet 20
7.9 Power Management

Whenever the Link is commanded to enter a low power state, it enters the link-reset state. This state is
only exited in response to a software command and follows all link rules for exiting the link reset state.
The Audio Function Group and the analog input / output converter widgets support power control function.
The whole chip power states can be controlled through the Audio Function Group, while individual DACs
and ADCs can also be controlled through the corresponding power state control verbs. The following table
describes the definition of the power states.
Power States Definitions Referenced with AC97

D0 All power on. Individual ADCs & DACs can be
controlled.
D1 All amplifiers and analog converters are powered PR0 & PR1 & PR2
down. Register values maintained, and analog
reference voltage is still on.
D2 Register values maintained, but analog reference PR3
voltage is also down.
D3 Same as D2 state. PR3
7.10 Unsolicited Response Behavior Description

y As jack plug in, and jack pull out, “unsolicited response” occurs.
y As initial state (boot-up or wake-up), jack already plugged-in, the unsolicited response does not
report. Bit 31 of pin sense register needs to correctly report whether anything is plugged in.
y All pin widgets except SPDIF TX, only analog jacks externally exposed, and of the 3.55 mm (1/8’’)
mini jack type need “unsolicited response”.
y “Unsolicited response” is a capability that could be reported by any type of widgets. Microsoft class
driver only takes advantage of pin widget on this because it is not clear what other widget types
(AOW, AIW and MW) are going to use this response.
y While Microsoft spec. is not very clear about what its Default should be, Microsoft recommendation
is to set it as disabled by Default. Class driver will enable it before using unsolicited response.

Data Sheet 21
8 Widget Description
8.1 Node ID List
Table 5 – Node ID List
Node ID Name Input Connection List Note

00 Root Node N/A
01 AFG N/A Audio Function Group
10 AOW0 N/A Analog Output Widget 0
12 DOW0 N/A Digital Output Widget 0 for S/PDIF TX0
13 AIW0 17 Analog Input Widget 0
14 AIW1 1E Analog Input Widget 1
15 DOW1 N/A Digital Output Widget 1 for S/PDIF TX1
16 MW0 10, 1A, 1B, 1D, 1E, 1F, 25 Analog Mixer
17 SW0 16, 1A, 1B, 1D, 1E, 1F ADC Input Selection
18 SW1 11 AOW1 Mute
19 PW0 18 Port A
1A PW1 27 Port B
1B PW2 18 Port C
1C PW3 16 Port D
1D PW4 16, 25 Port E
1E PW5 16, 25 Port F
1F PW8 N/A Pin Widget 8 for CD Input
20 PW9 12 Pin Widget 9 for S/PDIF TX0
21 PW10 15 Pin Widget 10 for S/PDIF TX1
22 VD4 N/A Vendor Widget 4
23 PW7 27 Port G
27 SW2 25 AOW2 Mute

Data Sheet 22
8.2 Root Node (Node ID = 00)
8.2.1 Get Parameter Verb (Verb ID = F00h)
Offset
Get Vendor ID (Payload = 00h) Response: 1106 4397h
Bit Attribute Default Description

31:16 R 1106h Vendor ID
15:0 R 4397h Device ID
Offset
Get Revision ID (Payload = 02h) Response: 0010 0000h

31:24 R 0 Reserved
23:20 R 0001b MajRev
The major revision number (left of the decimal) of the High
Definition Audio Spec to which the codec is fully compliant.
19:16 R 0 MinRev
The minor revision number (right of the decimal) of the High
Definition Audio Spec to which the codec is fully compliant.
15:8 R 0 Revision ID
7:0 R 0 Stepping ID
Offset
Get Subordinate Node Count (Payload = 04h) Response: 0001 0001h

31:24 R 0 Reserved
23:16 R 01h Starting Node Number
15:8 R 0 Reserved
7:0 R 01h Total Number of Nodes
(Only 1 Audio Function Group in the Codec )

Data Sheet 23
8.3 Audio Function Group (Node ID = 01)
Offset
Get Subordinate Node Count (Payload = 04h) Response: 0010 0018h

31:24 R 0 Reserved
23:16 R 10h Starting Node Number.
15:8 R 0 Reserved
7:0 R 18h Total Number of Nodes
Offset
Get Function Group Type (Payload = 05h) Response: 0000 0001h

31:9 R 0 Reserved
8 R 0 Unsolicited Response (Not supported)
7:0 R 01h Audio Function Group
Offset
Get Function Group Capabilities (Payload = 08h) Response: 0000 0306h

31:17 R 0 Reserved
16 R 0 Beep Gen
15:12 R 0 Reserved
11:8 R 3h Input Delay
7:4 R 0 Reserved
3:0 R 6h Output Delay
Offset
Get Supported Power States (Payload = 0Fh) Response: 0000 0000h

31:4 R 0 Reserved
3 R 0 D3Sup
2 R 0 D2Sup
1 R 0 D1Sup
0 R 0 D0Sup
Offset
Get GPIO Capabilities (Payload = 11h) Response: 0000 0001h

31 R 0 GPIOWake= 0
30 R 0 GPIOUnsol= 0, GPIO Unsolicited Response Supported.
29:24 R 0 Reserved
23:16 R 0 NumGPIs= 00h. No GPI Pin Supported
15:8 R 0 NumGPOs= 00h. No GPO Pin Supported
7:0 R 01h NumGPIOs =01h. One GPIO Pin Supported
When pin 2 is not configured as SPDIF_TX1 (F83h, bit4=0), the
number of GPIO will be 2.

Data Sheet 24
8.3.2 Subsystem ID Control Verb (Verb ID = F20h & 720h-723h)

Description Verb ID Payload
Get Get Subsystem ID F20h 8’b0
Set1 Set Subsystem ID[7:0] 720h Subsystem ID [7:0]
Offset
Subsystem ID Register Response: 1106 0000h

31:16 RW 1106h Manufacturer ID
15:8 RW 00h Board SKU
7:0 RW 00h Assembly ID
Note: All 32 bits in the Subsystem ID register are writeable, with the power-on default value of 1106
0000h. The system board BIOS can change the values during power up sequence to precisely describe
the information about the motherboard so that the OS can load the correct driver.
8.3.3 Power State Verbs (Verb ID = F05h & 705h)

Get Get Converter Power State F05h 8’b0
Set Set Converter Power State 705h PS-Set
8’h00: Power State is D0.
Offset
The Whole Chip Power-down Control Register Response: 0000 0000h

31:8 R 0 Reserved
7:4 R 0 PS-Act. Same as PS-Set for AFG.
3:0 RW 0 PS-Set
8.3.4 GPIO Unsolicited Response (Verb ID = F08h & 708h)

Get Get Unsolicited Response F08h 8’b0
Set Set Unsolicited Response 708h Enable unsolicited response
Offset
GPIO Unsolicited Format Response: 0000 0000h

7 RW 0 Unsolicited Response Control
0: Unsolicited Response Disabled
1: Unsolicited Response Enabled
6 R 0 Reserved
5:0 RW 0 Tag
Used by software to determine which node generated the
unsolicited response.

Data Sheet 25
8.3.5 GPIO Data (Verb ID = F15h & 715h)

Get Get GPIO data Response F15h 8’b0
Set Set GPIO data 715h GPIO Data [7:0]
Offset
Set GPIO Data Format Response: - h

7:2 R 0 Reserved
1 W - GPIO1 Data, when GPIO1 Pin is Configured as GPO.
0 W - GPIO0 Data, when GPIO0 pin is Configured as GPO.
Offset
Get GPIO Data Response Format Response: - h

31:2 R 0 Reserved
1 R - GPIO1 Data
0 R - GPIO0 Data
8.3.6 GPIO Enable Mask (Verb ID = F16h & 716h)

Get Get GPIO Enable Mask Response F16h 8’b0
Set Set GPIO Enable Mask 716h GPIO Enable Mask [7:0]
Offset
Get/ Set GPIO Enable Mask Format Response: 0000 0000h

31:2 R 0 Reserved
1 RW 0 0: GPIO1 pin is disabled and in Hi-Z state.
1: GPIO1 pin is enabled and the pin’s behavior will be determined
by the GPIO1 Direction control.
0 RW 0 0: GPIO0 pin is disabled and in Hi-Z state.
1: GPIO0 pin is enabled and the pin’s behavior will be determined
by the GPIO0 Direction control.
8.3.7 GPIO Direction (Verb ID = F17h & 717h)

Get Get GPIO Direction Response F17h 8’b0
Set Set GPIO Direction 717h GPIO Direction[7:0]
Offset
Get/Set GPIO Data Response Format Response: 0000 0000h

31:2 R 0 Reserved
1 RW 0 GPIO1 Direction
0: Input 1: Output
0 RW 0 GPIO0 Direction
0: Input 1: Output

Data Sheet 26
8.3.8 GPIO Unsolicited Response Enable Mask (Verb ID = F19h & 719h)
Get Get GPIO Unsolicited Response Enable Mask F19h 8’b0
Response
Set Set GPIO Unsolicited Response Enable Mask 719h GPIO Unsolicited Response
Enable Mask[7:0]
Offset
Get/ Set GPIO Unsolicited Response Enable Mask Format Response: 0000 0000h

31:2 R 0 Reserved
1 RW 0 0: An unsolicited response will NOT be sent when a GPIO1 line
changes state.
1: An unsolicited response will be sent when a GPIO1 line
changes state.
0 RW 0 0: An unsolicited response will NOT be sent when a GPIO0 line
changes state.
1: An unsolicited response will be sent when a GPIO0 line
changes state.
8.3.9 Vendor Defined Verbs (Verb ID = F70h – F74h) - Reserved
8.3.10 Vendor Defined Verbs (Verb ID = F78h – F7Ch) - Reserved
8.3.12 Vendor Defined Verbs (Verb ID = F88h – F8Ch) – Reserved
8.3.14 Vendor Defined Verbs (Verb ID = F98h – F9Ch) - Reserved
8.3.15 Vendor Defined Verbs (Verb ID = FA0h – FA4h) - Reserved
8.3.16 Vendor Defined Verbs (Verb ID = FA8h – FACh) - Reserved
8.3.17 Function Reset Verb (Verb ID = 7FFh)

Set Function Reset 7FFh 8’b0

Data Sheet 27
8.4 Audio Analog Output Converter Widget (Node ID = 10h, 11h, 25h)
Offset
Audio Widget Capabilities (Payload = 09h) Response: 0000 041Dh

31:24 R 0 Reserved
23:20 R 0 Audio Output Converter Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
10 R 1b Power Control Supported
9 R 0 Analog Widget, not Digital
8 R 0 Connection List is not Present
7 R 0 Does not Support Unsolicited Response
6 R 0 No Processing Control
5 R 0 Reserved
4 R 1b Contain Format Information
3 R 1b Contain Amplifier Parameter
2 R 1b Out Amp Presented
1 R 0 In Amp not Present
0 R 1b Stereo
Offset
Supported PCM Size, Rates (Payload = 0Ah) Response: 000E 05E0h

31:21 R 0 Reserved
20 R 0 No 32-bit Audio Format Support
19 R 1b 24-bit Audio Format Support
16 R 0 8-bit Audio Format Support
15:12 R 0 Reserved
11 R 0 384 kHz not Supported
10 R 1b 192 kHz Supported
9 R 0 176.4 kHz Supported
7 R 1b 88.2 kHz Supported
3 R 0 22.05 kHz not Supported

Data Sheet 28
Offset
Supported Stream Formats (Payload = 0Bh) Response: 0000 0001h

31:3 R 0 Reserved
2 R 0 No AC3 Support
1 R 0 No Float32 Support
0 R 1b PCM Supported
Offset
Supported Power States (Payload = 0Fh) Response: 0000 000Fh

31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup
Offset
Output Amplifier Capabilities (Payload = 12h) Response: 0005 2A2Ah

31 R 0 No Mute Capability
30:23 R 0 Reserved
22:16 R 0000101b Step Size
0000101: Step size is 1.5 dB
15 R 0 Reserved
14:8 R 0101010b Number of Steps
0101010: Number of steps is 42 (-63 dB – 0 dB)
7 R 0 Reserved
6:0 R 0101010b Offset
0101010: Offset 2Ah is 0 dB

Offset
DAC Power-down Control Response: 0000 0000h

31:8 R 0 Reserved
7:4 R 0 PS-Act. Reports the Actual Power State of the Widget.
3:0 RW 0 PS-Set

Data Sheet 29
8.4.3 Converter Stream, Channel Verbs (Verb ID = F06h & 706h)

Get Get Converter Stream / Channel F06h 8’b0
Set Set Converter Stream / Channel 706h Stream is in bit [7:4], and Channel in bit
[3:0].
8.4.4 Converter Format Verbs (Verb ID = Ah & 2h)

Get Get Converter Format Ah 16’b0
Set Set Converter Format 2h Format
Offset
Converter Format Response: 0000 0031h

15 R 0 Stream Type
0: PCM 1: Non-PCM ( Not supported )
14 RW 0 Sample Base Rate
0: 48 kHz 1: 44.1 kHz
13:11 RW 0 Sample Base Rate Multiple
000: x1: 48 kHz, 44.1 kHz 001: x2: 96 kHz, 88.2 kHz
010: x3: 144 kHz ( Not supported )
011: x4: 192 kHz 100-111: Reserved
10:8 RW 0 Sample Base Rate Divisor
000: /1; 48 kHz Others: Not supported
7 R 0 Reserved
6:4 RW 011b Bits per Sample
000: 8-bit ( Not supported )
001: 16-bit 010: 20-bit
011: 24-bit 100: 32-bit ( Not supported )
3:0 RW 0001b Number of Channels (CHAN)
Refers to the number of channels for the stream in each “sample
block” of the “packets” in each “frame” on the link.
0000: 1 0001: 2
……
1111: 16

Data Sheet 30
8.4.5 Amplifier Gain/Mute Verbs (Verb ID = Bh & 3h)

Get Get Amplifier Gain/Mute Bh Format
Set Set Amplifier Gain/Mute 3h Format
Offset
Get Payload Format
15 W - 0: The input amplifier is being requested (Ignored).
1: The output amplifier is being requested.
14 W - Reserved
13 W - 0: The right amplifier is being requested.
1: The left amplifier is being requested.
12:4 W - Reserved
3:0 W - Index
Offset
Get Response Format Response: 0000 002Ah

31:8 R 0 Reserved
7 R 0 Amplifier is Un-muted.
6:0 R 0101010b Amplifier Gain Setting
0101010b: Offset 2Ah is 0 dB.
Offset
Set Payload Format Response: 0000 0000h

15 W - The Output Amplifier is being Set.
14 W - The Input Amplifier is being Set (Ignored).
13 W - The Left Amplifier is being Set.
12 W - The Right Amplifier is being Set.
11:8 W - Index Ignored
7 W - Un-mute
6:0 W - Gain Setting

Data Sheet 31
8.5 Audio Digital Output Converter (S/PDIF TX) Widget (Node ID = 12h, 15h)
Offset
Audio Widget Capabilities (Payload = 09h) Response: 0000 0611h
31:24 R 0 Reserved
23:20 R 0 Audio Output Converter Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
9 R 1b Digital Widget, not Analog
8 R 0 Connection List is not Present.
7 R 0 Does not Support Unsolicited Response.
5 R 0 Reserved
4 R 1b Contains Format Information.
3 R 0 Contains Amplifier Parameter.
2 R 0 Out Amp Present
0 R 1b Stereo
Offset
Supported PCM Size, Rates (Payload = 0Ah) Response: 000E 05E0h
31:21 R 0 Reserved
20 R 0 No 32-Bit Audio Format Support
19 R 1b 24-Bit Audio Format Support
16 R 0 8-Bit Audio Format Support
15:12 R 0 Reserved
10 R 1b 192 kHz not Supported

Data Sheet 32
Offset
31:3 R 0 Reserved
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup

Offset
S/PDIF TX Power-down Control Response: 0000 0400h
31:11 R 0 Reserved
10 R 1b PS-SettingsReset
9:8 R 0 Reserved
7:4 R 0 PS-Act
Reports the actual power state of the widget.
3:0 RW 0 PS-Set

Set Set Converter Stream / Channel 706h Stream is in bit[7:4]; Channel bit[3:0]

Data Sheet 33
8.5.4 S/PDIF Converter Control 1 & 2 Verbs (Verb ID = F0Dh & 70Dh, 70Eh)
Get Get Converter Control State F0Dh 8’b0
Set Set Converter Control 1 70Dh SIC[7:0]
Set Set Converter Control 2 70Eh SIC[15:8]
Offset
S/PDIF IEC Control Bits Format Response: 0000 0000h
15 R 0 Reserved
14:8 RW 0 CC[6:0] Category Code
7 RW 0 L: Generation Level
6 RW 0 PRO
0: Consumer mode. 1: Professional mode.
5 RW 0 AUDIO
0: Data is PCM format. 1: Data is non PCM format.
4 RW 0 Copy
0: Copyright is not asserted. 1: Copyright is asserted.
3 RW 0 Pre
0: Pre-emphasis is none. 1: Filter pre-emphasis is 50/ 15 µs
2 RW 0 VCFG
Determine S/PDIF transmitter behavior when data is not being
transmitted.
1 RW 0 Validity Flag
0 RW 0 DigEn
0: S/PDIF TX disabled. 1: S/PDIF TX enabled.

Data Sheet 34

Offset
15 RW 0 Stream Type
0: PCM 1: Non-PCM
0: 48 kHz 1: 44.1 kHz
000: x1; 48 kHz, 44.1 kHz
001: x2; 96 kHz, 88.2 kHz
010: x3; 144 kHz (Not supported)
011: x4; 192 kHz, 176.4 kHz (176.4 kHz not support)
100-111: Reserved
000 = /1: 48 kHz Others: Not supported
7 R 0 Reserved
000: 8-bit (Not supported) 001: 16-bit
010: 20-bit 011: 24-bit
100: 32-bit (Not supported)
Refers to number of channels for this stream in each “sample
0000: 1 0001: 2
…… 1111: 16

Data Sheet 35
8.6 Audio Analog Input Converter Widget (Node ID = 13h, 14h)
Offset
Audio Widget Capabilities (Payload = 09h) Response: 0010 051Bh
31:24 R 0 Reserved
23:20 R 0001b Audio Input Converter Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
8 R 1b Connection List is Present.
5 R 0 Reserved
4 R 1b Contains Format Information
3 R 1b Contains Amplifier Parameter
2 R 0 Out Amp is not Present.
1 R 1b In Amp is Present.
0 R 1b Stereo
Offset
Supported PCM Size, Rates (Payload = 0Ah) Response: 000E 0560h

31:21 R 0 Reserved
20 R 0 No 32-bit Audio Format Support
16 R 0 8-bit Audio Format Support
15:12 R 0 Reserved

Data Sheet 36
Offset

31:3 R 0 Reserved
Offset
Input Amplifier Capabilities (Payload = 0Dh) Response: 8005 1F0Bh

31 R 1b Mute Capable
30:23 R 0 Reserved
22:16 R 0000101b Step Size
0000101b: Step size is 1.5 dB.
15 R 0 Reserved
14:8 R 0011111b Number of steps
0011111b: Number of steps is 32 (-16.5 dB – 30 dB).
7 R 0 Reserved
6:0 R 0001011b Offset
0001011b: Offset 0Bh is 0dB.
Offset
Connection List Length (Payload = 0Eh) Response: 0000 0001h

31:8 R 0 Reserved
7 R 0 Short Form
6:0 R 0000001b 1 Input Available
Offset

31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup

Data Sheet 37
8.6.2 Connection List Entry Control Verbs (Verb ID = F02h)

Get Get Connection List Entry F02h Offset index n
Offset
Response: 0000 0017h
or 0000 001Eh
31:8 R 0 Reserved
7 R 0 Independent NID
6:0 R - 0010111b: From SW0 (NID = 17h) for AIW0
0011110b: From PW5 (NID = 1Eh) for AIW1

Offset
ADC Power-down Control Response: 0000 0000h

31:8 R 0 Reserved
7:4 R 0 PS-Act. Report the Actual Power State of the Widget.
6:0 R 0 PS-Set

Set Set Converter Stream / Channel 706h Stream is in bit [7:4].
Channel is in bit [3:0].

Data Sheet 38

Offset
15 R 0 Stream Type
0: PCM 1: Non-PCM (Not supported)
0: 48 kHz 1: 44.1 kHz
000: x1; 48 kHz, 44.1 kHz 001: x2; 96 kHz
010: x3; 144 kHz ( Not supported )
011: x4; 192 kHz
100-111: Reserved
000: /1; 48 kHz Others : Not supported
7 R 0 Reserved
000: 8-bit ( Not supported ) 001: 16-bit
010: 20-bit 011: 24-bit
100: 32-bit ( Not supported )
Refers to the number of channels for this stream in each “sample
0000: 1 0001: 2
…… 1111: 16

Data Sheet 39

Offset
Get Payload Format
15 W - 0: The input amplifier is being requested.
1: The output amplifier is being requested (ignored).
14 W - Reserved
12:4 W - Reserved
Offset
Get Response format Response: 0000 008Bh
31:8 R 0 Reserved
7 R 1b 0: Amplifier is un-muted.
1: Amplifier is muted.
0001011b: 0 dB
Offset
15 W - The Output Amplifier is being Set (Ignored).
14 W - The Input Amplifier is being Set.
7 W - 0: Un-mute
1: Mute

Data Sheet 40
8.7 Mixer Widget (Node ID = 16h)
Offset
Audio Widget Capabilities (Payload = 09h) Response: 0020 050Bh

31:24 R 0 Reserved
23:20 R 0010b Audio Mixer Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
5 R 0 Reserved
4 R 0 No Format Information
3 R 1b Amplifier Parameter
2 R 0 Out Amp not Presented
1 R 1b In Amp Present
0 R 1b Stereo
Offset
Input Amplifier Capabilities (Payload = 0Dh) Response: 8005 1F17h

30:23 R 0 Reserved
22:16 R 0000101b Step Size
0000101b: Step size is 1.5 dB.
15 R 0 Reserved
14:8 R 0011111b Number of Steps
0011111b: Number of steps is 31 (-34.5 dB – 12 dB).
7 R 0 Reserved
6:0 R 0010111b Offset
0010111b: Offset 17h is 0 dB.
Offset
31:8 R 0 Reserved
7 R 0 Short Form
6:0 R 0000111b 7 Inputs Available

Data Sheet 41
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup

Offset
Response: 1B1A 1F10h (n=0)
or 0025 1D1Eh (n=4)
Offset index n = 0 Offset index n = 4
31:24 R 1Bh or Connection List Entry n+3 -
00h 1Bh: (PW2, Port C) 00h
23:16 R 1Ah or Connection List Entry n+2 Connection List Entry n+2
25h 1Ah: (PW1, Port B) 25h: (AOW2)
15:8 R 1Fh or Connection List Entry n+1 Connection List Entry n+1
1Dh 1Fh: (PW8, CD) 1Dh: (PW4)
7:0 R 10h or Connection List Entry n Connection List Entry n
1Eh 10h: (AOW0) 1Eh: (PW5, Port F)

Offset
Mixer Power-down Control Response: 0000 0000h
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Data Sheet 42

Offset
Get Payload Format
1: The output amplifier is being requested (ignored).
14 W - Reserved
12:4 W - Reserved
3:0 W - Index
Offset
Get Response Format Response: 0000 0097h
31:8 R 0 Reserved
0010111b: Offset 17h is 0dB.
Offset
15 W - The Output Amplifier is being Set (ignored).
7 W - 0: Un-mute
1: Mute

Data Sheet 43
8.8 Selector Widget SW0 (Node ID = 17h)
Offset
31:24 R 0 Reserved
23:20 R 0011b Audio Selector Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
8 R 1b Connection List is Present
5 R 0 Reserved
3 R 0 Amplifier Parameter
0 R 1b Stereo
Offset
31:8 R 0 Reserved
7 R 0 Short Form
6:0 R 0000110b 6 Inputs Available
Offset

31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup
8.8.2 Connection Select Control Verbs (Verb ID = F01h & 701h)

Get Get Connection Select F01h 8’b0
Default: 00000001h (MIC)
Set Set Connection Select 701h The connection index value to be set

Data Sheet 44

Offset
Response: 1E1B 1A1Fh (n=0)
or 0000 161Dh (n=4)
Offset index n = 0 Offset index n = 4
31:24 R 1Eh or Connection List Entry n+3 Connection List Entry n+3
00h 1Eh: (PW5, Port F) 00h
23:16 R 1Bh or Connection List Entry n+2 Connection List Entry n+2
00h 1Bh: (PW2, Port C) 00h
15:8 R 1Ah or Connection List Entry n+1 Connection List Entry n+1
16h 1Ah: (PW1, Port B) 16h: (MW)
7:0 R 1Fh or Connection List Entry n Connection List Entry n
1Dh 1Fh: (PW8, CD) 1Dh: (PW4, Port E)

Offset
SW0 Power-down Control Response: 0000 0000h
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Data Sheet 45
8.9 Selector Widget SW1-SW2 (Node ID = 18h, 27h)
Offset
31:24 R 0 Reserved
23:20 R 0011b Audio Selector Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
5 R 0 Reserved
3 R 1b Amplifier Parameter
2 R 1b Out Amp Present
0 R 1b Stereo
Offset
31:8 R 0 Reserved
7 R 0 Short Form
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup
Offset
Output Amplifier Capabilities (Payload = 12h) Response: 8000 0000h
30:23 R 0 Reserved
22:16 R 0 Step Size
0000000b: Step size is 0 dB.
15 R 0 Reserved

Data Sheet 46
14:8 R 0 Number of Steps

0000000b: Number of steps is 0.
7 R 0 Reserved
6:0 R 0 Offset

Set Set Connection Select 701h The connection index value to be set.

Offset
or 0000 0025h
31:8 R 0 Reserved
7:0 R 0 Connection List Entry n
11h: (AOW1) for SW1
25h: (AOW2) for SW2

Offset
SW1~SW2 Power-down Control Response: 0000 0000h
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Data Sheet 47

Offset
Get Payload Format
14 W - Reserved
12:4 W - Reserved
Offset
31:8 R 0 Reserved
6:0 R 0 Amplifier Gain Setting
Offset
14 W - The Input Amplifier is being Set (Ignored).
7 W - 0: Un-mute
1: Mute

Data Sheet 48
8.10 Pin Widget PW0 (Node ID = 19h)
Offset
31:9 R 0 Reserved
8 R 1b Unsolicited Capable
7:0 R 00000001b Audio Function Group
Offset
31:24 R 0 Reserved
23:20 R 0100b Pin Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
7 R 1b Support Unsolicited Response
5 R 0 Reserved
4 R 0 Doesn’t Contain Format Information
3 R 0 Contain Amplifier Parameter
2 R 0 Out Amp not Present
0 R 1b Stereo
Offset
Pin Capabilities (Payload = 0Ch) Response: 0000 0014h
31:17 R 0 Reserved
16 R 0 EAPD Capable
15:8 R 0 Vref Control
7 R 0 Reserved
6 R 0 Balanced I/O Pins
5 R 0 Input Capable
4 R 1b Output Capable
3 R 0 Headphone Drive Capable
2 R 1b Presence Detect Capable
1 R 0 Trigger Required
0 R 0 Impedance Sense Capable.

Data Sheet 49
Offset
31:8 R 0 Reserved
7 R 0 Short Form
6:0 R 0000001b Only 1 Input Available
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup

Offset
31:8 R 0 Reserved
6:0 R 0011000b From SW1

Get Get Converter Power State F05h Offset index n
Offset
PW0 Power-down Control Response: 0000 0000h

31:8 R 0 Reserved
3:0 R 0 PS-Set

Data Sheet 50
8.10.4 Pin Widget Control Verbs (Verb ID = F07h & 707h)

Get Get Pin Widget Control F07h 8’b0
Set Set Pin Widget Control 707h PinCntl
Offset
7 RW 0 Headphone Enable
0: Disabled
1: Headphone enabled (Not supported)
6 RW 0 Output Enable
0: Disabled (default)
1: Output enabled
5 R 0 Input Enable
0: Disabled
1: Input enabled (Not supported).
4:0 R 0 Reserved
8.10.5 Unsolicited Response Control (Verb ID = F08h & 708h)

Get Get Unsolicited Response Control F08h 8’b0
Set Set Unsolicited Response Control 708h Enable unsolicited response
Offset
Unsolicited Format Response: 0000 0000h
7 RW 0 0: Unsolicited Response Disabled
6 R 0 Reserved
5:0 RW 0 Tag
Used by software to determine the node that generated the
8.10.6 Right Channel Sense (Verb ID = F09h & 709h)

Get Get Pin Sense Control F09h 8’b0
Set Set Pin Sense Control 709h PinCntl
Offset
PinCntl Format Response: 0000 0000h
7:1 R 0 Reserved
0 R 0 Right Channel Sense ( Not supported )

Data Sheet 51
Offset
Presence Detect Response: 0000 0000h
31 R 0 Presence Detect
0: Nothing plugged in.
1: Jack plugged in.
30:0 R 0 Reserved
8.10.7 Pin Widget Configuration Default Verbs (Verb ID = F1Ch & 71Ch-71Fh)
Get Get Pin Widget Configuration Default F1Ch 8’b0
Set Set Pin Widget Configuration Default 71Ch Config bits [7:0]
Set Set Pin Widget Configuration Default 71Dh Config bits [15:8]
Set Set Pin Widget Configuration Default 71Eh Config bits [23:16]
Set Set Pin Widget Configuration Default 71Fh Config bits [31:24]
Offset
Configation Bits Format Response: 0101 1012h
31:30 RW 0 Port Connectivity
00: Connected to a jack
29:24 RW 000001b Location
23:20 RW 0 Default Device
0000b: Line-out
19:16 RW 0001b Connection Type
15:12 RW 0001b Color
11:8 RW 0 Misc.
7:4 RW 0001b Default Association
3:0 RW 0010b Sequence
0010b: Surround out in association # 1

Data Sheet 52
8.11 Pin Widget PW3 (Node ID =1Ch)
Offset
31:9 R 0 Reserved
Offset
31:24 R 0 Reserved
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
5 R 0 Reserved
4 R 0 Does not Contain Format Information.
1 R 0 In Amp not Present.
0 R 1b Stereo
Offset
Pin Capabilities (Payload = 0Ch) Response: 0001 001Ch
37:17 R 0 Reserved
16 R 1b EAPD Capable
15:8 R 0 VRef Control
7 R 0 Reserved
5 R 0 Input Capable
3 R 1b Headphone Drive Capable.
0 R 0 Impedance Sense Capable

Data Sheet 53
Offset
37:8 R 0 Reserved
7 R 0 Short Form
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup
Offset
30:23 R 1b Reserved
22:16 R 0 Step Size
15 R 0 Reserved
0000000b: Number of steps is 0h.
7 R 0 Reserved
6:0 R 0 Offset

Offset
31:8 R 0 Reserved
6:0 R 0010110b From MW0

Data Sheet 54

Offset
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Offset

0: Disabled
1: Headphone enabled
0: Disabled
1: Output enabled
5 RW 0 Input Enable
0: Disabled
1: Input enabled (Not supported)
4:0 R 0 Reserved

Offset

6 R 0 Reserved
5:0 RW 0 Tag

Data Sheet 55
8.11.6 Pin Sense Control Verbs (Verb ID = F09h & 709h)

Offset

7:1 R 0 Reserved
0 R 0 Right Channel Sense (Not supported)
Offset

0: Nothing plugged in
1: Jack plugged in
30:0 R 0 Reserved
8.11.7 EAPD Enable Verbs (Verb ID = F0Ch & 70Ch)

Get EAPD Control F0Ch 8’b0
Set 70Ch Bit 1 is EAPD
Offset

11:8 RW 0 Misc.
3:0 RW 0 Sequence

Data Sheet 56

Get Get Amplifier Gain/Mute Bh
Set Set Amplifier Gain/Mute 3h
Offset
Get Payload Format
14 W - Reserved
12:4 W - Reserved
3:0 W - Index
Offset

31:8 R 0 Reserved
7 R 1b 0: Amplifier is unmated.
Offset

14 W - The Input Amplifier is being Set (ignored).
7 W - 0: Un-Mute
1: Mute

Data Sheet 57
8.12 Pin Widget PW4 (Node ID =1Dh)

Offset
31:9 R 0 Reserved
Offset

31:24 R 0 Reserved
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
5 R 0 Reserved
4 R 0 Doesn’t Contain Format Information.
1 R 0 In Amp Present
0 R 1b Stereo
Offset
31:17 R 0 Reserved
16 R 0 EAPD Capable
15:8 R 23h Vref Control
23h: 100% & 50% & Hi-Z
7 R 0 Reserved
5 R 1b Input Capable
3 R 1b Headphone Drive Capable

Data Sheet 58
Offset
31:8 R 0 Reserved
7 R 0 Short Form
6:0 R 2h 2 Input Available
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R‘ 1b D0Sup
Offset
Input Amplifier Capabilities (Payload = 0Dh) Response: 0000 0000h
31 R 0 Mute Capable
30:23 R 0 Reserved
22:16 R 0 Step Size
0000000b: Step size is 0 db.
15 R 0 Reserved
7 R 0 Reserved
6:0 R 0 Offset
Offset
30:23 R 0 Reserved
22:16 R 0 Step Size.
15 R 0 Reserved
7 R 0 Reserved
6:0 R 0 Offset

Data Sheet 59

Set Set Connection Select 701h The connection index value to be set
8’b0: from MW0
8’b1: form AOW2
Offset
Get Response Format Response: -h
31:8 R 0 Reserved
7:0 R - Connection Index Currently Set
00h: Connection from MW0
01h: Connection form AOW2

Offset

31:16 R 0 Reserved
15:8 R 00100101b From AOW2
6:0 R 0010110b From MW0

Offset
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Data Sheet 60

Offset
0: Disabled
0: Disabled
1: Output enabled
5 RW 0 Input Enable
0: Disabled
1: Input enabled
4:3 R 0 Reserved
2:0 RW 0 VRef Enable
These bits control the VRef signal associated with the pin widget.
000b: Hi-Z
001b: 50% (half of AVdd)
010b: 0V (Not supported)
101b: AVdd
Others: Reserved

Offset

6 R 0 Reserved
5:0 RW 0 Tag

Data Sheet 61

Offset
7:1 R 0 Reserved
0 R 0 Right Channel Sense ( Not supported )
Offset
Response: -h
31 R - Presence Detect
1: Jack plugged in
30:0 R 0 Reserved
Offset
Config Bits Format Response: 0221 401Fh
23:20 RW 0010b Default Device
11:8 RW 0 Misc.

Data Sheet 62

Offset
Get Payload Format
14 W - Reserved
12:4 W - Reserved
3:0 W - Index
Offset
Get Response Format Response: -h
31:8 R 0 Reserved
7 R - 0: Amplifier is un-muted (input default).
1: Amplifier is muted (output default).
Offset
15 W - The Output Amplifier is being Set
14 W - The Input Amplifier is being Set
13 W - The Left Amplifier is being Set
12 W - The Right Amplifier is being Set
7 W - 0: Un-mute
1: Mute

Data Sheet 63
8.13 Pin Widget PW7 (Node ID =23h)
Offset
31:9 R 0 Reserved
Offset
Audio Widget Capabilities (Payload = 09h) Response: 0040 0581b
31:24 R 0 Reserved
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
5 R 0 Reserved
1 R 0 In Amp not Presented
0 R 1b Stereo
Offset
31:17 R 0 Reserved
16 R 0 EAPD Capable
7 R 0 Reserved
5 R 0 Input Capable

Data Sheet 64
Offset
31:8 R 0 Reserved
7 R 0 Short Form
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R‘ 1b D0Sup

Offset
Response: 0000 0027h (for PW7)
31:8 R 0 Reserved
6:0 R 0100111b (From SW2) for PW7

Offset
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Data Sheet 65

Offset
7 R 0 Headphone Enable
0: Disabled 1: Output enabled
5 RW 0 Input Enable
0: Disabled
1: Input enabled (not supported)
4:0 R 0 Reserved

Offset
6 R 0 Reserved
5:0 RW 0 Tag

Data Sheet 66

Offset
PinCntl Format Response: - h
7:1 R - Reserved
0 R - Right Channel Sense ( Not supported )
Offset

1: Jack plugged in
30:0 R 0 Reserved
Offset
Response: 0101 6011h for PW7
0110b: for PW7
11:8 RW 0 Misc
0001b: for PW7

Data Sheet 67
8.14 Pin Widget PW1, PW2 (Node ID = 1Ah, 1Bh)
Offset
31:9 R 0 Reserved
Offset
31:24 R 0 Reserved
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
5 R 0 Reserved
1 R 0 In Amp Presented
0 R 1b Stereo
Offset
31:17 R 0 Reserved
16 R 0 EAPD Capable
15:8 R 23h VRef Control
23h: 100% & 50% & Hi-Z
7 R 0 Reserved

Data Sheet 68
Offset
31 R 0 Mute Capable
30:23 R 0 Reserved
22:16 R 0 Step Size
0: Step size is 0 dB
15 R 0 Reserved
0: Number of steps is 0h
7 R 0 Reserved
6:0 R 0 Offset
0000000b: Offset 00h
Offset
31:8 R 0 Reserved
7 R 0 Short Form
6:0 R 0000001b Only 1 Input Available.
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R‘ 1b D0Sup

Offset
Response: 0000 0027h (for PW1)
0000 0018h (for PW2)
31:8 R 0 Reserved
6:0 R - 0100111b: (From SW2, NID = 27h) for PW1
0011000b: (From SW1, NID = 18h) for PW2

Data Sheet 69

Offset
PW1, PW2 Power-down Control Response: 0000 0000h
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Offset
6 RW 0 Output Enable (for Smart 5.1 Configuration)
1: Output enabled
5 RW 0 Input Enable
1: Input enabled
4:3 R 0 Reserved
000: Hi-Z (default)
001: 50% (half of AVdd)
010: 0V (Not supported)
101: AVdd
Others: Reserved

Data Sheet 70

Offset
Unsolicited Format Response: - h
7 RW - 0: Unsolicited Response Disabled
6 R - Reserved
5:0 RW - Tag

Offset
7:1 R - Reserved
0 R - Right Channel Sense (Not supported)
Offset
Response Response: - h
1: Jack plugged in
30:0 R 0 Reserved

Data Sheet 71
Offset
Config Bits Format Response: 01A1 9026h for PW1
0181 302Eh for PW2
29:24 RW - Location
000001: For PW1
000001: For PW2
23:20 RW - Default Device
1010b: For PW1
1000b: For PW2
15:12 RW - Color
1001b: For PW1
0011b: For PW2
11:8 RW 0 Misc
7:4 RW - Default Association
0010b: For PW1
0010b: For PW2
3:0 RW - Sequence
0110b: For PW1
1110b: For PW2

Data Sheet 72

Offset
Get Payload Format
15 W - 0: The input amplifier is being requested (ignored).
14 W - Reserved
12:4 W - Reserved
3:0 W - Index
Offset
Get Response format Response: 0000 0000h
31:8 R 0 Reserved
7 R 0 0: Amplifier is un-muted (input default)
Offset
15 W - The Output Amplifier is being Set (Ignored).
7 W - 0: Un-mute
1: Mute

Data Sheet 73
8.15 Pin Widget PW5 (Node ID = 1Eh)
Offset
31:9 R 0 Reserved
7:0 R 00000001 Audio Function Group
Offset
31:24 R 0 Reserved
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
5 R 0 Reserved
2 R 1b Out Amp Presented
1 R 0 In Amp Presented
0 R 1b Stereo
Offset
31:17 R 0 Reserved
16 R 0 EAPD Capable
15:8 R 23h VRef Control
23h: 100% & 50% & Hi-Z
7 R 0 Reserved
3 R 1b Headphone Drive Capable

Data Sheet 74
Offset
31 R 0 Mute Capable
30:23 R 0 Reserved
22:16 R 0 Step Size
0: Step size is 0 dB.
15 R 0 Reserved
0: Number of steps is 0h.
7 R 0 Reserved
6:0 R 0 Offset
Offset
31:8 R 0 Reserved
7 R 0 Short Form
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup
Offset

30:23 R 0 Reserved
22:16 R 0 Step Size
0: Step size is 0 dB
15 R 0 Reserved
0: Number of steps is 0h.
7 R 0 Reserved
6:0 R 0 Offset

Data Sheet 75

Set Set Connection Select 701h The Connection Index Value to be Set.
8’b0: from MW0
8’b1: form AOW2
Offset
Get Response Format Response: - h
31:8 R 0 Reserved
7:0 R - Connection Index Currently Set
00h: Connection from MW0
01h: Connection form AOW2

Offset

31:16 R 0 Reserved
15:8 R 00100101b From AOW2
6:0 R 0010110b From MW0

Offset
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Data Sheet 76

Offset
0: Disabled
6 RW 0 Output Enable (for Smart 5.1 Configuration)
5 RW 0 Input Enable
0: Disabled 1: Input enabled
4:3 R 0 Reserved
000: Hi-Z 001: 50% (half of AVdd)
010: 0V ( Not supported ) 101: AVdd
Others: Reserved

Offset
6 R 0 Reserved
5:0 RW 0 Tag

Data Sheet 77

Offset
7:1 R 0 Reserved
0 R - Right Channel Sense ( Not supported )
Offset
Response: - h

0 : Nothing plugged in 1 : Jack plugged in
30:0 R 0 Reserved
Offset
Config Bits Format Response: 02A1 9027h

11:8 RW 0 Misc.

Data Sheet 78

Offset
Get Payload Format
1: The output amplifier is being requested (Ignored).
14 W - Reserved
12:4 W - Reserved
3:0 W - Index
Offset
Get Response format Response: 0000 0000h
31:8 R 0 Reserved
7 R 0 0: Amplifier is un-muted (input default).
1: Amplifier is muted (output default).
Offset
7 W - 0: Un-mute
1: Mute

Data Sheet 79
8.16 Pin Widget PW8 (Node ID = 1Fh) CD Analog Input
Offset
31:24 R 0 Reserved
23:20 R 0100 Pin Widget
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
8 R 0 Connection List is not Presented
5 R 0 Reserved
3 R 0 Doesn’t Contain Amplifier Parameter
1 R 0 In Amp not Presented
0 R 1b Stereo
Offset

31:17 R 0 Reserved
16 R 0 EAPD Capable
7 R 0 Reserved
4 R 0 Output Capable.
2 R 0 Presence Detect Capable
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R‘ 1b D0Sup

Data Sheet 80

Offset
31:8 R 0 Reserved
3:0 RW 0 PS-Set

Offset
0: Disabled
6 R 0 Output Enable
0: Disabled
5 RW 0 Input Enable
0: Disabled
1: Input enabled
4:3 R 0 Reserved
2:0 R 0 VRef Enable

Data Sheet 81
Offset
Config Bits Format Response: 5933 11F8h

31:30 RW 01b Port Connectivity
011001b: Internal
0011b: CD
11:8 RW 0001b Misc

Data Sheet 82
8.17 Pin Widget PW9 (Node ID = 20h ) S/PDIF TX Pin
Offset
31:24 R 0 Reserved
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R Swap
9 R 1b Digital Widget
5 R 0 Reserved
4 R 0 Not Containing Format Information
3 R 0 Not Containing Amplifier Parameter
2 R 0 Out amp not Presented
1 R 0 In amp not Present
0 R 1b Stereo
Offset
31:17 R 0 Reserved
16 R 0 EAPD Capable
7 R 0 Reserved
5 R 0 Input Capable
Offset
31:8 R 0 Reserved
7 R 0 Short Form

Data Sheet 83
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup

Offset
31:8 R 0 Reserved
6:0 R 0010010b From DOW0 (NID = 12h)

Offset

31:11 R 0 Reserved
9:8 R 0 Reserved
7:4 R 0 PS-Act
Reports the actual power state of the widget.
3:0 RW 0 PS-Set

Data Sheet 84

Offset
0: Disabled
5 R 0 Input Enable
0: Disabled
4:3 R 0 Reserved
2:0 R 0 VRef Enable
Offset
0100b: SPDIF Out
11:8 RW 0001b Misc.

Data Sheet 85
8.18 Pin Widget PW10 (Node ID = 21h ) HDMI Audio Output Pin
Offset
31:24 R 0 Reserved
19:16 R 0 Delay
15:12 R 0 Reserved
11 R 0 No L-R swap.
9 R 1b Digital Widget
5 R 0 Reserved
4 R 0 Contain no Format Information.
3 R 0 Contain no Amplifier Parameter.
2 R 0 Out amp not Presented
1 R 0 In amp not Present
0 R 1b Stereo
Offset
31:17 R 0 Reserved
16 R 0 EAPD Capable
7 R 0 Reserved
5 R 0 Input Capable
Offset

31:8 R 0 Reserved
7 R 0 Short Form

Data Sheet 86
Offset
31:4 R 0 Reserved
3 R 1b D3Sup
2 R 1b D2Sup
1 R 1b D1Sup
0 R 1b D0Sup

Offset
31:8 R 0 Reserved
6:0 R 0010101b From DOW1, NID = 15h

Offset
31:11 R 0 Reserved
9:8 R 0 Reserved
3:0 RW 0 PS-Set

Data Sheet 87

Offset
0: Disabled
0: Disabled
1: Output enabled
5 R 0 Input Enable
0: Disabled
4:3 R 0 Reserved
2:0 R 0 VRef Enable
Offset
31:30 RW 10b Port Connectivity
0101b: SPDIF Out
11:8 RW 0001b Misc.

Data Sheet 88
9 Functional Descriptions
9.1 Clock Control

One of the major differences between the High Definition Audio Specification and AC97 is the clock source.
The High Definition Audio Controller provides a 24 MHz clock (BITCLK). An internal PLL (PLL1) in the
codec uses BITCLK (24 MHz) as the reference clock and generates 49.152 MHz clocks for internal use. A
second PLL (PLL2) also takes the 24 MHz BITCLK and generates 22.5792 MHz clock for 44.1 kHz base
rates. The PLLs can be powered down by the Power Widget for power management. Both PLL output
clocks can be routed to Pin 48 by a vendor defined verb for testing.
The interface signals between digital block and the 2 PLLs are listed below.
PLL1 (49.152 MHz)

Pin Name Direction (From PLL) Pin Description
REFCLK I Connect to a 24-MHz clock input.
CLK49152 O 49.152-MHz clock output.
When RST is high, the PLL enters a low power mode and all
RST I
internal states are reset.
PWRPD I When PWRPD is high, the PLL enters a power-down mode.
VDD IO Digital power supply for PFD and Dividers. Nominally 3.3V.
GND IO Ground for PFD and Dividers.
VCOPWR IO Analog power supply for VCO. Nominally 3.3V.
VCOGND IO Ground for VCO.
CHGPPWR IO Analog power supply for Bias and Charge Pump. Nominally 3.3V.
CHGPGND IO Ground for Bias and Charge Pump.
22.5792 MHz
Pin Name Direction (From PLL) Pin Description
REFCLK I Connect to a 24-MHz clock input.
CLK225792 O 22.5792-MHz clock output.
When RST is high, the PLL enters a low power mode and all
RST I
internal states are reset.
PWRPD I When PWRPD is high, the PLL enters a power-down mode.
VDD IO Digital power supply for PFD and Dividers. Nominally 3.3V.
GND IO Ground for PFD and Dividers.
VCOPWR IO Analog power supply for VCO. Nominally 3.3V.
VCOGND IO Ground for VCO.
CHGPPWR IO Analog power supply for Bias and Charge Pump. Nominally 3.3V.
CHGPGND IO Ground for Bias and Charge Pump.
9.2 Interpolation / Decimation

To take advantage of the high bandwidth provided by the new audio interface, the hardware only
supports native 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz sample rates, and the driver is
responsible for converting the data to / from 192 kHz. This way the large area previously required for
implementing the digital interpolation / decimation filters can be saved.
9.3 HPF for ADC DC Removal

The built-in high-pass filter for each ADC can remove the DC component in the ADC data.

Data Sheet 89
9.4 Audio Jack Detection Circuits

Based on the jack detection circuit defined in the High Definition Audio Specification, the figure below
summarizes the equivalent resistance values to the SENSE Pin in different scenario.
Figure 19 – Jack Detect Circuit
9.5 Internal Loop-back and Peak Detection for Low Cost Production Test
Internal loop-back paths can be used to test all DACs and ADCs functions. The output of each DAC can be
routed back to the input of the ADC. The ADC output data is analyzed by a specially designed block to
detect the zero-crossing point and the peak values. These information can be read back to decide
whether the digital & analog functions are normal. Refer to the descriptions in the Vendor-Defined Verbs
in the Audio Function Group.
9.6 GPIO Implementation
9.6.1 GPIO Pinout
y Pin 47: EAPD
y Pin 48: SPDIF_TX0
y Pin 2: GPIO0/ SPDIF_TX1
y Pin 3: GPIO1
9.6.2 Usage
y GPI:
– Front Panel Sense
– Others
y GPO:
– EAPD-like Control
– Others
NB 1 NB 2 NB 3 Desk Top 1 Desk Top 2 I/O

GPO for EAPD0 (Line √ √ √ - - -
Out)
GPO for EAPD1 √ √ √ - - -
(Head Phone)
SPDIF_TX0 √ √ √ √ √ -
SPDIF_TX1 - - - √ √ -
GPI √ √ - √ - -
(Front Panel
Sense)
Pin 47: EAPD GPO GPO GPO - - O
Pin 48: SPDIF_TX0 SPDIF_TX0 SPFID_TX0 SPDIF_TX0 SPDIF_TX0 O
SPDIF_TX0
Pin 2: GPO GPO GPO SPDIF_TX1 SPDIF_TX1 IO
SPDIF_TX1
Pin 3: GPI GPI - GPI - IO
GPIO1

Data Sheet 90
10 Electrical Specification
Absolute Maximum Rating
Symbol Parameter Min Max Unit Note

TS Storage Temperature -55 125 °C —
TA Ambient Operating Temperature 0 85 °C —
Electrostatic Discharge
VESD — 2 kV —
(human body model)
Note: Stress above conditions may cause permanent damage to the device. Functional operation of this
device should be restricted to the conditions described.
Recommended Operating Conditions
Symbol Parameter Min Max Unit Note

AVDD Analog Power Supplies
– 5 – V
(preferred)
AVDD Analog Power Supplies
– 3.3 – V
(for low-power apps)
Digital DC and AC Characteristics
DC Performance Characteristic
Symbol Parameter Min Typ Max Unit

DVdd Digital Power Supply 3.135 3.3 3.465 V
VIN Input Voltage Range -0.3 DVdd + 0.3 V
VIL Low Level Input Voltage 0.35 x DVdd V
VIH High Level Input Voltage 0.65 x DVdd V
VOH High Level Output Voltage 0.9 x DVdd V
VOL Low Level Output Voltage 0.1 x DVdd V
Input Leakage Current -10 10 µA
(AC-Link inputs)
Output Leakage Current -10 10 µA
(Hi-Z’d AC-Link outputs)
Input / Output Pin Capacitance 7.5 pF

Data Sheet 91
Analog Performance Characteristics
Parameter Min Type Max Unit

Analog Input
Full Scale Input Voltage
Line Inputs 1.0 Vrms
Mic Inputs with 20 dB Gain 0.1
Mic inputs with 0 dB Gain 1
Input Impedance 10 kΩ
Input Capacitance 7.5 pF
Power Supply Rejection Ratio (10 kHz) 54.59 dB
Analog Output
Full Scale Output Voltage
Line Output 1.0 Vrms
Headphone Output 1.41
Analog S/N
Other to LINE_OUT 100 dB
Analog Frequency Response 20 20,000 Hz
Vrefout 2.25-2.75 V
ADC Converters
Dynamic Range (-60 dB Full Scale, A-Weight) 93 dB
Total Harmonic Distortion 0.003 %
Frequency Response 20 21,600 Hz
Transition Band 21,600 28,800 Hz
Stop Band 28,800 Hz
Stop Band Rejection -74 dB
Out-of-Band Rejection -40 dB
Spurious Tone Reduction -100 dB
Attenuation, Gain Step Size 1.5 dB
DAC Converters
Dynamic Range (-60 dB Full Scale, A-Weight) 100 dB
Total Harmonic Distortion 0.003 %
Frequency Response 20 21,600 Hz
Transition Band 21,600 28,800 Hz
Stop Band 28800 Hz
Stop Band Rejection -75 dB
Out-of-Band Rejection -40 dB
Channel Separation -90 dB
Spurious Tone Reduction -100 dB
Attenuation, Gain Step Size 1.5 dB
Note: The frequency response, transition band and stop band specified in the table is based on fs = 48
kHz, and scale with fs.

Data Sheet 92
11 Mechanical Specification
Figure 20 – VT1705 LQFP-48 Package (7 mm×7 mm)

Data Sheet 93
12 Application Circuit
Figure 21 – The System with Front Panel Design
Figure 22 – The System without Front Panel Design

Data Sheet 94
Figure 23 – The System with Only One Back Panel Connector Design

Data Sheet
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Data Sheet: VT1705 High Definition Audio Codec

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Data Sheet

June 11, 2009

Free Datasheet http://www.datasheet4u.com/

Rev Date Initial Note

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Revision History ........................................................................................................................ i

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Figure 1 – VT1705 Functional Block Diagram ............................................................................... 4

Table 1 – VT1705 Pin List .......................................................................................................... 6

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1.1 Hardware Features

y Compliant with Intel High Definition

y Three Stereo Digital-to-analog

y Jack Presence Detection y Power Supply

y Analog Microphone y Package

y Three Built-in Headphone Amplifiers

y Front Panel Jack Re-tasking

y Support Smart 5.1 Output and

y High Performance Analog Mixer (for

y High Quality Differential CD Input

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1.2 Software Features

y Meets Microsoft WLK1.2 and Conforms

y Functions of Speaker Device

y General Features for Mic-Array

y Recording Control for Microphone

y Digital Output Control UI

y VIA Driver Support

y Optional Sound Effects

y Optional Software Features

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3 Functional Block Diagram

Figure 1 – VT1705 Functional Block Diagram

Figure 2 – VT1705 Pin Diagram for LQFP-48 (Top View)

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Table 1 – VT1705 Pin List

Pin Pin Name Pin Pin Name

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Table 2 – Signal Type Definitions

6.1 Digital I/O Pins

6.2 Analog I/O Pins

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VREFOUT-C 29 O Reference Voltage Output for Port C

6.3 Power and Ground

6.4 NC Pins (Pins with No Connection)

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7 High Definition Audio Link Protocol

7.1 Link Signaling

Figure 3 – High Definition Audio Link Conceptual View

7.2 Signal Definitions

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Figure 4 – Bit Timing Diagram

Figure 5 – SYNC and SDO Timing Relative to BITCLK

Figure 6 – SDI Timing Relative to BITCLK

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7.3 Signaling Topology