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    Data Sheet: HEF4040B MSI

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    abesseda
    This 3 sentence summary provides the essential information about the HEF4040B integrated circuit document: The HEF4040B is a 12-stage binary ripple counter integrated circuit that contains a clock input, master reset input, and 12 outputs. It functions by advancing the counter on the falling edge of the clock input and can be reset by a high signal on the master reset input. The document provides information on the pinning, logic diagram, AC characteristics, and typical applications of the HEF4040B 12-stage binary counter integrated circuit.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Data Sheet: HEF4040B MSI

    Uploaded by

    abesseda
    57 views5 pages
    This 3 sentence summary provides the essential information about the HEF4040B integrated circuit document: The HEF4040B is a 12-stage binary ripple counter integrated circuit that contains a clock input, master reset input, and 12 outputs. It functions by advancing the counter on the falling edge of the clock input and can be reset by a high signal on the master reset input. The document provides information on the pinning, logic diagram, AC characteristics, and typical applications of the HEF4040B 12-stage binary counter integrated circuit.

    Original Description:

    cmos logic 4040 datasheet

    Original Title

    HEF4040B_CNV_3

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    © © All Rights Reserved

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    This 3 sentence summary provides the essential information about the HEF4040B integrated circuit document: The HEF4040B is a 12-stage binary ripple counter integrated circuit that contains a clock input, master reset input, and 12 outputs. It functions by advancing the counter on the falling edge of the clock input and can be reset by a high signal on the master reset input. The document provides information on the pinning, logic diagram, AC characteristics, and typical applications of the HEF4040B 12-stage binary counter integrated circuit.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    57 views5 pages

    Data Sheet: HEF4040B MSI

    Uploaded by

    abesseda
    This 3 sentence summary provides the essential information about the HEF4040B integrated circuit document: The HEF4040B is a 12-stage binary ripple counter integrated circuit that contains a clock input, master reset input, and 12 outputs. It functions by advancing the counter on the falling edge of the clock input and can be reset by a high signal on the master reset input. The document provides information on the pinning, logic diagram, AC characteristics, and typical applications of the HEF4040B 12-stage binary counter integrated circuit.

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    © All Rights Reserved
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    INTEGRATED CIRCUITS

    DATA SHEET
    For a complete data sheet, please also download:

    • The IC04 LOCMOS HE4000B Logic


    Family Specifications HEF, HEC
    • The IC04 LOCMOS HE4000B Logic
    Package Outlines/Information HEF, HEC

    HEF4040B
    MSI
    12-stage binary counter
    Product specification January 1995
    File under Integrated Circuits, IC04
    Philips Semiconductors Product specification

    HEF4040B
    12-stage binary counter
    MSI

    DESCRIPTION
    The HEF4040B is a 12-stage binary ripple counter with a
    clock input (CP), an overriding asynchronous master reset
    input (MR) and twelve fully buffered outputs (O0 to O11).
    The counter advances on the HIGH to LOW transition of
    CP. A HIGH on MR clears all counter stages and forces all
    outputs LOW, independent of CP. Each counter stage is a
    static toggle flip-flop. Schmitt-trigger action in the clock
    input makes the circuit highly tolerant to slower clock rise
    and fall times.

    Fig.1 Functional diagram.

    PINNING
    CP clock input (HIGH to LOW edge-triggered)
    MR master reset input (active HIGH)
    O0 to O11 parallel outputs

    APPLICATION INFORMATION
    Some examples of applications for the HEF4040B are:
    • Frequency dividing circuits
    • Time delay circuits
    Fig.2 Pinning diagram. • Control counters

    FAMILY DATA, IDD LIMITS category MSI


    See Family Specifications
    HEF4040BP(N): 16-lead DIL; plastic
    (SOT38-1)
    HEF4040BD(F): 16-lead DIL; ceramic (cerdip)
    (SOT74)
    HEF4040BT(D): 16-lead SO; plastic
    (SOT109-1)
    ( ): Package Designator North America

    January 1995 2
    Philips Semiconductors Product specification

    HEF4040B
    12-stage binary counter
    MSI

    Fig.3 Logic diagram.

    AC CHARACTERISTICS
    VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

    VDD TYPICAL EXTRAPOLATION


    SYMBOL MIN. TYP. MAX.
    V FORMULA
    Propagation delays
    CP → O0 5 105 210 ns 78 ns + (0,55 ns/pF) CL
    HIGH to LOW 10 tPHL 45 90 ns 34 ns + (0,23 ns/pF) CL
    15 35 70 ns 27 ns + (0,16 ns/pF) CL
    5 85 170 ns 58 ns + (0,55 ns/pF) CL
    LOW to HIGH 10 tPLH 40 80 ns 29 ns + (0,23 ns/pF) CL
    15 30 60 ns 22 ns + (0,16 ns/pF) CL
    On → On + 1 5 35 70 ns note 1 (0,55 ns/pF) CL
    HIGH to LOW 10 tPHL 15 30 ns note 1 (0,23 ns/pF) CL
    15 10 20 ns note 1 (0,16 ns/pF) CL
    5 35 70 ns note 1 (0,55 ns/pF) CL
    LOW to HIGH 10 tPLH 15 30 ns note 1 (0,23 ns/pF) CL
    15 10 20 ns note 1 (0,16 ns/pF) CL
    MR → On 5 90 180 ns 63 ns + (0,55 ns/pF) CL
    HIGH to LOW 10 tPHL 40 80 ns 29 ns + (0,23 ns/pF) CL
    15 30 60 ns 22 ns + (0,16 ns/pF) CL
    Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
    HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
    15 20 40 ns 6 ns + (0,28 ns/pF) CL
    5 60 120 ns 10 ns + (1,0 ns/pF) CL
    LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
    15 20 40 ns 6 ns + (0,28 ns/pF) CL

    January 1995 3
    Philips Semiconductors Product specification

    HEF4040B
    12-stage binary counter
    MSI

    VDD TYPICAL EXTRAPOLATION


    SYMBOL MIN. TYP. MAX.
    V FORMULA
    Minimum clock 5 50 25 ns
    pulse width; HIGH 10 tWCPH 30 15 ns
    15 20 10 ns
    Minimum MR 5 40 20 ns
    pulse width; HIGH 10 tWMRH 30 15 ns
    15 20 10 ns see also waveforms
    Recovery time 5 40 20 ns Fig.4
    for MR 10 tRMR 30 15 ns
    15 20 10 ns
    Maximum clock 5 10 20 MHz
    pulse frequency 10 fmax 15 30 MHz
    15 25 50 MHz
    Note
    1. For other loads than 50 pF at the nth output, use the slope given.

    VDD
    TYPICAL FORMULA FOR P (µW)
    V
    Dynamic power 5 400 fi + ∑ (foCL) × VDD2 where
    dissipation per 10 2 000 fi + ∑ (foCL) × VDD2 fi = input freq. (MHz)
    package (P) 15 5 200 fi + ∑ (foCL) × VDD2 fo = output freq. (MHz)
    CL = load cap. (pF)
    ∑ (foCL) = sum of outputs
    VDD = supply voltage (V)

    January 1995 4
    Philips Semiconductors Product specification

    HEF4040B
    12-stage binary counter
    MSI

    Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths.

    January 1995 5

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