1

CHAPTER 1

INTRODUCTION

As a massive amount of data transmission is required in modern

digital systems, a high speed serial link interface is widely employed. Since it
requires a less power and area than the conventional parallel interface.
Moreover with the growing bandwidth requirement, low power and area
efficient designs became the most important requirement. The transmitter
consists of i) serializer ii) predriver iii) output driver. Initially, the transmitter
was designed with MOSFET for copper on chip serial link interconnect.

As the VLSI technology continues to scale increases the integrated

circuit density and performance. Scaling decreases the device and
interconnect dimensions. Initially, transistor scaling shows performance
improvement but it degrades the interconnect performance. Interconnect
scaling results more delay and power dissipation. Various techniques were
proposed to alleviate these issues in interconnect. When the integrated circuit
scales below 45nm, material level issues like source-drain tunnelling, surface
scattering arises in transistor and electromigration and electroscattering in
interconnect.

This will force the researchers to find an alternate material for

transistor as well as interconnect. Various researches propose CNT as an
alternate material for both transistor and interconnect because it can be act as
metal and semiconductor depending upon its chirality vector.

By considering the indices (n, m) shown in Fig. 1, the nanotube is metallic if

n = m or n-m = 3i where i is an integer. Otherwise, the tube is
 2

semiconducting. CNTFETs are the FETs that make use of semiconducting

CNTs as channel material between two metal electrodes that act as source and
drain contacts. The operation principle of CNTFET is similar to that of
traditional silicon devices. As shown in Fig.2, this three (or four) terminal
device consists of a semiconducting nanotube, acting as conducting channel,
bridging the source and drain contacts. The device is turned On or off
electrostatically via the gate.

Fig 1.1 unrolled graphite sheet Fig 1.2 Cross section view of CNTFET

In this project we are going to design the “CNTFET based

transmitter for serial link interconnect”. CNTFET=CARBON NANO
TUBE FIELD EFFECT TRANSISTOR.

In transmitter circuit both voltage and current mode techniques are

used to transmit the signals. In order to achieve low swing, Less power
dissipation and propagation delay we propose pseudo NMOS multiplexing
based current mode and voltage mode driver. To achieve area and cost
requirement we propose SIPF(Single P-CNTFET) and STPF(Stacked P-
CNTFET) based Transmitter circuit. This Transmitter circuit implemented
by Hspice simulator using 180nm technology.
 3

1.1 SERIAL LINK TRANSCEIVER

A high speed link has four parts:

1. A transmitter that converts the bits to an electrical signal capable of

propagating on a long wire.

2. The long wire itself.

3. A receiver that converts the signal energy of the wire back to bits.

4. Timing recovery circuit that compensates for the time delay of the wire.

A transmitter sends the data as analog quantities or symbols. The analog

values are simply either a HIGH level or LOW level to represent a single bit
known as non-return-to-zero (NRZ). For example, in an optical system, the
levels are different amounts of optical power. For electrical systems, these
levels are different signal voltages. The duration of each HIGH or LOW
symbol is the bit time. The difficulty in a transmitter design is to maintain
clean signal levels while transmitting high data rates.

Fig.1.3 Serial Link Transceiver

The channel is the medium on which the data is propagated. This

medium can physically be an optical fiber, a coaxial transmission line, an
unshielded twisted-pair, a printed circuit board (PCB) trace, or the chip
package. The medium can attenuate or filter the signal, and introduce noise.
To achieve very high data rates, a channel with low attenuation and distortion
 4

at high frequencies is necessary to reduce the noise and filtering . On the

receiver side, inverters are replaced by sensitive receiver amplifiers to reduce
the required signal swing and achieve a higher bit rate. This project not deals
with receiver.

1.2 EFFECT OF TECHNOLOGY SCALING AND

INTERCONNECT
For over 30 years, the feature size of CMOS technology has shrunk to
dimensions into the nanometre region now-a-days. As a result of this
continuous scaling, higher circuit speeds, lower power and larger packing
densities of transistors are achieved.

The scaling of technology also affects interconnects. Both the thickness

of the metal layers itself and the thickness of the oxide between the metal
layers decrease with scaling. Also, the minimum width of an interconnect and
the minimum spacing between two interconnects decrease.

When looking at the scaling of serial link interconnects, it is important

to distinguish between local and global interconnects .The concept is shown
in fig 1.4.

Fig 1.4 Scaling of Local and Global Interconnects

Under scaling, a circuit with the same functionality will be smaller in a new
technology. Interconnect of this circuit will also become shorter and these
 5

scaled interconnects are called local interconnects. However, as more

functionality is packed on a chip, the total size of the chip remains roughly the
same under scaling. Next to local interconnects, there will also be
interconnects that span the entire chip. These interconnects do not scale in
length and are called global interconnects.

1.3 LOGIC AND WIRE DELAY

Improvements in VLSI circuit density and performance have been
achieved by scaling down transistors. Consequence of the transistor scaling,
the number of transistors on each chip is increasing is shown in Fig.1.3,
results in high speed of operation, their density is also increasing. This results
in adding extra functionality on the chip. A wiring hierarchy is typically used
that places the shorter wires nearer to the silicon surface and increasing longer
wires on higher layers. Fig. 1.6 shows a cross-section of an advanced
hierarchical wiring scheme using copper metallization . The lower levels of
interconnect are thinner and are used in local routing, which is used to
connect transistors. Intermediate layers are of medium thickness and used for
semi global routing that is used to connect functional blocks. Finally, the top
layers are the thickest and are used for global routing, which is used for
routing the data, clock and power signals.
 6

Fig 1.5 Moore’s Law

Fig 1.6 Sample Cross-Section of Hierarchical Wire Scaling.

The International Technology Roadmap for Semiconductors (ITRS)

illustrates the growing problem of global interconnect delays is shown in Fig.
1.7 which becomes significant for many applications such as buses used
between cache memories and Processors.

Fig 1.7 ITRS 2001 Predictions for Logic and Wire Delays

Fig.1.5 shows that as technology continues to scale, the logic delays

decrease due to faster transistors. At the same time, local interconnect delays
similarly improve because the physical size of circuit blocks decrease, and the
local interconnect spans shorter distances. On the other hand, the global
 7

interconnect delays rise with technology scaling for one of two different
reasons. They are

(i) The overall chip size increases so that interconnects need to span
longer distances.

(ii) Even if chips do not become larger, the increased complexity of

circuits requires an increased density of interconnects. This is achieved by
reducing the cross sectional area of wires, which negatively impacts the
resistance, and decreasing wire spacing, which adversely impacts the
capacitance. Delay of this on chip global interconnects increase quadratically
with the length

RC
τ= (l total )2
2 (1.1)

Where, R and C are resistance and capacitance per unit length. L total
length of the interconnect.
 8

CHAPTER 2

LITERATURE SURVEY

Young-Hoon Song, et al (2012).,presents a Low-power (LP) high-speed

serial I/O transmitters which include equalization to compensate for channel
frequency-dependent loss are required to meet the aggressive link energy-
efficiency targets of future systems. This brief presents an LP serial-link-
transmitter design that utilizes an output stage which combines a voltage-
mode driver, which offers low staticpower dissipation, and current-mode
equalization, which offers low complexity and dynamic-power dissipation.
The utilization of current-mode qualization decouples the equalization
settings and termination impedance, allowing for a significant reduction in
predriver complexity relative to segmented voltage-mode drivers. Proper
transmitter series termination is set with an impedance control loop which
adjusts the on-resistance of the output transistors in the driver voltage-mode
portion. Further reductions in dynamic-power dissipation are achieved
through scaling the serializer and local clock distribution supply with data
rate. Fabricated in a 1.2-V 90-nm LP CMOS process, the transmitter supports
an output swing range of 100–400 mVppd and up to 6 dB of equalization and
includes output-duty-cycle control. The transmitter achieves 6-Gbit/s
operation at 1.26-pJ/bit energy efficiency with 300-mVppd output swing and
3.72-dB equalization.

Koon-Lun Jackie Wong, et al (2004)., presents a 3.6-Gb/s 27-mW

transceiver for chip-to-chip applications. A voltage-mode transmitter is
proposed that equalizes the channel while maintaining impedance matching.
 9

A comparator is proposed that achieves sampling bandwidth control and

offset compensation. A novel timing recovery circuit controls the phase by
mismatching the current in the charge pump. The architecture maintains high
signal integrity while each port consumes only 7.5 mW/Gb/s. The entire
design occupies 0.2 mm2 in a 0.18- m 1.8-V CMOS technology.

Saravanan Rajapandian, Zheng Xu, et al (2005).,presents an energy-

efficient means to achieve on-chip dc–dc conversion for digital CMOS
circuits. The approach uses balanced voltage islands running at fractions of
the off-chip supply voltage. Charge “discarded” by one domain is “recycled”
to supply energy for another. When the domains are ideally balanced, all the
energy dissipated by electrons in “dropping” to lower potentials is used for
active computation. We describe the design and measurement of a prototype
system in a 0.18um CMOS process that provides active on-chip voltage
regulation and controlled dc–dc conversion with this technique.

Ming-Ju Edward Lee, et al (2000).,presents a 4-Gb/s I/O circuit that fits in

0.1-mm of die area, dissipates 90 mW of power, and operates over 1 m of 7-
mil 0.5-oz PCB trace in a 0.25um CMOS technology. Swing reduction is used
in an input-multiplexed transmitter to provide most of the speed advantage of
an output-multiplexed architecture with significantly lower power and area. A
delay-locked loop (DLL) using a supply-regulated inverter delay line gives
very low jitter at a fraction of the power of a source-coupled delay line-based
DLL. Receiver capacitive offset trimming decreases the minimum resolvable
swing to 8 mV, greatly reducing the transmission energy without affecting the
performance of the receive amplifier. These circuit techniques enable a high
level of I/O integration to relieve the pin bandwidth bottleneck of modern
VLSI chips.

Efraim Rotem , et al (2005)., presents a A generalized theoretical analysis of

an ac-coupled fiber-optic burst-mode receiver is presented. This receiver is
 10

designed to operate in optical burst-switching networks using dc-balanced

data coding such as 8B10B. Analytic expressions for the recovery time are
derived as a function of the system dynamic range, power penalty, and data
coding format. The theoretical calculations are verified with a detailed
simulation. It is shown that locking time of the order of nanoseconds can be
achieved with commercially available ac-coupled receivers. The burst-mode
receiver can adapt to large (>10 dB) amplitude variations in 30 ns with a
power penalty of 2 dB at 12.5 Gb/s. An overall optimization of the
transmitter-receiver link-setup time is performed for an optical burst-
switching network based on tunable laser transmitters. The dark interval
during laser tuning (50 ns) is shown to have a beneficial impact on the
receiver’s response time, effectively reducing its locking time to a few
nanoseconds, thus resulting in an overall link setup time of about 50 ns,
limited by the laser’s tuning time.

Vladimir Bratov, et al (2006)., This paper presents a new detailed analysis

of low-voltage differential signaling (LVDS) output buffers that are intended
for use in high-speed integrated circuits. Three theoretically possible
architectures of a LVDS output driver are discussed in rigorous detail,
resulting in the recognition of the most power-conserving circuit
configuration. An innovative realization of this identified low-power
architecture is presented in this paper along with computer simulation results
and test lab measurement data. The novel LVDS driver is designed using a
unique hetero-junction bipolar transistor structure. Computer simulation
results show total current consumption of 6.3 mA for the bipolar driver at a 1-
GHz clock frequency while operating from a positive supply voltage between
1.7 and 3.3 V, as well as demonstrate full stage compliance with all the
requirements of the IEEE 1596.3–1996 standard. The presented version of the
buffer was utilized in a multiplexer/demultiplexer chip set that was fabricated
 11

in a modern 50-GHzft SiGe technology. Test results of the LVDS output

buffer taken from five different chip samples reveal high-quality output.

CHAPTER 3

TRANSMITTER ARCHITECTURES

In high speed serial link transceiver, transmitter converts the digital

input data into current or voltage. The signal is transmitted from transmitter to
receiver through interconnect link. This link is terminated with a termination
resistor at the receiving end to avoid reflection. The receiver is the circuit that
amplifies and samples the waveform while an additional circuit, the timing
recovery circuit properly places the sampling strobe. It produce the correct
digital data to the signal received through interconnect. Various signalling
techniques are used to transmitter to receiver through interconnect.

3.1. SIGNALLING TECHNIQUES

Depending upon the physical arrangement of the wire channels of data

links, electrical signalling schemes for data transmission over wire channels
can be classified into single ended, fully differential. In an effort to reduce the
intrusion of repeater logic, reduce power dissipation, and potentially drive
longer distances, differential low swing signalling may be employed. They
can also be categorized into voltage mode and current mode signalling
schemes on the basis of the carriers of data links.

3.1.1 Single-Ended Signaling

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Fig.3.1 Single-Ended Signaling System

Single-ended transmission is performed by using one signal line for each

information channel and a common ground return path shared among
numerous information channels.

Advantages

1. Simplest method and most commonly used for transmitting electrical

signals over wires.
2. Signal is transferred via single channel.
3. Less expensive and less wires only needed for transmitting multiple
signals.
4. N signal present means N+1 wires only needed.

Disadvantages

1. Poor noise immunity-lacks the ability to reject the noise

2. Sharing the current by same conductor- crosstalk occur.

Fig.3.2 Noise in single ended signaling

 13

3.1.2 Differential Signaling

Differential transmission addresses many of the shortcomings of single-

ended solutions by using a pair of signal lines for each information channel.
Fig3.3 shows an electrical schematic diagram of a differential transmission
system. The differential driver uses a pair of complementary outputs to
indicate the state transmitted. The differential receiver detects the voltage
difference between the signal pair, rather than relative to ground, to determine
its output state.

Fig.3.3 Differential Signaling System

1. Method for electrically transmitting information using two

complementary signals.
2. Differential signals are transferred via two adjacent channels.
3. Each signal has opposite logic levels
4. Examples: Printed circuit boards (PCB),Twisted pair, Ribbon
cables.

Advantages

a) Large Signal Swing

1. Signal=positive signal-negative signal

2. Threshold=(positive signal+ negative signal)/2

b) Common Mode Noise Rejection

1. Noise usually affects both positive and negative channels

 14

2. Subtraction rejects common mode noise

Fig 3.4 Noise removed in Differential Signalling System

3.1.3 Voltage Mode Signaling

Fig 3.5 Voltage Mode Signaling.

The signal conveyed to the channel by the driver is the output voltage of
the inverter. It is determined from

dv o ( t ) dv o ( t )−V DD
CL + −C L V OL ∂ ( t )=0(Rising edge ) (3.1)
dt Rp

dv o ( t ) dv ( t )
CL −C L V OH ∂ ( t ) + o =0 ( Falling edge ) (3.2)
dt Rn

where Rn and Rp are the channel resistance of the NMOS and PMOS
transistors in the triode, respectively, CL is the load capacitance of the driver,
VOL and VOH are the voltage of Logic-0 and Logic-1 states, respectively,
C L V OL ∂ ( t )∧¿ C L V OH ∂(t)quantify the effect of the initial voltage of the load

capacitor at the onset of charging and discharging.

 15

3.1.4 Current Mode Signaling

That current mode signalling offers the advantages of low supply

voltage requirement, a small propagation delay, superior signal integrity, low
switching noise, and low power consumption. The single-ended signalling
scheme cannot reject the noise coupled to the channels. In addition, the
channels of data links with single ended signalling have a large inductance
and are sensitive to inductive interferences from other sources.

Fig 3.6 Current Mode Signaling.

Fully differential signalling effectively rejects the noise coupled to the

channels at the cost of two conductors per channel. Data links with fully
differential signalling have a small channel inductance and a low
electromagnetic emission. At the receiver side, together with the drawback of
voltage-mode signalling, limit data rates. Current mode incremental
signalling, on the other hand, achieves high data rates by utilizing the
advantages of the fully differential and current mode signalling schemes. Data
links with current mode incremental signalling have a small channel
inductance and a low level of electromagnetic emission.
 16

In below table 3.1 Shows that the comparison of voltage mode and
current mode signaling techniques.

Table 3.1 Difference between the Voltage mode and Current mode Signaling

VOLTAGE MODE CURRENT MODE

It provides high input impedance It provides low input impedance

It consumes less power It consumes more power
High voltage required Swing Low swing and achieves wide bandwidth
Low power consumption at high frequency
- Low cross talk and switching noise, High
speed

3.2 ARCHITECTURE OF THE TRANSMITTER

The main function of serial link transmitters includes serialization of

parallel data, pre-emphasis to compensate for the high-frequency loss of wire
channels, conveying either voltages or currents of a sufficiently large
amplitude and a proper slew rate to channels, and providing a matching
impedance to minimize the reflection at the near end of the channels.
Serialization that converts a parallel bit stream into an analog wave-form is
achieved using multiplexers. Multiplexers are the key to relax the frequency
of on-chip clocks .

The serial link transmitter consist of three parts:

 Serializer (Multiplexer)

 Pre driver

 Output driver
 17

Fig 3.7 Transmitter Architecture.

3.2.1 Types of Multiplexers

The main function of serial link transmitters includes serialization of

parallel data, pre-emphasis to compensate for the high frequency loss of wire
channels, conveying either voltages or currents of a sufficiently large
amplitude and a proper slew rate to channels, and providing a matching
impedance to minimize the reflection at the near end of the channels. The
selection pulses of the multiplexers must be non-overlapping and their
duration must be no larger than the symbol time Tsym.

A high multiplexing speed can be achieved by,

(i) Reducing the capacitance of the multiplexing node

(ii) Lowering the voltage swing of the multiplexing node and

(iii) Utilizing advanced circuit techniques, such as inductive peaking, to

speed up the charge and discharge of the multiplexing node.

a) Transmission Gate Multiplexer

Fig 3.8 Transmission Gate Multiplexer

 18

The widely used transmission gate multiplexers shown in Fig 3.8

achieve a high multiplexing speed by utilizing the advantage of the low and
nearly constant equivalent channel resistance of transmission gates. The time
constant of the multiplexing node is determined by the equivalent resistance
of transmission gates RTG and the capacitance at the multiplexing node.
Transmission gate multiplexers are not suitable for applications where the
symbol time T symis less than 4FO4. The main reason for this is that RTG is not
small. To lower R y the transmission gates must be made wide. The
capacitance of the gates, however, will increase accordingly, resulting in no
net reduction in the propagation delay, as is evident from Fig 3.8

b) Pseudo NMOS Multiplexers

Multiplexing speed can be improved by using the pseudo NMOS based

multiplexers shown in Fig 3.9 By assuming that the pull-up PMOS transistor
is in the triode in both the pullup and pulldown operations, the time constant
can be estimated from

T ≈ C A R p , low high ¿ C A ( Rn|R p ) ,high ¿ low ¿

{ (3.1)
¿

where Rn and Rp are the effective pull-down and pull-up resistances,

respectively, and CA is the capacitance of the multiplexing node. Because

V OH =V DD , (3.2)

Rn
V OL = V (3.3)
R n+ R p DD ,

The pull-up PMOS transistor must be weakly sized, i.e. in order to

reduce VOL in eqn(3.4) subsequently a large output voltage swing at the
output, as shown in Fig.3.9. This is, however, at the cost of an increase in the
low-to-high propagation delay TPLH.
 19

Fig.3.9 Pseudo NMOS multiplexer

c) Current-Steering Multiplexer

Multiplexers that are based on current steering logic circuits, draw a

constant current from the supply voltage. They neither generate switching
noise nor inject noise to the substrate. Further current steering logic circuits
consume less power as compared with complementary static logic circuits at
GHz. Because the fan-in of current-steering multiplexers is small, typically 2,
to implement multiplexers with a large fan-in, multiple stages are needed.

As pointed out earlier that the design of these multiplexers is greatly

affected by the difficulty encountered in generating a high frequency on chip
clock with stringent timing requirements and lining up the inputs of these
multiplexers at Gbps data rates.

d) Yang’s Multiplexer

The speed of multiplexers can be increased by moving the multiplexing

node to the near end of the channel to take the advantage of the low
impedance of the channels, typically 50ohms, as shown in Fig.3.10 .
 20

Fig.3.10 Output Multiplexed Architecture

e) Current Mode Multiplexer

Multiplexing speed can also be increased by multiplexing in the current

domain where the output of the multiplexers are currents rather than voltages.
A high multiplexing speed in this case is obtained by lowering both the
impedance and the voltage swing of the multiplexing node. Consider the
pseudo NMOS and current-mode multiplexers shown in Fig.3.11.

Fig 3.11 Current Mode Multiplexer

The impedance of the multiplexing node of the pseudo-nMOS

multiplexer is given by R pin the pullup operation and Rn\\ R p in the pull-down
operation approximately, whereas that of the current mode multiplexer is

1 1
∨¿ Rn in the pull-down operation and i in the pullup operation. The
gm gm

voltage swing of the pseudo NMOS multiplexer was given in

eqn(3.6)whereas that of the current-mode multiplexer is obtained from

∆ v=J ( g1 − g1 ∨¿ R )
m m
n (3.4)

Both the voltage swing and the impedance of the multiplexing node of
the pseudo NMOS multiplexer are larger than those of the current mode
 21

multiplexer. It is seen that the rising time is much larger as compared with
the falling time, mainly due to the small width of the pullup PMOS transistor.
Also observed is that both decrease monotonically with the increase in the
size of the pull up PMOS transistor.

3.2.2 Types of Drivers

The main functionality of drivers is to convey a voltage or a current of

sufficiently large amplitude and slew rates to channels. Drivers with a low
output impedance make their appearance as voltage sources and are referred
to as voltage mode drivers. Drivers with a high output impedance behaves as
current sources and are called current mode drivers. Traditional voltage mode
signalling becomes a major bandwidth bottleneck when data rates approach
multiple Gb/s and the supply voltage is aggressively scaled down. This is
because not only the rising and falling times of the voltage of each node of the
voltage mode transmitters are large, mainly due to the large voltage swing
requirement of voltage-mode circuits.

a) Inverter Drivers

The configuration of static inverter-based drivers is shown in Fig.3.12.

Inverter drivers fall into the category of voltage-mode drivers. Impedance
matching at the output node is achieved with a serial termination resistor at
the near end of the channel. Due to the full voltage swing nature of inverters,
the rise and fall times cannot be improved by reducing the voltage swing.
Increasing the transistor size, although reduces the output impedance of the
inverter Z out subsequently increases the output current I , loads the preceding
stage, resulting in no net speed improvement. In addition, because Z out varies
with the mode of operation of the inverter, a reflection at the near end of the
channel exists. Because the input impedance of the load inverter is
significantly larger than the channel characteristic impedance Z 0, a total
refiection at the far end of the channel exists.
 22

Fig 3.12 Static Inverter Driver

b) Low-Voltage Differential-Signalling Drivers

Low voltage differential signalling or bipolar current mode signalling is

a widely used signalling scheme for high speed serial links. Fig.3.14. shows a
typical configuration of LVDS drivers.

Fig 3.13 Low Voltage Differential Signalling Drivers

A load resistor at the far end of the channel provides both impedance
matching and current to voltage conversion. As compared with open drain
drivers whose output current always flows in one direction (unipolar
signalling), LVDS drivers convey two currents of equal amplitude but
opposite polarity to the channel (bipolar signalling), minimizing the
electromagnetic interference exerted from the channel to neighbouring
devices. A main drawback of LVDS drivers is the need for four transistors
stacked between the supply and ground rails makes them less attractive for
applications where only low supply voltages are available. The minimum
supply voltage of the driver can be estimated from
 23

V DD ,min =2 V sat +2 V DS ,min + Z T I where VDS,min is the minimum voltage of

drain-source of the four switching transistors that support current I when

biased in the triode.

c) Voltage Mode Driver

` Recently, a voltage mode driver has become a popular choice due to

better power efficiency .With the advanced CMOS technology, the use of the
voltage-mode driver has become more attractive for a multi-gigabit-per-
second transceiver with its increased operation speed. Here the power
consumption is also low.

Fig 3.14 Voltage mode driver

Advantages
1. It provides high input impedance
2. It consumes less power

Disadvantages
1. The overhead of designing a voltage regulator to control the output
swing”.
 24

2. It increase the design complexity.

3. It is an unavoidable choice for “LP DESIGN”
4. More Delay
5. High voltage Swing
d) Current Mode Driver

It is the Source terminated current mode driver with “unidirectional”

signal current flow. It is used in serial links. It is suitable for achieving high
bandwidth signalling with insensitivity to power supply noise. Here the
output swing is controlled by “adjusting the current flowing through the load
resistor”.

Fig 3.15 current mode driver

Advantages
1. It provides low input impedance
2. Less delay
3. Low swing and achieves wide bandwidth
4. Low power consumption at high frequency
5. Low cross talk and switching noise
6. High speed
3.3 MOSFET BASED TRANSMITTER ARCHITECTURE
The Existing transmitter is implemented by 180nm CMOS
Technology. As complementary metal-oxide semiconductor (CMOS)
continues to scale down deeper into the Nano-scale, various device non-
 25

idealities cause the I-V characteristics to be substantially different from well-

tempered metal-oxide semiconductor field-effect transistors (MOSFETs).
3.3.1 Overview of MOSFET
Metal-oxide-semiconductor field-effect transistor, in short is commonly
known as MOSFET, was first invented around 1964. With a continuous
reduction in the MOSFET size, especially scaling its gate length through
Moore’s Law application , the integrate chip will be packed with a large
number of complex circuitries .

Figure 3.16 The gate of the transistors Fig 3.17 The number of transistors

plotted against the calendar year packed within a single integrated

through the forecast of Moore’s Law. chip for the past 40 years

(a) First silicon IC in the history (b)IntelPentium4

(year 1959) mirco processor (year 2000)
 26

Figure 3.18 Evolution of the IC integration level: (a) First IC by

Fairchild Semiconductor with 4 transistors [a]. (b) Intel Pentium 4
microprocessor with 50 million transistors [b].

Table 3.2 Linear Scaling Rules

A MOSFET is a semiconductor device with three terminals: gate, drain

and source. In the gate terminal, it is a metal electrode that will control the
flow of the current from the source terminal to the drain terminal. In order to
permits the current to flow, the gate voltage requires to be higher than the
threshold voltage. Usually the source is grounded and a small amount of drain
voltage is applied .
 27

Fig 3.19 MOSFET diagram with gate, drain and source

The trans conductance (gm), which is referred to as the ratio between the
current output to the voltage input, is an important property for the FETs.

gm 1
≈ (3.5)
2 π C g L g2

where C g is the capacitance of the gate per unit area.

From the equation above, as the gate length is reduced, the MOSFET will
get faster and increases the gain.

The methodology of MOSFET operations are as follows:

 When gate voltage is increase above the threshold voltage, an

inversion channel is created, causing electrons to flow from the
source terminal to drain terminal. The current will flow from drain
terminal to source terminal.
 A layer of oxide behaves as an insulator causing no current to flow
to the gate terminal.
However by reducing the gate length of the transistors, parasitic effects
will be induced and physical challenges of scaling the size while maintaining
the MOSFET operation are two main key limitation factors.

Following are the effects that would affect the internal performance of
MOSFET when the process of scaling occurs are:
 28

a. Tunneling effect
b. Short channel effect
c. Threshold voltage
d. Oxide thickness
e. Ballistic Transport

Limitations that will occur when the process of scaling occurs are
theoretical limitations, economical limitations and technology limitations.

i) Limitations of MOSFET
As the possible effects and limitations of MOSFET will be discussed
in this section.

a. Tunneling effect
In an ideal case, transistors are being separated so as to ensure one
transistor’s operation will not affect the other transistor’s performances. A
material such as oxide can be used to acts as a barrier to prevent undesired
situation to occur. In small electronics devices that measures as small as in
nanometers, this barrier’s thickness is also measured in nanometers. With
such small thickness, the chances of carrier migration might occur.

Fig 3.20 Two types of tunneling effects

b. Short channel effect

 29

With the channel of the MOSFET has been reduced, it introduces

current leakages known as short channel effect. An example of current
leakage mechanism is commonly known as punch through. When there is a
case of channel length modulation in the MOSFET, the depletion layers
around the drain and source regions will then merge into a single depletion
region. The field which lies beneath the gate then becomes totally dependent
on the drain-source voltage. This undesired effect causes an increasing current
with increasing drain-source voltage. When this effect occurs, the output
conductance increases rapidly and the maximum operating voltage will be
limited for the MOSFET.

Fig 3.21 An example of short channel effect called "Punch through".

c. Threshold voltage
When current begins to flow in the channel, voltage at the gate is
known as threshold voltage. In the graph plotted below, it shows how the
reduction of channel length affects the threshold voltage.

Fig 3.22 Relationship between threshold voltage and channel length .

 30

In Figure 7, it shows a relationship between the threshold voltage (V TH )

and channel length ( LCH ). From the graph, it clearly shows that the reduction
of channel length below 15 nm, the threshold voltage also decreases. At 5 nm
channel length the threshold voltage reduces significantly. When the channel
length has been increased more than 15nm, the threshold voltage remains
relatively constant.

d. Oxide thickness
When the MOSFET has been scaled downsized, both the gate-oxide
thickness and voltage level will also be reduced. In order to ensure the gate
terminal of the MOSFET will have more control than the drain, it is
recommend having the gate oxide thickness proportional with the channel
length .

3.4. CNTFET BASED TRANSMITTER ARCHITECTURE

3.4.1 Introduction to CNTFET
Carbon Nanotube Field Effect Transistors (CNTFET) are promising
Nano-scaled devices for implementing high performance very dense and
low power circuits. A Carbon Nanotube Field Effect Transistor refers to a
FET that utilizes a single CNT or an array of CNT’s as the channel material
instead of bulk silicon in the traditional MOSFET structure.
The core of a CNTFET is a carbon nanotube. CNTFET is the most
promising technology due to three reasons: first, the operation principle and
the device structure are similar to CMOS devices and it is possible to reuse
the established CMOS design infrastructure. Second, it is also possible to
reuse CMOS fabrication process. And the most important reason is that
CNTFET has the best experimentally demonstrated device current carrying
ability to date.
 31

Fig 3.23 Circuit for CNTFET

a) Carbon Nanotubes (CNT)

Carbon nanotubes (CNTs) are hollow cylinders composed of one or
more concentric layers of carbon atoms in a honeycomb lattice arrangement.
Multiwalled nanotubes (MWCNTs) were observed for the first time in
transmission electron microscopy (TEM) studies by Iijima in 1991,while
single-walled nanotubes (SWCNTs) were produced independently by Iijima
and Bethune in 1993.
A graphene sheet is a layer of single three-dimensional graphite which
it’s carbon atoms will form three σ (sigma) bonds in plane in a configuration
of sp2, while the other p zorbital is perpendicular to the graphene plane,
making a π (pi) covalent bond. These σ states will form covalent bonds with
their surround neighbors and hence will give rise to the lattice structure of the
graphene. In Figure 8, 2 p z is the orbital and is weakly bonded, making it easy
to hop between the neighboring atoms. This state is known as π state and is
aligned in z -direction.
 32

Fig 3.24 Energy level of Carbon.

A graphene lattice has 2 atom basis, which is normally known as A and

B atoms, having a lattice vector of

a a
á 1=( √ 3 , 1) and a´2=( √3 ,−1) (3.6)
2 2

where a=√ 3 acc =2.46 Å is the lattice constant and a cc=1.42 Å which refers to
the bond distance for graphene.

Fig 3.25 Lattice vectors of a 2D graphene sheet .

A graphene structure can be determine by it’s chirality. It can be

summarised as follows:

a. A chirality of (n , m) where m=0 forms an armchair-edge

graphene which can be metallic or semiconducting properties.
b. A chirality of (n , m) where n=m forms a zigzag-edge graphene
which is metallic in properties.
 33

Fig 3.26 Zigzag and armchair structure of graphene

When a honeycomb lattice of a piece of graphene sheet is being rolled into

a cylinder, it forms a carbon nanotube, or CNT.

Fig 3.27 Rolling of graphene to a carbon nanotube

The diameter of carbon nanotube the can be expressed as,

(3.7)

where a=0.142nm.refers as the distance between the carbon atoms. n,m

represents the chirality indices. the band gap of carbon nanotube is
 34

(3.8)

The threshold voltage of the CNFET is equal to half of the band gap and
can be expressed as:

(3.9)

Carbon nanotube can be classified into 2 main categories,

i) Single-walled CNTs (SWCNT)

SWCNTs are several μms in length, typically will be up to 100μm. The
diameter is approximately 1 to 2 nm . They can be classified as armchair,
zigzag and chiral structure.

Fig 3.28 Lattice structure of different types of CNT

ii) Multi-walled CNTs (MWCNT)

With a number of concentration cylinders of hollow carbon nanotube of
different radius, a MWNT is composed.
 35

Fig 3.29 A typical structure of a MWCNT

Chiral vector is a common term used to represent the way grapheme

sheet is rolled up to form a nanotube. It is represented by two integer numbers
n and m and is normally define as (n,m) . With this, its circumferential
direction can be formulated as:

c⃗ =n á1 +m a´2 (3.10)

where á 1 and a´2 are the vectors of the graphene sheet

When m=0 , the nanotube are known as zigzag. When n=m , the
nanotube are known as armchair. Else, they are called chiral. Depending on

the chiral vector (n,m) , a SWNT can be either a semiconductor or metallic

material. This property is due to a particular band structure of the grapheme
sheet and the wrapping in a cylindrical shape that leads to the existence of
cyclic boundary conditions. In practical SWNT can possess metallic
characteristic if n−m is an integer multiple of 3. If not, it will be a
semiconductor .
 36

Fig 3.30 Metallic and semiconducting properties of a CNT

In Figure 3.31, the graph on the left indicates the one-dimensional band
structure of the type of carbon nanotube. Understanding of band structure is
important as it allows the investigation of what is the range of energy that an
electron will travel in the carbon nanotube characteristic, especially in the
terms of electronics and physics. Figure 3.32 shows a simple illustration of
band gaps.

Fig 3.31 Illustration of band gap

 37

b) Carbon Nanotube FET (CNTFET)

To build a CNTFET, single walled carbon nanotubes (SWCNTs) are used
due to their semiconducting and metallic properties and its ability to carry
high current. It has already proven that carbon nanotubes can carry current
density of the order 10µA/nm². This is much higher as compared to standard
metal wires which could carry 10nA/nm².. CNTFETs can have almost a near-
ballistic transport characteristic because the mean free path for electrons in
SWCNTs exceed close to 1 µm. This will results in a much higher speed
device as compared to silicon MOSFETs. These mention research concludes
that carbon nanotubes have a promising for the future of Nano-electronics due
to their superior electrical characteristic.

In structural look, the CNTFET looks like a MOSFET. The only change in
that he silicon channel is being replaced by carbon nanotubes. Improvements
such as orientations and arrangements of the carbon nanotube have been
constantly being research on so as to have a better end result. There are 2
main type of structure, they are known as back-gate CNTFET and top-gate
CNTFET. These two gated devices are commonly known as geometry
dependent CNTFET.

i) Back-Gate CNTFET
The first back-gated CNTFET was designed with thick gate insulators,
which is silicon oxide, measured in an estimation of 100 to 150 nm. Two
noble metal (normally gold) electrodes were being bridge with a single
SWCNT prefabricated by lithography onto an oxidized silicon wafer. Noble
metals are a type of metal which could resists acid attack and does not corrode
easily. In comparison with a silicon MOSFET, the SWCNT acts as a channel
while the two metal electrodes will play the role of source and drain channel
respectively. The silicon wafer, which is heavily doped, will behave as a back
gate.
 38

With this structural design, there are some limitation such as high parasitic
contact resistance (measuring ≥1M ohm), low trans conductance (gm ≈ 1nS)
and low drive currents (measuring a few Nano amperes) [3] [8].

Fig 3.32 An example of back gate CNTFET

The possible root cause of such parasitic limitations is due to bad contact
between the carbon nanotube and the two gold electrodes. In order to have a
much better performance, the dielectric constant can be increased or the gate
capacitance can be increased while reducing the thickness of insulator.

ii) Top-Gate CNTFET

To overcome the back-gated CNTFET limitations, a top-gate CNTFET is
proposed with Ti gate, drain and source electrodes. The gate is placed above
the carbon nanotube and a SiO2 film measuring 15nm to 20nm was being used
as the gate oxide. This is done through the process of chemical vapour
deposition process.

This design’s performance turns out to be much better than the back-gate
CNTFET. Due to the device geometry, the electric field is increased and
contact resistance has been greatly reduced due to a different choice of
material. The threshold voltage has been lowered as compared to back-gate
CNTFET and higher drive current.
 39

Fig 3.33 An example of top gate CNTFET

Fig 3.34 Different Properties of the CNT and its applications

3.4.2 Properties of CNTFET

CNT properties and their implications for electronics are,

1) Carrier transport is 1-D. This implies a reduced phase space for scattering
of the carriers and opens up the possibility of ballistic transport.
Correspondingly, power dissipation is low. Furthermore, their electrostatic
behavior is different from that of silicon devices with implications on
screening and electron/hole tunneling.
 40

2) All chemical bonds of the C atoms are satisfied and there is no need for
chemical passivation of dangling bonds as in silicon. This implies that CNT
electronics would not be bound to use SiO 2 as an insulator. High dielectric
constant and crystalline insulators can be used, allowing, among other things,
the fabrication of
three-dimensional (3-D) structures.
3) The strong covalent bonding gives the CNTs high mechanical and thermal
stability and resistance to electro-migration. Current densities as high as 10 9
A/cm2 can be sustained
4) Their key dimension, their diameter, is controlled by chemistry, not
conventional fabrication.
5) In principle, both active devices (transistors) and interconnects can be
made out of semiconducting and metallic nanotubes, respectively.

a) Ratio between PMOS and NMOS

For comparing the performance of CNTFETs with MOSFETs at circuit
level, the inverter as a fundamental logic gate is considered first; the inverter
is designed with minimal width and a number of tubes in 32 nm technology.
For Si-CMOS, a PMOS/NMOS ratio between 2 and 3 is used for
compensating the difference in mobility between PMOS and NMOS. In
CMOS inverter , a 3 to 1 (PMOS:NMOS) ratio is used when designing the
inverter because the voltage Transfer characteristic(VTC) of the MOSFET
inverter shows a more symmetrical shape in the center of the logic threshold
voltage (VDD/2) for a ratio of 3 in 32 nm.
However, for the CNTFET case, a 1 to 1 (pFET:nFET) ratio is used
because the nFET and the pFET have almost the same current driving
capability with same transistor geometry. The VTC of the CNTFET also has
a symmetrical shape at a 1 to 1 (pFET:nFET) ratio. Even though the current in
a CNT is smaller than the minimum sized MOSFET (at32nmtechnology), a
CNTFET has a steeper curve in the transition region due to the higher gain.
 41

This contributes to a 22.5% improvement in noise margin(NM), and this

progressed performance is preserved under a decrease in power supply
voltage

Fig 3. 35 Voltage transfer characteristic for 32 nm metal-oxide

semiconductor field-effect transistor(MOSFET)and carbon nanotube FET
(CNTFET) inverters at 0.9 V supply voltage.
3.4.3 Performance and Parameters of CNTFET
Table 3.3 Threshold voltage W.R.T different channel length

In the above table 3.3 shows that the threshold voltage of the CNTFET
and MOSFET with respect to their channel lengths.
Table 3.4 Device parameter and process assumptions for simulations
(CNTFET model)
 42

In the above table 3.4 it shows that the Device Parameters and the
process assumptions of CNTFET used for Simulation.
3.4.4 MVL (Multi Valued Logic) of CNTFET
In a CNTFET, the threshold voltage of the transistor is determined by
the diameter of the CNT. Therefore, a multi-threshold design can be
accomplished by employing CNTs with different diameters (and, therefore,
chirality) in the CNTFETs. A resistive-load CNTFET-based ternary logic
design has been proposed. However, in this configuration, large OFF-chip
resistors (of at least 100MΩ values) are needed due to the current requirement
of the CNTFETs. The design technique proposed in this paper relies on and
eliminates the large resistors by employing Active load with P-type CNTFETs
in the ternary logic(three valued logic) gates. Ternary logic has been attracted
considerable interest due to its potential advantages over binary logic for
designing digital systems. For example, it is possible for ternary logic to
achieve simplicity and energy efficiency in digital design since the logic
reduces the complexity of interconnects and chip area. The multivalued logic
design based on multi threshold CNTFETs is assessed and compared with
existing designs based on CNTFETs.
 43

This logic describes that carbon Nano tubes of different diameters in

CNTFET’s have different threshold voltages.
 a= 2.49 angstrom is a carbon to carbon atom distance
 Vπ =3.033eV Carbon π-π bond energy
 DCNT = Diameter of the CNT
Table 3.5 Threshold Voltage With Respect to Different Chiral Vector

3.4.5 CNTFET Based Transmitter Design

3.4.5.1 Voltage Mode Transmitter

Fig 3.36 voltage mode transmitter

Transmitter consists of multiplexer, predriver, output driver. The
transmitter multiplexes parallel data(D0-D3) generates differential serial data
output and drives it to interconnect segment. Pseudo NMOS voltage mode
 44

multiplexer requires only one driver for all the inputs. Input data and
depending on the selected line the output to be high. The signal driven by the
predriver. Predriver nothing but static inverter used to reduce the output delay
and convert full swing signal into limited signal. Finally Output Driver to
reduce the swing and reducing power consumption. In Voltage mode driver
the capacitor is charging and discharging the signal value is 1F. Similarly the
complement signal is generated using the complemented data inputs to output.
3.4.5.2 Current Mode Transmitter

Fig 3.37 current mode transmitter

The large size of voltage mode drivers and the large amount of delay
and energy consumed by the required predrivers are a significant
disadvantage of voltage mode signalling.

The current mode drivers are significantly faster and more power
efficient than low impedance voltage mode driver. So to reduce output delay,
current steering driver should be used with limited swing pre-driver. It
 45

consists of a 4:1 multiplexer, a pre amplifier, and an output driver. The

transmitter employs a dual pseudo NMOS multiplexers at its input, one for
the signal and one for its complement. Each multiplexer input is switched by
two series NMOS that are gated by two adjacent clock phases in the same
manner that the driver pull downs are gated by adjacent clock phases.

3.4.6 Proposed CNTFET Based Transmitter Design

It is a new on-chip signaling method that relies on differential current
mode sensing to improve both delay and energy dissipation compared to
previous transmitters. This proposed method can be used as for point-to-point
as well as N-to-1 Connections. In this circuit a transmitter generates a
differential current at a output side. Control signals are used to enable the
transmitter to reduce static power. The transmitter contains two current
sources and a few control gates. When DIN is “1” current I is drawn in dwire
while there is no current in dwire. Like wise when DIN is 0 current I is drawn
in dwire and no current in dwire. Signal ten (Transmit Enable) control the
transmitter operation. Input DIN must be stable for as long as the transmitter
is enabled.

Fig 3.38 Circuit of the SIPF(Single PCNTFET) transmitter.

 46

Fig 3.39 SIPF(Single PCNTFET) transmitter.

In SIPF CNTP1(CNTFET BASED PMOS) and CNTP2 are used as
current sources. When TEN is “1” one of the P-CNTFET is active, depending
ON DIN. Pull down N-CNTFETs CNTN1(CNTFET BASED NMOS) and
CNTN2 are OFF. When ten is “0” CNTN1 and CNTN2 are turned on to
discharge the interconnects and initiate the transmitter for the next data
transfer.

Fig 3.40 Circuit of the STPF(Stacked PCNTFET) transmitter.

 47

Fig 3.41 STPF(Stacked PCNTFET) transmitter.

In the STPF transmitter design the current flow is controlled by
PCNTFETs CNTP3 AND CNTP4 placed between the current sources and the
interconnects. These P-CNTFETs are enabled when TEN is “1”. Depending
on the value of din, current flows to one of DWIRE and DWIRE.

Fig 3.42 Multiple Valued Logic Using Resistor Loaded Ternary SIPF
 48

In the above Fig 3.42 the NAND gate is replaced by Resistor loaded

NAND using Multiple Valued Logic Circuits (Multi Threshold Logic) and the

result is observed. Here the replaced Resistor Value is 100KΩ.

Fig 3.43 Multiple Valued Logic Using PSEUDO NCNFET Ternary

SIPF

In the above Fig 3.43 the NAND gate is replaced by PSEUDO NCNFET

NAND using Multiple Valued Logic Circuits (Multi Threshold Logic) and the

result is observed. Here the Pull up network replaced by single P-CNTFET

and the input of the gate is ground.

 49

CHAPTER 4

SIMULATION RESULTS

4.1 SYNOPSYS HSPICE SIMULATIONS

The transmitter circuit implemented by CNTFET in 32nm technology

using Synopsys HSPICE and Avanwaves viewer. The simulation results are
presented in below figures.

Fig.4.1. Output Waveforms for Voltage Mode transmitter using 32nm

MOSFET

Fig.4.1 shows that output waveforms of voltage mode driver, where

D0-D3 true and complement signal.Sel1,sel2 are selected lines. out1, out2
true and complement output signal. It is observed that the Average power is
5.2464E-04 and the Predelay is 1.49E-10.
 50

Fig.4.2. Output Waveforms for Voltage Mode transmitter using 32nm

CNTFET

Fig.4.2 shows that output waveforms of voltage mode driver, where

D0-D3 true and complement signal.Sel1,sel2 are selected lines. out1, out2
true and complement output signal. It is observed that the Average power is
4.8020E-04.Here the average power is reduced than the 32nm MOSFET
based transmitter. The Predelay is 3.22E-11. Here the Predelay also reduced
than the 32nm MOSFET based transmitter.

Fig.4.3. Output Waveforms for Current Mode transmitter using 32nm

MOSFET
 51

Fig.4.3 shows output waveforms of current mode driver,where where

5,8,12,15 true and complement signal. 3,10 are selected lines. 21, 22 are true
and complement output signal. It is observed that the Average power is
4.76E-03 but achieve low swing then Voltage mode transmitter. Observed
swing is 4.5736E-01. The Predelay is 3.66E-11.

Fig.4.4. Output Waveforms for Current Mode transmitter using 32nm

CNTFET

Fig.4.4 shows output waveforms of current mode transmitter, where

5,8,12,15 true and complement signal. 3,10 are selected lines. 21, 22 are true
and complement output signal. It is observed that the Average power is
4.80E-04 but achieve low swing then Voltage mode transmitter. Observed
swing is 1.3954E-02.

Fig.4.5. Output Waveforms for SIPF transmitter using 32nm CNTFET

 52

Fig.4.5 shows output waveforms of SIPF transmitter, where 2,5 are DIN
and TEN signal.10,11 are the DWIRE and DWIRE True and complement
output signal. It is observed that the Average power is 5.17E-05 and Predelay
is 1.68E-12. Here the proposed SIPF –CNTFET transmitter average power
and delay is reduced 10 times than the Existing CNTFET based transmitter.

Fig.4.6. Output Waveforms for STPF transmitter using 32nm CNTFET

Fig.4.6 shows output waveforms of STPF transmitter, where 2,4 are

DIN and TEN signal.7 is the DWIRE output signal. It is observed that the
Average power is 4.79E-05 and Predelay is 3.00E-12. Here the proposed
STPF–CNTFET transmitter average power and delay is reduced than the
Existing CNTFET based transmitter.

Fig.4.7. Output Waveforms for Multiple Valued Logic Using Resistor

Loaded Ternary SIPF
 53

Fig.4.7 shows output waveforms of Multiple Valued Logic Using

Resistor Loaded Ternary Inverters SIPF transmitter, where 2,4 are DIN and
TEN signal.10 is the DWIRE output signal. It is observed that the Average
power is 1.02E-05 and Predelay is 2.00E-13. Here the Proposed Multiple
Valued Logic Using Resistor Loaded Ternary Inverters SIPF–CNTFET
transmitter average power and delay is reduced than the Existing CNTFET
based transmitter. Here we observed the Predelay is reduced and we got the
PDP in ATTO seconds(AS).

Fig.4.8. Output Waveforms for Multiple Valued Logic Using PSEUDO

NCNFET Ternary SIPF

Fig.4.8 shows output waveforms of Multiple Valued Logic Using

PSEUDO NCNFET Ternary Inverters SIPF transmitter, where 2,4 are DIN
and TEN signal.10 is the DWIRE output signal. It is observed that the
Average power is 1.11E-05 and Predelay is 2.00E-13. Here the Proposed
Multiple Valued Logic Using Resistor Loaded Ternary Inverters SIPF–
CNTFET transmitter average power and delay is reduced than the Existing
CNTFET based transmitter. Here we observed the Predelay is reduced and we
got the PDP in ATTO seconds(AS).The PDP value is 2.22E-18.
 54

4.2 ANALYSIS OF PERFORMANCE CHARACTERISTICS

The performance characteristic analysis of voltage mode and current

mode transmitter is implemented in both MOSFET and CNTFET in 32nm
technology and compares the results.

Table 4.1 Performance Comparison

TRANSMITTERCIRCUITS(32NM AVG.POWER PREDELAY PDP

)

VOLTAGE MODE MOSFET 5.25E-04 1.49E-10 7.80E-14

CURRENT MODE MOSFET 4.76E-03 3.66E-11 1.74E-13

VOLTAGE MODE CNTFET 4.80E-04 3.22E-11 1.55E-14

CURRENT MODE CNTFET 5.43E-04 4.82E-11 2.62E-14

SIPF CNTFET 5.17E-05 1.68E-12 8.69E-17

STPF CNTFET 4.79E-05 3.00E-12 1.44E-16

SIPF MVL RESISTOR LOADED 1.02E-05 2E-13 2.05E-18

SIPF MVL PSEUDO LOGIC 1.11E-05 2E-13 2.22E-18

In the above table shows that the predelay, average power and power
delay product(pdp) metrics comparison of the both MOSFET and CNTFET
based transmitter. The Results are analysed. And it shows that when
compared to MOSFET the CNTFET having the reduced predelay, average
power and pdp.
 55

5.00E-03
4.50E-03
4.00E-03
3.50E-03
3.00E-03
2.50E-03
2.00E-03
1.50E-03
1.00E-03
5.00E-04
0.00E+00

Fig 4.9 Comparison chart for average power

In above Fig 4.9 shows that the average power of the CNTFET is
reduced than the average power of the MOSFET.

2.00E-13
1.80E-13
1.60E-13
1.40E-13
1.20E-13
1.00E-13
8.00E-14
6.00E-14
4.00E-14
2.00E-14
0.00E+00

Fig 4.10 Comparison chart for Power Delay Product

In the above Fig 4.10 shows that the power delay product of the
CNTFET using both current mode and voltage mode is less than the
MOSFET. It shows that SIPF and STPF based CNTFET transmitter shows
better power delay product than the Existing CNTFET based transmitter.
 56

1.60E-10
1.40E-10
1.20E-10
1.00E-10
8.00E-11
6.00E-11
4.00E-11
2.00E-11
0.00E+00

Fig 4.11 Comparison chart for Predelay

In the above Fig 4.11 shows that the Predelay of the CNTFET is
reduced than the MOSFET based voltage mode and current mode transmitter.
 57

CHAPTER 5

CONCLUSION AND FUTURE SCOPE

5.1 CONCLUSION
The Carbon Nanotube Field Effect Transistor (CNTFET) is one of the
most promising devices among emerging technologies to extend and/or
complement the traditional Si-MOSFET. In this paper, delay, Swing and
power consumption of CNTFET based transmitter have been assessed and
compared against the CMOS based transmitter. Simulation results have
shown that the PDP and the swing of the CNTFET based transmitter are
lower than for the MOSFET based transmitter. This paper has demonstrated
the advantages offered by CNTFET gates under different operational
conditions such as very low power supply voltage. The circuits designed
using CNTFET gates have a high robustness to process, voltage, and
temperature variations. The quantitative results of this paper have confirmed
that CNTFET technology is a viable solution to replace conventional
MOSFET technology.

5.2 FUTURE SCOPE

In the future, the CNTFET based Receiver will be designed and

combined with SIPF and STPF CNTFET based transmitter it may
provide better performance in terms of area reduction and less power
consumption than the MOSFET based Receiver.
 58

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