MICROPROCESSORTECHNOLOGY

BENC2423
FLAGS & DATA PROCESSING INSTRUCTIONS

Syafeeza Ahmad Radzi1, Wong YanChiew2

1syafeeza@utem.edu.my, 2ycwong@utem.edu.my,
 Learning Outcomes

At the end of this lecture, you should be able to:

• understand the use of flags for eachinstruction.
• understand the comparison instructions.
• understand the use of data movement instructions.
• understand the use of data processinginstructions.
 Table of Contents

Introduction
Flags and their use – N, Z, C, V
Comparison instructions
Data movement instructions
Data processing instructions
• Logical instructions - Boolean operations
• Arithmetic instructions -Addition/Subtraction
• Multiplication
• Division
• Shifts and Rotates
 Introduction

• The Application Program Status Register (APSR) holds the ALU flags,
with the bits configured as shown in thefigure.
• The top four bits (bits 31, 30, 29, and 28) are the condition code (cc)
bits and are of most interest to us.
• Some instructions can optionally update the Condition Code (cc)
Flags (NZCV) to provide information about the result of executing
the instruction.
• What’s the purpose of flags?
– Tells the microprocessor the current status of arithmetic operation
and bit manipulation.

APSR EPSR IPSR

 Introduction (cont.)

• By default data processing instructions do not

update the condition flags.
• Instructions will update condition flags if it is
suffixed with anS.
• S modifier: update conditionflags.
• Compare instructions e.g: CMP does not have S.
• For example, the following instruction addstwo
registers and updates the condition flags.
ADDS r0, r1, r2
 Flags and their use: N, V, Z,C
31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8 7 6 5 4:0

xPSR N Z C V Q ICI/IT T ICI/IT Exception Number

When an ALU operation changes the flags:

• N – Negative
– is set if the result of a data processing instruction is negative.
– Bit [31] =1
– In comparison instructions, this is used to indicate less-than. The bit is cleared for all
positive/greater-than or zero/equal toresults.
• Z– Zero
– is set if the result iszero.
• C– Carry
– is set if the result of an addition, subtraction or compare is greater than 32 bits.
– is set if borrow does notoccur (subtraction).
• V –oVerflow
– Only for signed operations
– Is set if two positive numbers are added and produces negative result.
– Is set if two negative numbers are added and produces positive result.
– is set if the result is outside the range of −2n−1 ≤ Two's Complement ≤ 2n−1 −1
 Flags and their use: N, V, Z, C(cont.)

N: Negative
• N=1 to bit 31 of the result. N=1 if the signed value is negative, and N=0 if
the result is positive or zero.
• The N flag is set by an instruction if the resultis negative.
• In practice, N is set to the 2’s complement sign bit of the result (bit 31).
•E.g: ADDS r0, r1, r2
r1 = -110 = 0xFFFFFFFF
r2 =-210 =0xFFFFFFFE
r0 = (-1) + (-2), the result is -3 so N=1 (N flag isset)

* ADD instruction does not update the cc

r1: 1111 1111 1111 1111 1111 1111 1111 1111
r2: + 1111 1111 1111 1111 1111 1111 1111 1110
r0: 11111 1111 1111 1111 1111 1111 1111 1101
Bit [31]=1, so N = 1
 Flags and their use: N, V, Z, C(cont.)

Z: Zero
• Z=1 when the result of the operation is Zero. This is usual to denotean equal
result from a comparison. Ifthe result is non-zero, this flag is cleared.
•E.g: SUBSr0, r1, r2
r1 = 110
r2 =110
r0 = (1) - (1), the result is 0 so Z=1 (Z flag is set)

* ADD instruction does not update the cc

r1: 0000 0000 0000 0000 0000 0000 0000 0001
r2: + 1111 1111 1111 1111 1111 1111 1111 1111
r0: 1 0000 0000 0000 0000 0000 0000 0000 0000

Result = 010 so Z = 1
 Flags and their use: N, V, Z, C(cont.)
C: Carry (known as unsignedoverflow)
• C=1 ifthe result of an unsigned operation overflows the 32-bit result register.
• For other instructions that use shifting, this flag is set to the value of the last bit
shifted out by the shifter.
• Other instructions usually leave this flag alone.
E.g:

ldr r2, =0xCF0EC535 ; move data into r2

ldr r5, =0x37424114 ; move data into r5
adds r3, r2, r5
1100 1111 0000 1110 1100 0101 00110101
+ 0011 0111 0100 0010 0100 0001 0001 0100
1 0000 0110 0101 0001 0000 0110 01001001

The carry bit will cause Cflag to set (C =1)

 Flags and their use: N, V, Z, C(cont.)

• The carry (borrow) flag is also set if the

subtraction of 2 numbers requires aborrow
into the most significant bitssubtracted.

0000 – 0001 = 1111 (carry flag is turned on)

 Flags and their use: N, V, Z, C(cont.)
V: (Signed) Overflow
• V=1 if the result is outside the range of −2n−1 ≤ Two's Complement ≤ 2n−1 −1
−8 ≤ x[4] ≤ +7  for 4 bit number
−128 ≤ x[8] ≤ +127  for 8 bit number
−32768 ≤ x[16] ≤ +32767  for 16 bit number
−2147483648 ≤ x[32] ≤ +2147483647  for 32 bit number

Overflow rule for addition

• Overflow occurs (V=1) if
– (+A) + (+B) = −C; when the sum of 2 positive numbers is a negative result
– (−A) + (−B) = +C; when the sum of 2 negative numbers is a positive result
– * The sum of a positive and negative number will never overflow

• Example of overflow for 32bit:

Consider adding (A1234567+B0000000=151234567)16, which produces a result of +5123456716 in 32-bit
2’s complement:

1010 0001 0010 0011 0100 0101 0110 0111 Adding two (-ve) numbers
+ 1011 0000 0000 0000 0000 0000 0000 0000 that produces (+ve) results
1 0101 0001 0010 0011 0100 0101 0110 0111 indicates V=1
The carry bit does not indicateV=1
 Flags and their use: N, V, Z, C(cont.)
Overflow rule for subtraction
• Overflow occurs if
• (+A) − (−B) = −C (+A) + (B) = -C
• (−A) − (+B) = +C change –A and –B to 2’s complement and then perform addition
• All the “-” numbers need to be changed to 2’s complement numbers. In the end,
addition is performed instead of subtraction.
• Example of overflow for 32 bit subtraction:
LDR r1, =0x70000000
LDR r2, =-0x60000000
SUBS r0, r1, r2

means, 0x70000000-(-0x60000000) = 0x70000000 + 0x60000000 = 0xD0000000

0111 0000 0000 0000 0000 0000 0000 0000 Adding two (+ve) numbers
+ 0110 0000 0000 0000 0000 0000 0000 0000 that produces (-ve) results
1101 0000 0000 0000 0000 0000 0000 0000 indicates V=1

Bit [31] = 1, so N = 1
 Flags and their use: N, V, Z, C(cont.)
• Consider the following example:
LDR r1, =0xffffffff
LDR r2, =0x00000001
ADDS r0, r1, r2

• The result of the operation would be 0x100000000, but the top bit is
lost because it does not fit into the 32-bit destination register and so the
real result is 0x00000000. In this case, the flags will be set as follows:
Flag Condition
N= 0 The result is 0, which is considered positive, and so the N (negative) bit is set to 0.
Z=1 The result is 0, so the Z(zero) bit is set to 1.
C= 1 We lost some data because the result did not fit into 32 bits, so the processor
indicates this by setting C(carry) to 1.
V= 0 From a two's complement signed-arithmetic viewpoint, 0xffffffff really means -1, so
the operation we did was really (-1) + 1 = 0. That operation clearly does not overflow,
so V (overflow) is set to 0.
 Comparison instructions
• These instructions do not store the result inany register.
• It set the condition code bits (N, Z, C, and V) in the CPSRaccording to the selected
operation.

• Syntax: <instruction>{<cond>} Rn, operand2

where
Instruction is either CMP,CMN, TSTor TEQ
cond is an optional condition code
Rn is the register holding the first operand
operand2 is the flexible second operand

Instruction P-code Comment

CMP r1, r2 set cc on r1 - r2 compare
CMN r1, r2 set cc on r1 – (~ r2) compare negated
TSTr1, r2 set cc on r1 ANDr2 Test bits of a 32-bit value
TEQr1, r2 set cc on r1 XORr2 test for equality of two 32-bit values
 Comparison instructions (cont.)

• These comparisons work by performing

arithmetic or logical operations on the values
stored in the source registers and setting the
appropriate condition code flags in the
Application Program Status Register (APSR) as
necessary.
• However, the actual result of the underlying
arithmetic or logical operation is not stored in
any register.
 Comparison instructions (cont.)

 CMP r1, r2 ; set cc on r1 – r2

• The CMP instruction is a SUBTRACTION, which gives no
results EXCEPTpossibly changing conditional codes in CPSR
• CMP subtracts a register or an immediate value from a
register value and updates the cc.
• CMP can be used to check the contents of a register for a
particular value, such as at the beginning or end of a loop.
• The CMP (compare) instruction will set the condition codes
as follows:

 N = 1 if the most significant bit(MSB) of (r1 - r2) is 1, i.e. r2 > r1

 Z= 1 if (r1-r2) = 0, i.e. r1 =r2
 C= 1 if r1 and r2 are both unsigned integers AND (r1 <r2)
 V = 1 if r1 and r2 are both signed integers AND (r1 < r2)
 Comparison instructions (cont.)

• In order to perform branch on the “==“ operation, we need to use

CMP.
• Example:
CMP r3, #0 ; set Z flag if r3==0
CMP r3, r4 ; set Z flag if r3==r4

r3 == 0?
(true) (false)
r3 == 0 r3 != 0
Other flags can also be
c=d+e c=d-e affected not just Z

Exit
 Comparison instructions (cont.)

 CMN r1, r2 ; set cc on r1 –(~r2)

• The CMN (compare negative) instruction determines the
condition codes by performing the equivalent of:
operand1 - ( ~operand2).
• It is useful for comparing the values in registers against
small negative numbers (such as -1 which might be used to
mark the end of a datastructure.)
• CMN can be used when you want to compare with negative
numbers.
• Example:
If you typed CMP r0, #-20 (-20 is in decimal), theassembler
will instead generate CMN r0, #0x14
 Comparison instructions (cont.)

• ARM do not support negative constants.The

assembler will compensate for this:
• Example:
ADD r0, r1, #-2  SUBr0, r1,#2
CMP r3, #-10  CMN r3, #10
 Comparison instructions (cont.)
 TST r1, r2 ; set cc on r1 and r2
• Perform bit-wise ANDSoperation.
• The TST(test bits) instruction can be used to test if one or more bits
are set.
• The first operand is the value to be tested; the second operandis
the bit mask.
– TSTinstruction updates the N and Zflags according to the result.
– Can update the Cflag during the calculation of operand2.
– Do not affect the Vflag.
– Example: Totest bit 7 to see whether IRQ interrupt occurs or not.
; Did the chip trigger thisIRQ?
LDR r1, [r4, #Status_flags] ; load status flags
B r0, #(1<<7) ; is b7 set?
TST Our_Interrupt_Handler ; yes, so deal with interrupt
BEQ
 Comparison instructions (cont.)

 TEQ r1, r2 ; set cc on r1 xor r2

• The TEQ(test equivalent) instruction is similar to TST,but
differs in that it uses anEX-ORoperation.
• It can be used to determine if specific bits in two operands are
the same or different.
• Itdoes not change the overflow flag (V), unlike CMP.
• TEQcan be used to determine if two values have thesame
sign.
 Comparison instructions (cont.)

Example:
• Assuming r1 = 0x70000000 and r2 =
0x70000000. What are the CPSRflags
would be after the instructions
Instructions Flags
CMP r1, r2 N = 0, Z= 1, C= 1, V = 0 set cc on r1 – r2
CMN r1, r2 N = 1, Z= 0, C= 0, V = 1 set cc on r1 – (~r2)
TST r1, r2 N = 0, Z= 0, C= 0, V = 0 set cc on r1 and r2
TEQ r1, r2 N = 0, Z= 1, C= 0, V = 0 set cc on r1 xor r2
 Exercise 1

Specify ARM assembly instruction for the each

comment below:
; perform bitwise AND of r0 value to 0×3F8.
; APSRis updated but result isdiscarded.
; conditionally test if value in r10 is equal to the value in r9;
; APSRis updated but result isdiscarded.
 Answer Exercise 1

TST r0, # 0×3F8

TEQEQ r10, r9 (you can put GT,LT,MI, etc
because condition depends on previous
instruction)
 Data Movement Instructions (cont.)

MOV - is used to copy values from one register to another or to load

immediate data in the range 0-65535 (16-bit) into registers.
MVN - Move NOT(obtain logical inverted value)
Syntax:
MOV{S}{cond} Rd, Operand2
MOV{S}{cond} Rd, #imm16
MVN{S}{cond} Rd,Operand2
where:

S: Is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

cond: Is an optional condition code.

Rd: Is the destination register.

Operand2: Is a flexible second operand: a constant or a register with optional shift.

imm16: Is any value in the range 0-65535.

 Data Movement Instructions (cont.)

Example:
MOV r2, #2 ; Load the binary value 0000 0000 0000 0000 0000 0000 0000
0010into registers r2, r3 and r4.
MOV r3, r2 ; This sequence uses immediate data to register and register to
register data transfer.
MOV r4, r3
•These instruction ignore the first operandand
simply move the second operand to the
destination.
 MOV r0, r2 ; r0 = r2
–A MOV instruction that has the same source anddestination
registers does not do anything!
 Data Movement Instructions (cont.)
 MVN r0, r1 ; r0 = not r1
• The ‘MVN’ stands for ‘move negated’; it leaves the result register set
to the value obtained by inverting every bit in the source operand.
 r1: 1101 0110 1010 0000 0111 0101 10100011
 r0: 0010 1001 0101 1111 1000 1010 01011100

•The MVN instruction allows a programmer to insert

a negative value into a register.
•Complement the value of operand andmove
it into thedestination register.
 MVN r0, #0 ; moves -1 into r0
0000 0000 0000 0000 0000 0000 0000 0000
1111 1111 1111 1111 1111 1111 1111 1111
 Data Movement Instructions (cont.)
Equivalent MVN instructions for moving negative immediate numbers
Example MOV Signed Magnitude 2’s Negate Equivalent Equivalent MVN
instruction (decima converted to binary compleme decimal num instruction
l) nt
MOV r0, #-15 -15 1111 0001 1110 14 MVN r0, #14
MOV r0, #-14 -14 1110 0010 1101 13 MVN r0, #13
MOV r0, #-13 -13 1101 0011 1100 12 MVN r0, #12
MOV r0, #-12 -12 1100 0100 1011 11 MVN r0, #11
MOV r0, #-11 -11 1011 0101 1010 10 MVN r0, #10
MOV r0, #-10 -10 1010 0110 1001 9 MVN r0, #9
MOV r0, #-9 -9 1001 0111 1000 8 MVN r0, #8
MOV r0, #-8 -8 1000 1000 0111 7 MVN r0, #7
MOV r0, #-7 -7 0111 1001 0110 6 MVN r0, #6
MOV r0, #-6 -6 0110 1010 0101 5 MVN r0, #5
MOV r0, #-5 -5 0101 1011 0100 4 MVN r0, #4
MOV r0, #-4 -4 0100 1100 0011 3 MVN r0, #3
MOV r0, #-3 -3 0011 1101 0010 2 MVN r0, #2
MOV r0, #-2 -2 0010 1110 0001 1 MVN r0, #1
MOV r0, #-1 -1 0001 1111 0000 0 MVN r0, #0
 Data Movement Instructions (cont.)
MOVT – Move top
• Writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its
destination register. The write does not affect Rd[15:0].
• The instruction doesn’t change the flag.

Syntax
MOVT{cond} Rd, #imm16

where:
cond: is an optional condition code.
Rd: is the destination register.
imm16: is a 16-bit immediate constant.

Example:
MOVT r3, #0×ABCD ; Write 0×ABCD to upper halfword ofr3, lower halfword and
; APSRare unchanged
 Data Movement Instructions (cont.)

• The MOV, MOVT instruction pair enables you to

generate any 32-bit constant.
• Example:
What is the value of the destination register (r4)
after these instructions areexecuted?
MOV r4, #0×5678
MOVT r4, #0×ABCD

Answer: r4 =0×ABCD5678
 Comparison of instructions for
loading constants
MOV rd, constant
• Works for 0 – 65535 (16 bit)

MVN rd, constant ; rd <-~constant

• Effectively doubles the number of constants
• Assembler converts MOV with negate constant to MVN

LDR rd, = constant

• An assembler pseudo-op, not an instruction
• Converted to MOV or MVN if possible
• Else converts to LDRrd, [pc,#imm]
 Exercise 2

• What are the differences between MOVand

LDRinstruction? State TWO (2)differences.
 Answer Exercise 2

• LDRcan access memory but MOVcannot.

• Both can deal with constant number but with
different syntax and maximum value. For
example:
MOVr0, #constant ; syntax for loading constant intoregister
; The max value for the constant is 216-1 (16bit)

LDR r0, = constant ; syntax for loading constant intoregister

; The max value for the constant is 232-1 (32bit)
 Exercise 3

If r1 = 0×0012, what is the value ofr6 and r9?

MOV r6, r1
MOV r6, r1, LSL#3
MOV r9, #3
MOV r6, r1, LSLr9
 Answer Exercise 3

If r1 = 0×0012, what is the value ofr6 and r9?

MOV r6, r1  r6 = 0×0012
MOV r6, r1, LSL#3  r6 = 0×0090
MOV r9, #3  r9 =0×0003
MOV r6, r1, LSLr9  r6= 0×0090
 Exercise 4

What is the equivalent MVN instruction for the

following MOV instructions?
• MOV r4, #-20
• MOV r3, #-120
 Answer Exercise 4

What is the equivalent MVN instruction for the

following MOV instructions?
• MOV r4, #-20  MVN r4, #19
• MOV r3, #-120  MVN r3, #119
 Exercise 5

Specify ARM assembly instruction for the each

comment below:
; write value of 0×000B to r11, flags get updated.
; write value of 0×FA05 to r1, flags are not updated.
; write value in r12 to r10, flags get updated.
; write value of 23 to r3.
; write value of 0×FFFFFFF0(bitwise inverse of0×F)
to r2 and updateflags
 Answer Exercise 5

MOVS r11, # 0×000B

MOV r1, # 0×FA05
MOVS r10, r12
MOV r3, #23
MVNS r2, # 0×F
 Logical Instructions
Boolean operations (Bit-wise logicaloperations)
– These instructions perform the specified Boolean logic operation on eachpair
of the input operands.
– Logical operation are performed bit by bit on the inputoperands (which may
be values in registers or constants) and the result placed in a destination
register.

– Syntax: <instruction>{<cond>}{S} Rd, Rn, Operand2

Instruction P-code Comment

AND r0, r1,r2 r0 := r1 ANDr2 Logical bitwise AND of two 32-bit values
ORRr0, r1, r2 r0 := r1 ORr2 Logical bitwise ORof two 32-bitvalues
EORr0, r1, r2 r0 := r1 XORr2 Logical exclusive ORof two 32-bitvalues
BIC r0, r1, r2 r0 := r1 AND (NOT r2) Logical bit clear (ANDNOT)

– BIC stands for ‘bit clear’ (closely related to ANDinstruction)

– Every ‘1’ in the second operand clears the corresponding bit in the first
operand.
 Logical Instructions (cont.)

AND
Example:
AND r0, r1, r2 ; r0 = r1 and r2
the result bit is 1 if both input bits are 1
r1: 0101 0011 1010 1111 1101 1010 01101011
r2: 1101 0110 1010 0000 0111 0101 10100011
r0: 0101 0010 1010 0000 0101 0000 00100011

BEFORE AFTER A B AND

0 0 0
R0 0x0012 345A R0 0x52A0 5023
0 1 0
R1 0x53AF DA6B R1 0x53AF DA6B
1 0 0
R2 0xD6A0 75A3 R2 0xD6A0 75A3 1 1 1
 Logical Instructions (cont.)

• AND is used to clear specific bits

• Bits ‘AND’ with 0 results in a0 r0 1 1 0 1
• Bits ‘AND’ with 1remains * * * *
0x0A
unchanged 1 0 1 0

• Example: clear bits 1 and 2 r1 1 0 0 0

– Assume R0 =0x0000000D
• AND R1, R0, #0x0A
– 0x0A = 1010b (clear bits 1 and 3)
– 0x0A is known as the bit mask
 Logical Instructions (cont.)
ORR
Example:
ORR r0, r1, r2 ; r0 = r1 or r2
the result bit is 1 if either input bit is 1
r1: 0101 0011 1010 1111 1101 1010 0110 1011
r2: 1101 0110 1010 0000 0111 0101 1010 0011
r0: 1101 0111 1010 1111 1111 1111 1110 1011
ORRinstructions are useful for ensuring thatcertain bits are set.

A B OR
0 0 0
0 1 1
1 0 1
1 1 1
 Logical Instructions (cont.)
• ORR is used to set specific bits
• Bits ‘OR’ with 1 results in a1 r0 1 1 0 1
+ + + +
• Bits ‘OR’ with 0remains 0x03 0 0 1 1

unchanged
r1 1 1 1 1
• Example: set bits 1 and 2
– Assume r0 = 0x0000000D
• ORR r1, r0, #0x03
– 0x03 = 0011b (set bits 0 and 1)
– 0x03 is known as the bit mask
 Logical Instructions (cont.)

EOR
Example:
EOR r0, r1, r2 ; r0 = r1 xor r2
the result bit is set to 1 if one and only one of the inputs bits is 1
r1: 0101 0011 1010 1111 1101 1010 01101011
r2: 1101 0110 1010 0000 0111 0101 10100011
r0: 1000 0101 0000 1111 1010 1111 1100 1000
EORinstructions can be useful for inverting specificbits.
A B XOR
0 0 0
0 1 1
1 0 1
1 1 0
 Logical Instructions (cont.)

• EOR can be used as a NOT r0

• Bits ‘EOR’ with 1 to invert

0×0F
• Example: invert r0
– Assume r0 = 0x0000000A r2
• EOR r2, r3, #0xFF
– 0xFF to invert all bit
– 0xFF is known as the bit mask
 Logical Instructions (cont.)
BIC (Bit Clear)
Example:
BIC r0, r1, r2 ; r0 = r1 and (~r2)

bit clear: R2 is a mask identifying which bits of R1 will be cleared to zero

Example 1:
r1=0x11111111 r2=0x01100101
BIC r0, r1, r2
r0=0x10011010

Example 2:
r1=0x02FA62CA r2=0x0000FFFF
BIC r0, r1, r2
r0=0x02FA0000
 Arithmetic Instructions

Addition/Subtraction
– Syntax: <instruction>{<cond>}{S} Rd, Rn, Operand2
Instruction P-code Comment
ADD r0, r1, r2 r0 := r1 +r2 Add two 32-bit values
ADCr0, r1, r2 r0 := r1 + r2 +C Add two 32-bit values andcarry
SUBr0, r1, r2 r0 := r1 - r2 Subtract two 32-bit values
SBCr0, r1, r2 r0 := r1 - r2 + C-1 subtract withcarry of two 32-bit values
RSBr0, r1, r2 r0 := r2 – r1 Reverse subtract of two 32-bit values
RSCr0, r1, r2 r0 := r2 – r1 + C- 1 Reverse subtract with carry of two 32-bitvalues
 Arithmetic Instructions (cont.)

<instruction>{<cond>}{S} Rd, Rn, Operand2

Example of conditional execution:

SUBNE r3, r10, r5
SUBNE r3, r10, r5
S r3, r10, r5
ADDGT
 Arithmetic Instructions (cont.)

In the following, assume r1 = 0x20001003,

r2 = 0xF0030050, r3 = 0x70000042, r4 =
0x7C00003F, and the C flag is 1. Each
example is independent of all the other
examples.
ADC r0,r1,r2 ; 0x20001003 + 0xF0030050 + 1, r0 = 0x10031054
ADD r0,r1,r2 ; 0x20001003 + 0xF0030050, r0 = 0x10031053
SBC r0,r2,r3 ; 0xF0030050 – 0x70000042 + 1 – 1, r0 = 0x8003000E
SUB r0,r2,r3 ; 0xF0030050 - 0x70000042, r0 = 0x8003000E
RSB r0,r1,r2 ; 0xF0030050 - 0x20001003, r0 = 0xD002F04D
RSC r0,r1,r2 ; 0xF0030050 - 0x20001003 + 1 – 1, r0 = 0xD002F04D
 Exercise 6

Find new content of r3 from the instruction

below.
ADD r3, r2, r1, LSL#3

If r1 =0×0010
r2 =0×0001
r3 =0×0100
 Answer Exercise 6

ADD r3, r2, r1, LSL#3

If r1 = 0×0010  0×0010 * 8 =0×0080

r2 = 0×0001  0×0080 + 0×0001 = 0×0081
r3 = 0×0100  0×0081 (new value for r3)
 Exercise 7

Assume that r0 = 32, r1 =1

What will the following instructionsdo?
ADDS r0, r1, r1, LSL#2
SUB r0, r0, r1, LSL#4
 Answer Exercise 7

Assume that r0 = 32, r1 =1

What will the following instructionsdo?
ADDS r0, r1, r1, LSL#2 ; r0 is updated with the value 5
; update flag, N = 0, Z= 0, C= 0, V = 0
SUB r0, r0, r1, LSL#4 ; r0 is updated with the value 16
 Multiplication Instructions
Multiply
– The short multiply instructions have 32-bit source operands and
generate a 32-bit modulo result.
– The long multiply instructions have 32-bit source operands and
generate a full 64-bit result.
– In all the multiply instructions, all operands must be in registers
except that R15 (PC) and R13 (SP) is not allowed.
• If S is appended to a multiply instruction's opcode, the N and
Z flags will be set correctly but the C and V flags are set to
meaningless values.
• If S is used with the MUL instruction:
– Rd, Rn and Rm must be in the range R0 to R7.
– Rd must be the same as Rm.
– You must use the cond suffix.
 Multiplication Instructions (cont.)

MUL{cond} {S} {Rd,} Rn, Rm ; Multiply

MLA{cond} {S} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract

where
cond: is an optional condition code
S: is an optional suffix. If Sis specified, the conditioncode flags are
updated on the result of theoperation.
Rd: is the destination register. If Rd is omitted, the destination
register is Rn.
Rn, Rm: Are registers holding the values to bemultiplied.
Ra: is a register holding the value tobe added or subtracted from.
 Multiplication Instructions (cont.)

Short multiply instructions

• Syntax: MUL{<cond>}{S} Rd, Rm, Rs
MLA {<cond>}{S} Rd, Rm, Rs,Rn
MLS{cond} Rd, Rn, Rm, Ra (do not changethe flags)
• The second operand cannot be immediate value(#).
Instruction P-code Comment
MUL Rd = Rm * Rs 32x32 multiply with 32-bitproduct
MLA Rd = (Rm * Rs) + Rn 32x32 multiply added to a32-bit
accumulated value
MLS Rd = Ra- (Rn * Rm) 32x32 multiply subtracted from a 32-bit value

Example:
if r1 = 0xFFFFFFFF,r2 = 0x80000000, and r3 = 0x00020700 then
MUL r0, r1, r2 ; r1 * r2, r0 = 0x80000000
MLA r0, r1, r2, r3 ; (r1 * r2) + r3, r0 = 0x80020700
MULS r0, r1, r2 ; r1 * r2, r0 = 0x80000000, N = 1
 Multiplication Instructions (cont.)

• Multiply with accumulate (MLA) is particularly suited

for digital filters
Input, xn Output, yn
A0 +

xn-1 A1

xn-2 A2

xn-3 A3

• Typical digital filter equation (convolution)

yn =(xn  A0) + (xn-1  A1) + (xn-2  A2) + (xn-3  A3)
• MLA most suitable instruction
 Exercise 8

Specify ARM assembly instruction for the

following operation:
r1 = r0 * 4
r1 = r2 * 5
 Answer Exercise 8

Specify ARM assembly instruction for the

following operation:
r1 = r0 * 4  MUL r1, r0, r2 (assume 4 is stored in r2)
r1 = r2 * 5  MUL r1, r2, r4
 Exercise 9

Specify ARM assembly instruction for the each

comment below:
; multiply, r10 = r2 ×r5
; multiply with accumulate, r10 = (r2 × r1) + r5
; multiply with flag update, r0 = r2 × r2
; conditionally multiply, r2 = r3× r2
; multiply with subtract, r4 = r7 – (r5 × r6)
 Answer Exercise 9

MUL r10, r2, r5

MLA r10, r2, r1,r5
MULS r0, r2, r2
MULLT r2, r3, r2 (cond can beanything)
MLS r4, r5, r6, r7
 Exercise 10

Write an assembly code that performs the

mathematical equation: 4x2 + 3x – 5. Assume x is
stored in r1.
 Answer Exercise 10

4x2 + 3x – 5

MUL r0, r1, r1 ; r0 =r12

MOV r2, #4 ; r2 =4
MUL r0, r2, r0 ; r0 = 4 r12
MOV r2, #3 ; r2 =3
MUL r2, r2, r1 ; r2 =3r1
ADD r0, r0, r2 ; r0 = 4 r12 +3r1
SUB r0, r0, #5 ; r0 = 4 r12 + 3r1 - 5
 Division Instructions
• SDIV (Signed division) – performs a signed integer division of the value in Rn by
the value in Rm.
• UDIV (Unsigned division) – performs an unsigned integer division of the value in
Rn by the value in Rm.
• For both instructions, if the value in Rn is not divisible by the value in Rm, the
result is rounded towards zero.
• Syntax:
SDIV{cond} {Rd,} Rn, Rm ; signed division (do not change the flags)
UDIV{cond} {Rd,} Rn, Rm ; unsigned division (do not change the flags)

where
cond: is an optional condition code
Rd: is the destination register. If Rd is omitted, thedestination register is Rn
Rn: is the register holding the value to be divided.
Rm: is a register holding the divisor.
 Division Instructions (cont.)

Example:

SDIV r1, r2,r3

– Signed divide r1 = r2 / r3

UDIV r7, r7,r0

– Unsigned divide r7 = r7 / r0
 Exercise 11

Write assembly code for the followingstatement

from a) to j) in Figure 4(d). Determine the final
values for R0, R1, R2 andR3.
a. Load R0, R1 and R2 with 874, 5578 and 5
b. Square R2
c. Add R1 and R2 and store in R3.
d. Subtract R0 from R3 and store in R3
e. Multiply R0 by 6
f. Subtract 2477 from R1
g. Divide R1 by R2 and store in R1
h. Square R1
i. Subtract R1 from R3 and store in R3
j. Divide R3 by 100
 Answer Exercise 11
MOV R0, #874
MOV R0, #0 ; assign 874 to R0
T R1, #5578
MOV R1,#0 ; assign 5578 to R1
MOV R2,#5
T R2,#0 ; assign 5 to R2
MOV R4,#6
MOV R4,#0 ; assign 4 to R4 (1mark)
T
MOV
MOV
T
MUL R2, R2, R2 ; R2 = R2 * R2 (square R2) (1 mark)
ADD R3, R1, R2 ; R3 = R1 + R2 (1 mark)
SUB R3, R3, R0 ; R3 = R3 - R0 (1 mark)
MUL R0, R0, R4 ; R0 = R0 * R4 (6) (1mark)
SUB R1, R1, #2477 ; R1 = R1 – 2477 (1mark)
UDIV R2, R1, R2 ; R1 = R1 / R2 (1 mark)
MUL R1, R1, R1 ; R1 = R1 * R1 (square R1) (1 mark)
SUBS R3, R3, R1 ; R3 = R3 - R1 (1 mark)
;MOV
final answerR4,
is R0 =
#1005244, R1 = 15376, R2 =
; assign 25,toR3R4
100 = (1mark)
-106 (2 marks)
SDIV R3, R3, R4 ; R3 = R3 / R4 (100) (1 mark)
 Shift and Rotate Instructions
Shifts and Rotates
• There is no shift instruction inARM.
• Instead it has a barrel shifter which provides amechanism
to carry out shifts as part of other instructions.
• Shift instructions can replace multiplication instructions
(MUL, MLA) if cost is the mainconsideration.
Operand 1 Operand 2
Operand 2 can be a:
1) Register
Barrel - 32 bit sizeregister
Shifter 2) Immediate value
- Allows 32 bit constants to be
directly loaded into registers
ALU

Result
 Shift and Rotate Instructions (cont.)
• Barrel shifter can support 6 operations:
– LSL Logical Shift Left (unsigned multiplication by2n)
• Fill in “0” on the right
– LSR Logical Shift Right (unsigned division by2n)
• Fill in “0” on the left
– ASL Arithmetic Shift Left (unsigned multiplication by2n)
• Fill in “0” on the right
– ASR Arithmetic Shift Right (signed division by2n)
• Fill in “1” on the left
– ROR Rotate Right
• rotate right by 0 to 32 places; the bits which fall off the least significant end of the word are used, in
order, to fill the vacated bits at the most significant end of the word.
– RRX Rotate Right with Extend
• rotate right extended by 1 place; the vacated bit (bit 31) is filled with the old value of the Cflagand
the operand is shifted one place to the right.

ASL and LSL are the same, and may be freely interchanged.

• Shift and rotate operands can be applied to any of the followingARM instructions:
ADC,ADD, AND, BIC, CMN, CMP,EOR,MOV, MVN, ORR,RSB,SBC,SUB, TEQ,TST.
• Shift and rotate operands can also be applied to registers used for calculating
addresses in LDRand STRinstructions.
 Shift and Rotate Instructions (cont.)

• Syntax
op{S}{cond} Rd, Rm,Rs
op{S}{cond} Rd, Rm,#n
RRX{S}{cond} Rd, Rm
– Op is one of ASR,LSL,LSRand ROR.
– S is an optional suffix. If S is specified, the cc flag are updated on the result of
the operation.
• these instructions update the N and Z flags according to the result.
• the C flag is updated to the last bit shifted out, except when the shift length is 0.
– Rd specifies the destination register.
– Rm specifies the register holding the value tobe shifted.
– Rs specifies the register holding the shift length to apply to the value Rm. Only
the least significant byte is used and can be in the range 0 to 255.
– n Specifies the shift length. The range of shift length depends on the
instruction:
• ASRshift length from 1 to32
• LSLshift length from 0 to31
• LSRshift length from 1 to32
• RORshift length from 1 to31.
 Shift and Rotate Instructions (cont.)

LSL (Logical Shift Left)

• LSLis a logical shift left by 0 to 31 places. The
vacated bits at the least significant end of the
word are filled with zeros.
10100101100011010011010001101001

0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0

LSL#4
 Shift and Rotate Instructions (cont.)
Example: Logical shift left (LSL)

C Register 0
MOV R0, R2, LSL #2 @ R0:=R2<<2
@ R2 unchanged
Example: 0…0 0011 0000
Before R2=0x00000030
After R0=0x000000C0
R2=0x00000030
 Shift and Rotate Instructions (cont.)

LSR (Logical Shift Right)

• LSRis a logical shift right by 0 to 32 places.
The vacated bits at the most significant endof
the word are filled with zeros.
10100101100011010011010001101001

0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0

LSR #4
 Shift and Rotate Instructions (cont.)

Example: Logical shift right (LSR)

0 Register C
MOV R0, R2, LSR #2 @ R0:=R2>>2
@ R2 unchanged
Example: 0…0 0011 0000
Before R2=0x00000030
After R0=0x0000000C
R2=0x00000030
 Shift and Rotate Instructions (cont.)

ASL (Arithmetic Shift Left)

• ASLis an arithmetic shift left by 0 to 31 places. The vacated bits at
the least significant end of the word are filled with zeros.
• It is identical to LSL. In code terms, it is written in the same syntactic
form:

MOV r0, r1, ASL#4 ; shift value in r1 4 places left and fill in vacant slots with 0’s
MOV r0, r1, ASLr2 ; shift value in r1 by number of places given in r2 and fill in
vacant slots with 0’s

1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1

0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0

ASL#4
 Shift and Rotate Instructions (cont.)
ASR (Arithmetic Shift Right)
• ASRis an arithmetic shift right by 0 to 32places.
• The vacated bits at the most significant end of the
word are filled with zeros if the original value (the
source operand) was positive.
MOV r0, r1, ASL#4 ; shift value in r1 4 places left and fill in vacant bits with copies
of original MSB.
MOV r0, r1, ASLr2 ; shift value in r1 by number of places given in r2 and fill in
vacant bits with copies of original MSB.
00100101100011010011010001101001

0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0

ASR #4
 Shift and Rotate Instructions (cont.)
• The vacated bits are filled with ones if the original
value was negative.
• This is known as "sign extending" because the most
significant bit of the original value is the sign bit for 2's
complement numbers, i.e. 0 for positive and 1 for
negative numbers.
• Arithmetic shifting therefore preserves the sign of
numbers.
10100101100011010011010001101001

1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 1 0

ASR #4
 Shift and Rotate Instructions (cont.)

Example: Arithmetic shift right (ASR)

MSB Register C

MOV R0, R2, ASR #2 @ R0:=R2>>2

@ R2 unchanged
Example: 1010 0…0 00110000
Before R2=0xA0000030
After R0=0xE800000C
R2=0xA0000030
 Shift and Rotate Instructions (cont.)
ROR (Rotate right)
• RORbehaves much like LSRin that bits are moved between 0 and 32 places to the
right.
• However, whereas the rightmost bits in a LSRoperation fall off the register, in a
RORoperation, these bits are used to fill the vacated slots at the most significant
end of the register. In this way the bits "rotate".
• If the degree of the rotation is 32 places, then the output is identical to the input
as all the bits will have returned to their original location.
• RORcan be used with a literal or by sourcing the rotation from a register.
MOV r0, r0, ROR#3 ; rotate value in r0 3 places and put result in r0.
MOV r2, r0, RORr1 ; rotate r0 by value of places in r1 and put result in r2.

10100101100011010011010001101001

10011010010110001101001101000110

ASR #4
 Shift and Rotate Instructions (cont.)
Example: Rotate right (ROR)

Register C

MOV R0, R2, ROR #2 @ R0:=R2 rotate

@ R2 unchanged
Example: 0…0 0011 0001
Before R2=0x00000031
After R0=0x4000000C
R2=0x00000031
 Shift and Rotate Instructions (cont.)

RRX (Rotate Right with Extend)

• It rotates the number to the right by one place but the
original bit 31 is filled by the value of the Carry flag and the
original bit 0 is moved into theCarry flag.
• This allows a 33-bit rotation by using both the registerand
the carry flag.
MOV r0, r0, RRX ; rotate right extended and put result back into r0

C 31 0
0 10100101100011010011010001101001

1 0101001011000110100110100011010 0
RRX
 Shift and Rotate Instructions (cont.)

Example: Rotate right with extend (RRX)

Register C

MOV R0, R2, RRX @ R0:=R2 rotate

@ R2 unchanged
Example: 0…0 0011 0001
Before R2=0x00000031, C=1
After R0=0x80000018, C=1
R2=0x00000031
 Exercise 12

(a) Based on the above figure, access the values stored in register r0, r1 andr2
after the program completes.
(b) Change the program in the figure above by replacing the lastMOV
instruction with

ADD r2, r1, r1, LSL#2

Access the value in register r2 when the program reaches the infiniteloop
(the Binstruction).
 Answer Exercise 12

(c) (i) r0 = 0×11, r1 = 0×22, r2 = 0×44

(ii) r2 = 0×88