Intel 8085 Architecture

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is connected to internal data bus &
ALU.
Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit data.
General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be executed. Microprocessor
increments the program whenever an instruction is being executed, so that the program counter points to the memory address of
the next instruction that is going to be executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result stored in the accumulator.
These are the set of 5 flip-flops −

 Sign (S)

 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)
Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the Instruction register. Instruction
decoder decodes the information present in the Instruction register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following are the timing and control signals,
which control external and internal circuits −

 Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’

 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT

Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is executing a main program and
whenever an interrupt occurs, the microprocessor shifts the control from the main program to process the incoming request.
After the request is completed, the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.
Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial input data) and SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address buffer and address-data buffer to
communicate with the CPU. The memory and I/O chips are connected to these buses; the CPU can exchange the desired data
with the memory and I/O chips.
Address bus and data bus
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location to where it should be stored
and it is unidirectional. It is used to transfer the data & Address I/O devices.

Pin description
The 8085 and Its Buses

 The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory.
 It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz.
 The pins on the chip can be grouped into 6 groups:
 Address Bus.
 Data Bus.
 Control and Status Signals.
 Power supply and frequency.
 Externally Initiated Signals.
 Serial I/O ports.

8085 Pin description 

 Higher Order Address pins- A15 – A8

 The address bus has 8 signal lines A8 – A15 which are unidirectional.
 Lower Order Address/ Data Pins- AD7-AD0
 These are time multiplexed pins and are de-multiplexed using the pin ALE
 So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time.
 During the execution of the instruction, these lines carry the address bits during the early part,
then during the late parts of the execution, they carry the 8 data bits.
 In order to separate the address from the data, we can use a latch to save the value before the function of
the bits changes.
 Control Pins – RD, WR
 These are active low Read & Write pins
 Status Pins – ALE, IO/M (active low), S1, S0
 ALE (Address Latch Enable)-Used to de-multiplex AD7-AD0
 IO/M – Used to select I/O or Memory operation
 S1,S0 – Denote the status of data on data bus
 Interrupt Pins – TRAP, RST7.5, RST 6.5, RST 5.5, INTR, INTA
 These are hardware interrupts used to initiate an interrupt service routine stored at predefined locations of
the system memory.
 Serial I/O pins – SID (Serial Input Data), SOD (Serial Output Data)
 These pins are used to interface 8085 with a serial device.
 Clock Pins- X1, X2, CLK(OUT)
 X1, X2– These are clock input pins. A crystal is connected between these pins such that f crystal= 2f8085 where
fcrystal= crystal frequency & f8085 = operating frequency of 8085
 CLK(OUT) – This is an auxiliary clock output source
 Reset Pins – Reset In (active low), Reset Out
  Reset In is used to reset 8085 whereas Reset Out can be used to reset other devices in the system
 DMA (Direct Memory Access) pins – HOLD, HLDA
 These pins are used when data transfer is to be performed directly between an external device and the main
memory of the system.
 Power Supply Pins – +VCC, VSS

INTERRUPTS OF INTEL 8085

NEED FOR INTERRUPTS
Interrupt is a signal send by an external device to the processor, to the
processor to perform a particular task or work. Mainly in the microprocessor based system the
interrupts are used for data transfer between the peripheral and the microprocessor. When a peripheral
is ready for data transfer, it interrupts the processor by sending an appropriate signal to the interrupt pin
of the processor. If the processor accepts the interrupt then the processor suspends its current activity
and executes an interrupt service subroutine to complete the data transfer between the peripheral and
processor. After executing the interrupt service routine the processor resumes its current activity. This
type of data transfer scheme is called interrupt driven data transfer scheme.

TYPES OF INTERRUPTS:

The interrupts are classified into software interrupts and hardware interrupts.

Software interrupts:
software interrupt are program instructions. These instructions are inserted at
desired locations in a program. While running a program, if a software interrupt instruction is
encountered, then the processor executes an interrupt service routine (ISR). • The hardware interrupts
are initiated by an external device by placing an appropriate signal at the interrupt pin of the processor.
If the interrupt is accepted, then the processor executes an interrupt service routine (ISR). software
interrupt of 8085 The software interrupts are program instructions. When the instruction is executed,
the processor executes an interrupt service routine stored in the vector address of the software interrupt
instruction. The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6
and RST 7. The vector addresses of software interrupts are given in table below. The software interrupt
instructions are included at the appropriate (or required) place in the main program. When the
processor encounters the software instruction, it pushes the content of PC (Program Counter) to stack.
Then loads the Vector address in PC and starts executing the Interrupt Service Routine (ISR) stored in
this vector address. At the end of ISR, a return instruction - RET will be placed. When the RET
instruction is executed, the processor POP the content of stack to PC. Hence the processor control
returns to the main program after servicing the interrupt. Execution of ISR is referred to as servicing of
interrupt. All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be
masked and they cannot be disabled. The software interrupts are RST0, RST1, … RST7 (8 Nos).

HARDWARE INTERRUPTS OF 8085:

 An external device, initiates the hardware interrupts of 8O85
by placing an appropriate signal at the interrupt pin of the processor. The processor keeps on checking
the interrupt pins at the second T -state of last machine cycle of every instruction. If the processor finds
a valid interrupt signal and if the interrupt is unmasked and enabled, then the processor accepts the
interrupt. The acceptance of the interrupt is acknowledged by sending an INTA signal to the
interrupted device. The processor saves the content of PC (program Counter) in stack and then loads
the vector address of the interrupt in PC. (If the interrupt is non-vectored, then the interrupting device
has to supply the address of ISR when it receives INTA signal). It starts executing ISR in this address.
At the end of ISR, a return instruction, RET will be placed. When the processor executes the RET
instruction, it POP the content of top of stack to PC. Thus the processor control returns to main
program after servicing interrupt. The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST
5.5 and INTR.

Further the interrupts may be classified into VECTORED / NON-VECTORED and MASKABLE /
NON-MASKABLE

VECTORED INTERRUPT: In vectored interrupts, the processor automatically branches to the specific
address in response to an

NON-VECTORED INTERRUPT: But in non-vectored interrupts the interrupted device should give the
address of the interrupt service routine (ISR).

In vectored interrupts, the manufacturer fixes the address of the ISR to which the program control is to
be transferred.

• The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.

• The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has to supply
the address of ISR after receiving interrupt acknowledge signal.

MASKABLE & NON-MASKABLE INETRRUPTS:

The hardware vectored interrupts are classified into maskable and non-maskable interrupts.

• TRAP is non-maskable interrupt

• RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.

Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked the
processor will not accept the interrupt signal. The interrupts can be masked by moving an appropriate
data (or code) to accumulator and then executing SIM instruction. (SIM - Set Interrupt Mask). The
status of maskable interrupts can be read into accumulator by executing RIM instruction (RIM - Read
Interrupt Mask). All the hardware interrupts, except TRAP are disabled, when the processor is resetted.
They can also be disabled by executing Dl instruction. (Dl-Disable Interrupt).

• When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST 5.5, RST 6.5
and RST 7.5 are disabled by DI instruction and upon hardware reset).

• To enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-Enable
Interrupt). The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085
are defined by INTEL.

• The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal has to
make a low to high transition and then it has to remain high until the interrupt is recognized.
• The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the interrupt signal
has to make a low to high transition an it need not remain high until it is recognized.

• The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts the
interrupting signal should remain high, until it is recognized.