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SN54HC244, SN74HC244
SCLS130E – DECEMBER 1982 – REVISED MAY 2016

SNx4HC244 Octal Buffers and Line Drivers With 3-State Outputs

1 Features 3 Description
•
1 Wide Operating Voltage Range of 2 V to 6 V The SNx4HC244 octal buffers and line drivers are
designed specifically to improve both the
• High-Current Outputs Drive Up to 15 LSTTL performance and density of 3-state memory address
Loads drivers, clock drivers, and bus-oriented receivers and
• 3-State Outputs Drive Bus Lines or Buffer Memory transmitters. The SNx4HC244 devices are organized
Address Registers as two 4-bit buffers and drivers with separate output-
• Low Power Consumption: ICC, 80-µA (Maximum) enable (OE) inputs. When OE is low, the device
passes noninverted data from the A inputs to the Y
• Typical tpd = 11 ns outputs. When OE is high, the outputs are in the
• ±6-mA Output Drive at 5 V high-impedance state.
• Low Input Current of 1 µA (Maximum)
Device Information(1)
• On Products Compliant to MIL-PRF-38535,
PART NUMBER PACKAGE (PINS) BODY SIZE (NOM)
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production CDIP (20) 6.92 mm × 24.38 mm
Processing Does Not Necessarily Include Testing SN54HC244 CFP (20) 6.92 mm × 13.72 mm
of All Parameters. LCCC (20) 8.89 mm × 8.89 mm
SN74HC244DB SSOP (20) 5.30 mm × 7.25 mm
2 Applications SN74HC244DW SOIC (20) 7.50 mm × 12.80 mm
• Servers SN74HC244N PDIP (20) 6.30 mm × 25.40 mm
• LED Displays SN74HC244NS SOP (20) 5.30 mm × 12.60 mm

• Network Switches SN74HC244PW TSSOP (20) 4.40 mm × 6.50 mm

• Telecom Infrastructure (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Motor Drivers
• I/O Expanders
Logic Diagram (Positive Logic)

1OE 1 2OE 19

2 18 1Y1 11 9 1Y1
1A1 2A1

4 16 1Y1 13 7 1Y1
1A2 2A2

6 14 1Y1 15 5 1Y1
1A3 2A3

8 12 1Y4 17 3 1Y4
1A4 2A4

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC244, SN74HC244
SCLS130E – DECEMBER 1982 – REVISED MAY 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................ 11
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 11
3 Description ............................................................. 1 8.3 Feature Description................................................. 11
8.4 Device Functional Modes ....................................... 11
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
6 Specifications......................................................... 4
9.2 Typical Application .................................................. 12
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4 10 Power Supply Recommendations ..................... 13
6.3 Recommended Operating Conditions....................... 4 11 Layout................................................................... 13
6.4 Thermal Information .................................................. 5 11.1 Layout Guidelines ................................................. 13
6.5 Electrical Characteristics........................................... 5 11.2 Layout Example .................................................... 13
6.6 Electrical Characteristics – SN54HC244 .................. 5 12 Device and Documentation Support ................. 14
6.7 Electrical Characteristics – SN74HC244 .................. 6 12.1 Related Links ........................................................ 14
6.8 Switching Characteristics .......................................... 6 12.2 Community Resources.......................................... 14
6.9 Switching Characteristics – CL = 50 pF .................... 7 12.3 Trademarks ........................................................... 14
6.10 Switching Characteristics – CL = 150 pF ................ 7 12.4 Electrostatic Discharge Caution ............................ 14
6.11 Typical Characteristic.............................................. 8 12.5 Glossary ................................................................ 14
7 Parameter Measurement Information .................. 9 13 Mechanical, Packaging, and Orderable
8 Detailed Description ............................................ 11 Information ........................................................... 14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (August 2003) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Added Military Disclaimer to Features section ....................................................................................................................... 1
• Added Applications section .................................................................................................................................................... 1
• Removed Ordering Information table ..................................................................................................................................... 1
• Added Device Information table ............................................................................................................................................. 1

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5 Pin Configuration and Functions

DB, DW, J, N, NS, PW, W Package

20-Pin SSOP, SOIC, CDIP, PDIP, SOP, TSSOP, or CFP FK Package
Top View 20-Pin LCCC
Top View

VCC
1OE

2OE
2Y4

1A1
1OE 1 20 VCC

1A1 2 19 2OE

20

19
2Y4 3 18 1Y1
1A2 4 18 1Y1
1A2 4 17 2A4
2Y3 5 17 2A4
2Y3 5 16 1Y2
1A3 6 16 1Y2
1A3 6 15 2A3
2Y2 7 15 2A3
2Y2 7 14 1Y3
1A4 8 14 1Y3
1A4 8 13 2A2

10

12

13
11
2Y1 9 12 1Y4

9
GND 10 11 2A1

2Y1

GND

2A1

1Y4

2A2
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1OE I Output Enable
2 1A1 I Input
3 2Y4 O Output
4 1A2 I Input
5 2Y3 O Output
6 1A3 I Input
7 2Y2 O Output
8 1A4 I Input
9 2Y1 O Output
10 GND — Ground
11 2A1 I Input
12 1Y4 O Output
13 2A2 I Input
14 1Y3 O Output
15 2A3 I Input
16 1Y2 O Output
17 2A4 I Input
18 1Y1 O Output
19 2OE I Output Enable
20 VCC — Power Pin

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage range, VCC –0.5 7 V
(2)
Input clamp current, IIK VI < 0 or VI > VCC ±20 mA
Output clamp current, IOK VO < 0 or VO > VCC (2) ±20 mA
Continuous output current, IO VO = 0 or VCC ±35 mA
Continuous current through VCC or GND ±70 mA
Junction Temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

SN74HC244 VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
Δt/Δv Input transition rise and fall time VCC = 4.5 V 500 ns/V
VCC = 6 V 400
Cpd Power dissipation capacitance per buffer or driver (no load) 35 pF
SN54HC244 –55 125
TA Operating free-air temperature °C
SN74HC244 –40 85

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Texas Instruments application
report, Implications of Slow or Floating CMOS Inputs, SCBA004.

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6.4 Thermal Information

SN54HC244, SN74HC244
THERMAL METRIC (1) DB (SSOP) DW (SOIC) N (PDIP) NS (SOP) PW (TSSOP) UNIT
20 PINS 20 PINS 20 PINS 20 PINS 20 PINS
Junction-to-ambient thermal
RθJA 89.5 76.8 44.9 71.9 97.5 °C/W
resistance
Junction-to-case (top) thermal
RθJC(top) 50.9 42.2 30.9 38.2 32.6 °C/W
resistance
RθJB Junction-to-board thermal resistance 44.6 44.6 25.8 39.3 48.4 °C/W
Junction-to-top characterization
ψJT 17 15.6 16.4 14.9 1.7 °C/W
parameter
Junction-to-board characterization
ψJB 44.2 44.1 25.7 39 47.9 °C/W
parameter

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 2 V 1.9 1.998
IOH = –20 µA VCC = 4.5 V 4.4 4.499
VOH VI = VIH or VIL VCC = 6 V 5.9 5.999 V
IOH = –6 mA, VCC = 4.5 V 3.98 4.3
IOH = –7.8 mA, VCC = 6 V 5.48 5.8
VCC = 2 V 0.002 0.1
IOL = 20 µA VCC = 4.5 V 0.001 0.1
VOL VI = VIH or VIL VCC = 6 V 0.001 0.1 V
IOL = 6 mA, VCC = 4.5 V 0.17 0.26
IOL = 7.8 mA, VCC = 6 V 0.15 0.26
II VI = VCC or 0, VCC = 6 V ±0.1 ±100 nA
IOZ VO = VCC or 0, VI = VIH or VIL, VCC = 6 V ±0.01 ±0.5 µA
ICC VI = VCC or 0, IO = 0, VCC = 6 V 8 µA
Ci VCC = 2 V to 6 V 3 10 pF

6.6 Electrical Characteristics – SN54HC244

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 2 V 1.9
IOH = –20 µA VCC = 4.5 V 4.4
VOH VI = VIH or VIL VCC = 6 V 5.9 V
IOH = –6 mA, VCC = 4.5 V 3.7
IOH = –7.8 mA, VCC = 6 V 5.2
VCC = 2 V 0.1
IOL = 20 µA VCC = 4.5 V 0.1
VOL VI = VIH or VIL VCC = 6 V 0.1 V
IOL = 6 mA, VCC = 4.5 V 0.4
IOL = 7.8 mA, VCC = 6 V 0.4
II VI = VCC or 0, VCC = 6 V ±1000 nA
IOZ VO = VCC or 0, VI = VIH or VIL, VCC = 6 V ±10 µA
ICC VI = VCC or 0, IO = 0, VCC = 6 V 160 µA
Ci VCC = 2 V to 6 V 10 pF

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6.7 Electrical Characteristics – SN74HC244

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 2 V 1.9
IOH = –20 µA VCC = 4.5 V 4.4
VOH VI = VIH or VIL VCC = 6 V 5.9 V
IOH = –6 mA, VCC = 4.5 V 3.84
IOH = –7.8 mA, VCC = 6 V 5.34
VCC = 2 V 0.1
IOL = 20 µA VCC = 4.5 V 0.1
VOL VI = VIH or VIL VCC = 6 V 0.1 V
IOL = 6 mA, VCC = 4.5 V 0.33
IOL = 7.8 mA, VCC = 6 V 0.33
II VI = VCC or 0, VCC = 6 V ±1000 nA
IOZ VO = VCC or 0, VI = VIH or VIL, VCC = 6 V ±5 µA
ICC VI = VCC or 0, IO = 0, VCC = 6 V 80 µA
Ci VCC = 2 V to 6 V 10 pF

6.8 Switching Characteristics

TA = 25°C (unless otherwise noted; see Figure 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CL = 50 pF 40 115
VCC = 2 V
CL = 150 pF 56 165
CL = 50 pF 13 23
tpd From A (input) to Y (output) VCC = 4.5 V ns
CL = 150 pF 18 33
CL = 50 pF 11 20
VCC = 6 V
CL = 150 pF 15 28
CL = 50 pF 75 150
VCC = 2 V
CL = 150 pF 100 200
CL = 50 pF 15 30
ten From OE (input) to Y (output) VCC = 4.5 V ns
CL = 150 pF 20 40
CL = 50 pF 13 26
VCC = 6 V
CL = 150 pF 17 34
VCC = 2 V CL = 50 pF 75 150
tdis From OE (input) to Y (output) VCC = 4.5 V CL = 50 pF 15 30 ns
VCC = 6 V CL = 50 pF 13 26
CL = 50 pF 28 60
VCC = 2 V
CL = 150 pF 45 210
CL = 50 pF 8 12
tt To Y (output) VCC = 4.5 V ns
CL = 150 pF 17 42
CL = 50 pF 6 10
VCC = 6 V
CL = 150 pF 13 36

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6.9 Switching Characteristics – CL = 50 pF

over recommended operating free-air temperature range (unless otherwise noted; see Figure 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SN54HC244 170
VCC = 2 V
SN74HC244 145
SN54HC244 34
tpd From A (input) to Y (output) VCC = 4.5 V ns
SN74HC244 29
SN54HC244 29
VCC = 6 V
SN74HC244 25
SN54HC244 225
VCC = 2 V
SN74HC244 190
SN54HC244 45
ten From OE (input) to Y (output) VCC = 4.5 V ns
SN74HC244 38
SN54HC244 38
VCC = 6 V
SN74HC244 32
SN54HC244 225
VCC = 2 V
SN74HC244 190
SN54HC244 45
tdis From OE (input) to Y (output) VCC = 4.5 V ns
SN74HC244 38
SN54HC244 38
VCC = 6 V
SN74HC244 32
SN54HC244 90
VCC = 2 V
SN74HC244 75
SN54HC244 18
tt To Y (output) VCC = 4.5 V ns
SN74HC244 15
SN54HC244 15
VCC = 6 V
SN74HC244 13

6.10 Switching Characteristics – CL = 150 pF

over recommended operating free-air temperature range (unless otherwise noted; see Figure 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SN54HC244 245
VCC = 2 V
SN74HC244 210
SN54HC244 49
tpd From A (input) to Y (output) VCC = 4.5 V ns
SN74HC244 42
SN54HC244 42
VCC = 6 V
SN74HC244 35
SN54HC244 300
VCC = 2 V
SN74HC244 250
SN54HC244 60
ten From OE (input) to Y (output) VCC = 4.5 V ns
SN74HC244 50
SN54HC244 51
VCC = 6 V
SN74HC244 43
SN54HC244 315
VCC = 2 V
SN74HC244 265
SN54HC244 63
tt To Y (output) VCC = 4.5 V ns
SN74HC244 53
SN54HC244 53
VCC = 6 V
SN74HC244 45

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6.11 Typical Characteristic

60

50

40

tpd (ns)
30

20

10
CL 50pF
0 CL 150pF
2 3 4 5 6
VCC (V) C001

Figure 1. Propagation Delay

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7 Parameter Measurement Information

VCC

S1
Test
Point RL
From Output
Under Test
CL
S2
(see Note A)

Figure 2. Load Circuit

VCC
Input 50% 50%
0V
tPLH tPHL

In-Phase VOH
90% 90%
Output 50% 50%
10% 10% V
OL
tr tf
tPHL tPLH
VOH
Out-of-Phase 90% 90%
50% 50%
Output 10% 10%
VOL
tf tr

Figure 3. Propagation Delay and

Output Transition Times

VCC
Input 90% 90%
50% 50%
10% 10% 0 V
tr tf

Figure 4. Input Rise and Fall Times

Output
Control VCC
(Low-Level 50% 50%
Enabling) 0V
tPZL tPLZ
Output ≈VCC ≈VCC
Waveform 1 50%
(See Note B) 10% VOL
tPZH tPHZ
Output VOH
90%
Waveform 2 50%
(See Note B) ≈0 V

Figure 5. Enable and Disable Times

for 3-State Outputs

NOTE:
A. CL includes probe and test-fixture capacitance.

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Parameter Measurement Information (continued)

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by
the output control. Waveform 2 is for an output with internal conditions such that the output is high except
when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by
generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.

Table 1. Switching Information Table

PARAMETER RL CL S1 S2
tPZH 1 kΩ 50 pF or 150 pF Open Closed
ten
tPZL 1 kΩ 50 pF or 150 pF Closed Open
tPHZ 1 kΩ 50 pF Open Closed
tdis
tPLZ 1 kΩ 50 pF Closed Open
tpd or tt — 50 pF or 150 pF Open Open

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8 Detailed Description

8.1 Overview
The SNx4HC244 device is organized as two 4-bit buffers and line drivers with separate output-enable (OE)
inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-
sinking capability of the driver.

8.2 Functional Block Diagram

1OE 1 2OE 19

2 18 1Y1 11 9 1Y1
1A1 2A1

4 16 1Y1 13 7 1Y1
1A2 2A2

6 14 1Y1 15 5 1Y1
1A3 2A3

8 12 1Y4 17 3 1Y4
1A4 2A4

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8.3 Feature Description

The SNx4HC244 has a wide operating voltage of 2 V to 6 V. Inputs accept voltage levels up to VCC. This device
has a low power consumption of ICC 80 µA (maximum). The SNx4HC244 device can drive ±6 mA at VCC of 5 V.

8.4 Device Functional Modes

Table 2 lists the functions of the SNx4HC244.

Table 2. Function Table

(Each Buffer or Driver)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

SN74HC244 is a high-drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern.

9.2 Typical Application

Regulated 3V

SN74HC244

1OE VCC

A1 Y1
x MCU System
MCU or x x x
x x x Logic LEDS
System x
Logic x x x x
A4 Y4

GND

Copyright © 2016, Texas Instruments Incorporated

Figure 6. SN74HC244 Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads so
routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/ΔV in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
2. Recommend output conditions:
– Load currents should not exceed IO max per output and should not exceed the continuous current through
VCC or GND total current for the part. These limits are located in Absolute Maximum Ratings.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

9.2.3 Application Curve
100
90
80
70
60

ten (ns)
50
40
30
20
10 CL 50pF
0 CL 150pF
2 3 4 5 6
VCC (V) C002

Figure 7. Enable Time

10 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recomments a 0.1-μF capacitor. If there are multiple VCC terminals, then TI recommends 0.01-μF or
0.022-μF capacitors for each power terminal. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The
bypass capacitor should be installed as close to the power terminal as possible for the best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input and gate are used, or
when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.

11.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

Figure 8. Layout Diagram

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12 Device and Documentation Support

12.1 Related Links

Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54HC244 Click here Click here Click here Click here Click here
SN74HC244 Click here Click here Click here Click here Click here

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8409601VRA ACTIVE CDIP J 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 5962-8409601VR
Non-Green A
SNV54HC244J
5962-8409601VSA ACTIVE CFP W 20 25 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 5962-8409601VS
Non-Green A
SNV54HC244W
84096012A ACTIVE LCCC FK 20 1 Non-RoHS & POST-PLATE N / A for Pkg Type -55 to 125 84096012A
Non-Green SNJ54HC
244FK
8409601RA ACTIVE CDIP J 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 8409601RA
Non-Green SNJ54HC244J
8409601SA ACTIVE CFP W 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 8409601SA
Non-Green SNJ54HC244W
JM38510/65705B2A ACTIVE LCCC FK 20 1 Non-RoHS & POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
Non-Green 65705B2A
JM38510/65705BRA ACTIVE CDIP J 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 JM38510/
Non-Green 65705BRA
JM38510/65705BSA ACTIVE CFP W 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 JM38510/
Non-Green 65705BSA
M38510/65705B2A ACTIVE LCCC FK 20 1 Non-RoHS & POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
Non-Green 65705B2A
M38510/65705BRA ACTIVE CDIP J 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 JM38510/
Non-Green 65705BRA
M38510/65705BSA ACTIVE CFP W 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 JM38510/
Non-Green 65705BSA
SN54HC244J ACTIVE CDIP J 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 SN54HC244J
Non-Green
SN74HC244ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244A

SN74HC244APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244A

SN74HC244DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HC244DWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244DWRE4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244N ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type -40 to 85 SN74HC244N
Non-Green
SN74HC244NE4 ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type -40 to 85 SN74HC244N
Non-Green
SN74HC244NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244NSRG4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244PWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244PWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244PWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244PWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC244

SN74HC244QDWRG4Q1 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM HC244Q

SNJ54HC244FK ACTIVE LCCC FK 20 1 Non-RoHS & POST-PLATE N / A for Pkg Type -55 to 125 84096012A
Non-Green SNJ54HC
244FK
SNJ54HC244J ACTIVE CDIP J 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 8409601RA
Non-Green SNJ54HC244J
SNJ54HC244W ACTIVE CFP W 20 1 Non-RoHS & SNPB N / A for Pkg Type -55 to 125 8409601SA
Non-Green SNJ54HC244W

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC244, SN54HC244-SP, SN74HC244 :

• Catalog: SN74HC244, SN54HC244

• Automotive: SN74HC244-Q1, SN74HC244-Q1
• Enhanced Product: SN74HC244-EP, SN74HC244-EP

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

• Military: SN54HC244
• Space: SN54HC244-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC244ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HC244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74HC244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HC244DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74HC244DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74HC244DWRG4 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74HC244NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74HC244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HC244PWT TSSOP PW 20 250 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HC244QDWRG4Q1 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC244ADBR SSOP DB 20 2000 853.0 449.0 35.0
SN74HC244APWR TSSOP PW 20 2000 853.0 449.0 35.0
SN74HC244DBR SSOP DB 20 2000 853.0 449.0 35.0
SN74HC244DWR SOIC DW 20 2000 600.0 144.0 84.0
SN74HC244DWR SOIC DW 20 2000 350.0 350.0 43.0
SN74HC244DWRG4 SOIC DW 20 2000 367.0 367.0 45.0
SN74HC244NSR SO NS 20 2000 367.0 367.0 45.0
SN74HC244PWR TSSOP PW 20 2000 853.0 449.0 35.0
SN74HC244PWT TSSOP PW 20 250 853.0 449.0 35.0
SN74HC244QDWRG4Q1 SOIC DW 20 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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