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SN74LVC2244A
SCAS572L – APRIL 1996 – REVISED JULY 2014

SN74LVC2244A Octal Buffer/Driver With 3-State Outputs

1 Features 2 Applications
•
1 Operates From 1.65 V to 3.6 V • Wearable Health and Fitness Devices
• Inputs Accept Voltages to 5.5 V • Network Switches
• Max tpd of 5.5 ns at 3.3 V • Servers
• Output Ports Have Equivalent 26-Ω Series • Tests and Measurements
Resistors, So No External Resistors Are Required
• Typical VOLP (Output Ground Bounce) 3 Description
<0.8 V at VCC = 3.3 V, TA = 25°C The SN74LVC2244A octal buffer/line driver is
• Typical VOHV (Output VOH Undershoot) designed for 1.65-V to 3.6-V VCC operation.
>2 V at VCC = 3.3 V, TA = 25°C
Device Information(1)
• Supports Mixed-Mode Signal Operation on All PART NUMBER PACKAGE BODY SIZE (NOM)
Ports (5-V Input/Output Voltage
SSOP (20) 7.20 mm × 5.30 mm
With 3.3-V VCC)
SSOP (20) 8.65 mm × 3.90 mm
• Ioff Supports Live Insertion, Partial-Power-Down
SN74LVC2244A TVSOP (20) 5.00 mm × 4.40 mm
Mode, and Back-Drive Protection
SOIC (20) 12.80 mm × 7.50 mm
• Latch-Up Performance Exceeds 250 mA Per
TSSOP (20) 6.50 mm × 4.40 mm
JESD 17
(1) For all available packages, see the orderable addendum at
• ESD Protection Exceeds JESD 22 the end of the data sheet.
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

4 Simplified Schematic
1 19
1OE 2OE

2 18 11 9
1A1 1Y1 2A1 2Y1

4 16 13 7
1A2 1Y2 2A2 2Y2

6 14 15 5
1A3 1Y3 2A3 2Y3

8 12 17 3
1A4 1Y4 2A4 2Y4

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2244A
SCAS572L – APRIL 1996 – REVISED JULY 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 9 Detailed Description .............................................. 9
2 Applications ........................................................... 1 9.1 Overview ................................................................... 9
3 Description ............................................................. 1 9.2 Functional Block Diagram ......................................... 9
4 Simplified Schematic............................................. 1 9.3 Feature Description................................................... 9
9.4 Device Functional Modes.......................................... 9
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
7 Specifications......................................................... 4
10.2 Typical Application ............................................... 10
7.1 Absolute Maximum Ratings ..................................... 4
7.2 Handling Ratings....................................................... 4 11 Power Supply Recommendations ..................... 11
7.3 Recommended Operating Conditions ...................... 5 12 Layout................................................................... 11
7.4 Thermal Information .................................................. 5 12.1 Layout Guidelines ................................................. 11
7.5 Electrical Characteristics........................................... 6 12.2 Layout Example .................................................... 11
7.6 Switching Characteristics, –40°C to 85°C................. 6 13 Device and Documentation Support ................. 12
7.7 Switching Characteristics, –40°C to 125°C............... 6 13.1 Trademarks ........................................................... 12
7.8 Operating Characteristics.......................................... 7 13.2 Electrostatic Discharge Caution ............................ 12
7.9 Typical Characteristics .............................................. 7 13.3 Glossary ................................................................ 12
8 Parameter Measurement Information .................. 8 14 Mechanical, Packaging, and Orderable
Information ........................................................... 12

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision K (March 2005) to Revision L Page

• Updated document to new TI data sheet standards. ............................................................................................................. 1

• Deleted Ordering Information table. ....................................................................................................................................... 1
• Changed Ioff bullet in Features list. ......................................................................................................................................... 1
• Added Applications. ................................................................................................................................................................ 1
• Added Pin Functions table...................................................................................................................................................... 3
• Added Handling Ratings table. ............................................................................................................................................... 4
• Changed MAX ambient temperature to 125°C in Recommended Operating Conditions. .................................................... 5
• Added Thermal Information table. .......................................................................................................................................... 5
• Added –40°C to 125°C temperature range in Electrical Characteristics table. ...................................................................... 6
• Added data to Switching Characteristics, –40°C to 85°C....................................................................................................... 6
• Added Switching Characteristics table, –40°C to 125°C. ...................................................................................................... 6
• Changed Operating Characteristics table............................................................................................................................... 7
• Added Typical Characteristics. ............................................................................................................................................... 7
• Added Detailed Description section........................................................................................................................................ 9
• Added Application and Implementation section.................................................................................................................... 10

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6 Pin Configuration and Functions

DB, DBQ, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)

1OE 1 20 VCC
1A1 2 19 2OE
2Y4 3 18 1Y1
1A2 4 17 2A4
2Y3 5 16 1Y2
1A3 6 15 2A3
2Y2 7 14 1Y3
1A4 8 13 2A2
2Y1 9 12 1Y4
GND 10 11 2A1

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1OE I Output Enable 1
2 1A1 I 1A1 Input
3 2Y4 O 2Y4 Output
4 1A2 I 1A2 Input
5 2Y3 O 2Y3 Output
6 1A3 I 1A3 Input
7 2Y2 O 2Y2 Output
8 1A4 I 1A4 Input
9 2Y1 O 2Y1 Output
10 GND — Ground Pin
11 2A1 I 2A1 Input
12 1Y4 O 1Y4 Output
13 2A2 I 2A2 Input
14 1Y3 O 1Y3 Output
15 2A3 I 2A3 Input
16 1Y2 O 1Y2 Output
17 2A4 I 2A4 Input
18 1Y1 O 1Y1 Output
19 2OE I Output Enable 2
20 VCC — Power Pin

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3)
–0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
0 2000
pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
0 1000
JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Operating 1.65 3.6
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8
VI Input voltage 0 5.5 V
High or low state 0 VCC
VO Output voltage V
3-state 0 5.5
VCC = 1.65 V –2
VCC = 2.3 V –4
IOH High-level output current mA
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 1.65 V 2
VCC = 2.3 V 4
IOL Low-level output current mA
VCC = 2.7 V 8
VCC = 3 V 12
Δt/Δv Input transition rise or fall rate 10 ns/V
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).

7.4 Thermal Information

SN74LVC2244A
THERMAL METRIC (1) DB DBQ DGV DW NS PW UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 94.5 94.7 114.7 88.3 74.7 102.5
RθJC(top) Junction-to-case (top) thermal resistance 56.2 47.9 29.8 51.1 40.5 35.9
RθJB Junction-to-board thermal resistance 49.7 45.0 56.2 50.9 42.3 53.5
ψJT Junction-to-top characterization parameter 18.1 11.0 0.8 20.0 14.3 2.2 °C/W
Junction-to-board characterization
ψJB 49.5 44.6 55.5 50.5 41.9 52.9
parameter
Junction-to-case (bottom) thermal
RθJC(bot) n/a n/a n/a n/a n/a n/a
resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC (1)
UNIT
MIN TYP MAX MIN TYP (1) MAX
1.65 V to
IOH = –100 μA VCC – 0.2 VCC – 0.2
3.6 V
IOH = –2 mA 1.65 V 1.2 1.2
2.3 V 1.7 1.7
VOH IOH = –4 mA V
2.7 V 2.2 2.2
IOH = –6 mA 3V 2.4 2.4
IOH = –8 mA 2.7 V 2 2
IOH = –12 mA 3V 2 2
1.65 V to
IOL = 100 μA 0.2 0.2
3.6 V
IOL = 2 mA 1.65 V 0.45 0.45
2.3 V 0.7 0.7
VOL IOL = 4 mA V
2.7 V 0.4 0.4
IOL = 6 mA 3V 0.55 0.55
IOL = 8 mA 2.7 V 0.6 0.6
IOL = 12 mA 3V 0.8 0.8
II VI = 0 to 5.5 V 3.6 V ±5 ±5 μA
Ioff VI or VO = 5.5 V 0 ±10 ±10 μA
IOZ VO = 0 to 5.5 V 3.6 V ±10 ±10 μA
VI = VCC or GND 10 10
ICC IO = 0 3.6 V μA
3.6 V ≤ VI ≤ 5.5 V (2) 10 10
One input at VCC – 0.6 V, Other 2.7 V to
ΔICC 500 500 μA
inputs at VCC or GND 3.6 V
Ci VI = VCC or GND 3.3 V 4 4 pF
Co VO = VCC or GND 3.3 V 5.5 5.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

(2) This applies in the disabled state only.

7.6 Switching Characteristics, –40°C to 85°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
FROM TO VCC = 2.7 V
PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 10.9 7.9 6.4 1.5 5.5 ns
ten OE Y 12.6 9.6 8.1 1 7.1 ns
tdis OE Y 12.1 7.8 7.3 1.5 6.8 ns

7.7 Switching Characteristics, –40°C to 125°C

over operating free-air temperature range (unless otherwise noted)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
FROM TO VCC = 2.7 V
PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 12.4 10 7.1 1.5 6.5 ns
ten OE Y 14.1 11.7 8.5 1 7.8 ns
tdis OE Y 13.6 9.9 7.8 1.5 7.6 ns

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7.8 Operating Characteristics

TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP
Power dissipation capacitance Outputs enabled 43 43 46
Cpd f = 10 MHz pF
per buffer/driver Outputs disabled 1 1 2

7.9 Typical Characteristics

4 6
TDP in ns
3.5
5
3
4
2.5
TPD (ns)

TDP (ns)
2 3

1.5
2
1
1
0.5
TPD in ns
0 0
-100 -50 0 50 100 150 0 0.5 1 1.5 2 2.5 3 3.5
Temperature (qC) D001
VCC (V) D002

Figure 1. SN74LVC2244A TPD Across Temperature at 3.3 V Figure 2. SN74LVC2244A TDP Across VCC at 25°C

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8 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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9 Detailed Description

9.1 Overview
This octal buffer and line driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC2244A device is
organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes
data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The
outputs, which are designed to sink up to 12 mA, include equivalent 26-ohm resistors to reduce overshoot and
undershoot.

9.2 Functional Block Diagram

1 19
1OE 2OE

2 18 11 9
1A1 1Y1 2A1 2Y1

4 16 13 7
1A2 1Y2 2A2 2Y2

6 14 15 5
1A3 1Y3 2A3 2Y3

8 12 17 3
1A4 1Y4 2A4 2Y4

9.3 Feature Description

• Wide operating voltage range
– Operates from 1.65 V to 3.6 V
• Allows down voltage translation
– Inputs accept voltages to 5.5 V
• Ioff Feature
– Allows voltages on the inputs and outputs when VCC is 0 V

9.4 Device Functional Modes

Table 1. Function Table

(Each Buffer)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

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10 Application and Implementation

10.1 Application Information
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using
Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is
powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.

10.2 Typical Application

Regulated 3.3 V

OE VCC

A1 Y1
µC
System Logic

µC or A4 LEDs
Y4

System Logic
GND

Figure 4. Typical Application Diagram

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.

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Typical Application (continued)

10.2.3 Application Curves

300

250

200

ICC (mA)
150

100

50 ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
0
0 10 20 30 40 50 60
Frequency (MHz) D003
Figure 5. ICC vs Frequency

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled.

12.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 6. Layout Diagram

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13 Device and Documentation Support

13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC2244ADBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI -40 to 85

SN74LVC2244ADBQR ACTIVE SSOP DBQ 20 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244ADBQRE4 ACTIVE SSOP DBQ 20 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244ADBR ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244ADW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244ADWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244ANSR ACTIVE SO NS 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC2244A
& no Sb/Br)
SN74LVC2244APW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244APWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85
SN74LVC2244APWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC2244APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)
SN74LVC2244APWT ACTIVE TSSOP PW 20 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LE244A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 3-Jul-2014

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC2244ADBQR SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC2244ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LVC2244ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC2244ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74LVC2244ANSR SO NS 20 2000 330.0 24.4 9.0 13.0 2.4 4.0 24.0 Q1
SN74LVC2244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC2244APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC2244ADBQR SSOP DBQ 20 2500 367.0 367.0 38.0
SN74LVC2244ADBR SSOP DB 20 2000 367.0 367.0 38.0
SN74LVC2244ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0
SN74LVC2244ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LVC2244ANSR SO NS 20 2000 367.0 367.0 45.0
SN74LVC2244APWR TSSOP PW 20 2000 367.0 367.0 38.0
SN74LVC2244APWT TSSOP PW 20 250 367.0 367.0 38.0

Pack Materials-Page 2
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 IMPORTANT NOTICE

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