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SN74LVC125A
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015

SN74LVC125A Quadruple Bus Buffer Gate With 3-State Outputs

1 Features 3 Description
•
1 3-State Outputs This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
• Separate OE for all 4 buffers
• Operates From 1.65 V to 3.6 V The SN74LVC125A device features independent line
drivers with 3-state outputs. Each output is disabled
• Specified From –40°C to 85°C when the associated output-enable (OE) input is high.
and –40°C to 125°C
To ensure the high-impedance state during power up
• Inputs Accept Voltages to 5.5 V
or power down, OE should be tied to VCC through a
• Max tpd of 4.8 ns at 3.3 V pullup resistor; the minimum value of the resistor is
• Typical VOLP (Output Ground Bounce) determined by the current-sinking capability of the
< 0.8 V at VCC = 3.3 V, TA = 25°C driver.
• Typical VOHV (Output VOH Undershoot) Inputs can be driven from either 3.3-V or 5-V devices.
> 2 V at VCC = 3.3 V, TA = 25°C This feature allows the use of this device as a
• Latch-Up Performance Exceeds 250 mA translator in a mixed 3.3-V/5-V system environment.
Per JESD 17
Device Information(1)
• ESD Protection Exceeds JESD 22 PART NUMBER PACKAGE (PIN) BODY SIZE
– 2000-V Human-Body Model SOIC (14) 8.65 mm × 3.91 mm
– 200-V Machine Model SSOP (14) 6.20 mm × 5.30 mm
– 1000-V Charged-Device Model SN74LVC125A SOP (14) 10.30 mm × 5.30 mm
TSSOP (14) 5.00 mm × 4.40 mm
2 Applications VQFN (14) 3.50 mm × 3.50 mm

• Cable Modem Termination Systems (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• IP Phones: Wired and Wireless
• Optical Modules 4 Simplified Schematic
• Optical Networking:
– EPON or Video Over Fiber 1OE 3OE

• Point-to-Point Microwave Backhaul 1A 1Y 3A 3Y

• Power: Telecom DC/DC Modules: 2OE 4OE

– Analog or Digital 2A 2Y 4A 4Y

• Private Branch Exchanges (PBX)

• TETRA Base Stations
• Telecom Base Band Units
• Telecom Shelters:
– Filter Unit s
– Power Distribution Units (PDU)
– Power Monitoring Units (PMU)
– Wireless Battery Monitoring
– Remote Electrical Tilt Units (RET)
– Remote Radio Units (RRU)
– Tower Mounted Amplifiers (TMA)
• Vector Signal Analyzers and Generators
• Video Conferencing: IP-Based HD
• WiMAX and Wireless Infrastructure Equipment
• Wireless Communications Testers
• xDSL Modems and DSLAM
1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC125A
SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.1 Overview ................................................................... 9
2 Applications ........................................................... 1 9.2 Functional Block Diagram ......................................... 9
3 Description ............................................................. 1 9.3 Feature Description................................................... 9
9.4 Device Functional Modes.......................................... 9
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2 10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
6 Pin Configuration and Functions ......................... 3
10.2 Typical Application ............................................... 10
7 Specifications......................................................... 4
11 Power Supply Recommendations ..................... 11
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4 12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
7.3 Recommended Operating Conditions ...................... 5
12.2 Layout Example .................................................... 12
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 6 13 Device and Documentation Support ................. 13
7.6 Switching Characteristics .......................................... 6 13.1 Trademarks ........................................................... 13
7.7 Operating Characteristics.......................................... 6 13.2 Electrostatic Discharge Caution ............................ 13
7.8 Typical Characteristics .............................................. 7 13.3 Glossary ................................................................ 13
8 Parameter Measurement Information .................. 8 14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
9 Detailed Description .............................................. 9

5 Revision History
Changes from Revision P (October 2010) to Revision Q Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1

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6 Pin Configuration and Functions

D, DB, NS, OR PW PACKAGE
(TOP VIEW)

1OE 1 14 VCC
1A 2 13 4OE
1Y 3 12 4A
2OE 4 11 4Y
2A 5 10 3OE
2Y 6 9 3A
GND 7 8 3Y

RGY PACKAGE
(TOP VIEW)

1OE

VCC
1 14
1A 2 13 4OE
1Y 3 12 4A
2OE 4 11 4Y
2A 5 10 3OE
2Y 6 9 3A
7 8
GND

3Y

Pin Functions
PIN
D, DB, NS, PW TYPE DESCRIPTION
NAME
and RGY
1A 2 I Input
1OE 1 I Output enable
1Y 3 O Output
2A 5 I Input
2OE 4 I Output enable
2Y 6 O Output
3A 9 I Input
3OE 10 I Output enable
3Y 8 O Output
4A 12 I Input
4OE 13 I Output enable
4Y 11 O Output
GND 7 — Ground
VCC 14 — Power pin

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
(2)
VI Input voltage range –0.5 6.5 V
VO Output voltage range (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
(4) (5)
Ptot Power dissipation TA = –40°C to 125°C 500 mW
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
(4) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
(5) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.

7.2 ESD Ratings

PARAMETER DEFINITION VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000
Electrostatic
V(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101, all V
discharge 1000
pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
TA = 25°C –40°C to 85°C –40°C to 125°C
UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC 0.65 × VCC 0.65 × VCC
High-level
VIH VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V
input voltage
VCC = 2.7 V to 3.6 V 2 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC 0.35 × VCC 0.35 × VCC
Low-level
VIL VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 V
input voltage
VCC = 2.7 V to 3.6 V 0.8 0.8 0.8
VI Input voltage 0 5.5 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC 0 VCC V
VCC = 1.65 V –4 –4 –4
High-level VCC = 2.3 V –8 –8 –8
IOH mA
output current VCC = 2.7 V –12 –12 –12
VCC = 3 V –24 –24 –24
VCC = 1.65 V 4 4 4
Low-level VCC = 2.3 V 8 8 8
IOL mA
output current VCC = 2.7 V 12 12 12
VCC = 3 V 24 24 24
Δt/Δv Input transition rise or fall rate 8 8 8 ns/V

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4 Thermal Information

D (2) DB (2) NS (2) PW (2) RGY (3)
THERMAL METRIC (1) UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 86 96 76 113 47 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.

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7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
1.65 V to
IOH = –100 μA VCC – 0.2 VCC – 0.2 VCC – 0.3
3.6 V
IOH = –4 mA 1.65 V 1.29 1.2 1.05
VOH IOH = –8 mA 2.3 V 1.9 1.7 1.55 V
2.7 V 2.2 2.2 2.05
IOH = –12 mA
3V 2.4 2.4 2.25
IOH = –24 mA 3V 2.3 2.2 2
1.65 V to
IOL = 100 μA 0.1 0.2 0.3
3.6 V
IOL = 4 mA 1.65 V 0.24 0.45 0.6
VOL V
IOL = 8 mA 2.3 V 0.3 0.7 0.75
IOL = 12 mA 2.7 V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.8
II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 μA
IOZ VO = VCC or GND 3.6 V ±1 ±10 ±20 μA
ICC VI = VCC or GND, IO = 0 3.6 V 1 10 40 μA
One input at VCC – 0.6 V, 2.7 V to
ΔICC 500 500 5000 μA
Other inputs at VCC or GND 3.6 V
Ci VI = VCC or GND 3.3 V 5 pF

7.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM TO TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
1.8 V ± 0.15 V 1 4.5 11.8 1 12.3 1 13.8
2.5 V ± 0.2 V 1 2.7 5.8 1 6.3 1 8.4
tpd A Y ns
2.7 V 1 3 5.3 1 5.5 1 7
3.3 V ± 0.3 V 1 2.5 4.6 1 4.8 1 6
1.8 V ± 0.15 V 1 4.3 13.8 1 14.3 1 15.8
2.5 V ± 0.2 V 1 2.7 6.9 1 7.4 1 9.5
ten OE Y ns
2.7 V 1 3.3 6.4 1 6.6 1 8.5
3.3 V ± 0.3 V 1 2.4 5.2 1 5.4 1 7
1.8 V ± 0.15 V 1 4.3 10.6 1 11.1 1 12.6
2.5 V ± 0.2 V 1 2.2 5.1 1 5.6 1 7.7
tdis OE Y ns
2.7 V 1 2.5 4.8 1 5 1 6.5
3.3 V ± 0.3 V 1 2.4 4.4 1 4.6 1 6
tsk(o) 3.3 V ± 0.3 V 1 1.5 ns

7.7 Operating Characteristics

TA = 25°C
TEST
PARAMETER VCC TYP UNIT
CONDITIONS
1.8 V 7.4
Cpd Power dissipation capacitance per gate f = 10 MHz 2.5 V 11.3 pF
3.3 V 15

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7.8 Typical Characteristics

14 10
VCC = 3 V, VCC = 3 V,
TA = 25°C TA = 25°C
12

tpd – Propagation Delay Time – ns

One Output Switching
tpd – Propagation Delay Time – ns

One Output Switching

Four Outputs Switching 8 Four Outputs Switching
10

8 6

6
4
4

2 2
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition) Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance vs Load Capacitance

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8 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH - V∆
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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9 Detailed Description

9.1 Overview
The SN74LVC125A device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or
power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined
by the current-sourcing capability of the driver.

9.2 Functional Block Diagram

1OE 3OE

1A 1Y 3A 3Y

2OE 4OE

2A 2Y 4A 4Y

9.3 Feature Description

• Wide operating voltage range
– Operates from 1.65 V to 5.5 V
• Allows down voltage translation
• Inputs accept voltages to 5.5 V

9.4 Device Functional Modes

Table 1. Function Table

INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

SN74LVC125A is a high drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC
making it ideal for down translation.

10.2 Typical Application

3V
5V

1OE VCC

1Y
C/System
4OE
Logic/LEDs
C or System
4Y
Logic 1A

4A
GND

Figure 4. Typical Application Schematic

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended Input Conditions:
– For rise time and fall time specifcations, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.

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Typical Application (continued)

– Outputs should not be pulled above VCC.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.

10.2.3 Application Curves

100 60
TA = 25°C, VCC = 3 V, TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V, 40 VIH = 3 V, VIL = 0 V,
80 All Outputs Switching All Outputs Switching
20
60
0
I OL – mA

I OH – mA
40 –20

–40
20

–60
0
–80

–20 –100
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOL – V VOH – V

Figure 5. Output Drive Current (IOL) Figure 6. Output Drive Current (IOH)
vs LOW-level Output Voltage (VOL) vs HIGH-level Output Voltage (VOH)

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.

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12.2 Layout Example

VCC Input
Unused Input Output Unused Input Output

Input

Figure 7. Layout Diagram

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13 Device and Documentation Support

13.1 Trademarks
All trademarks are the property of their respective owners.

13.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC125AD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ADE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRG3 ACTIVE SOIC D 14 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ADTG4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ANSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC125A
& no Sb/Br)
SN74LVC125APW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC125APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS CU SN Level-1-260C-UNLIM LC125A
& no Sb/Br)
SN74LVC125APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC125A
& no Sb/Br)
SN74LVC125ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC125A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC125A :

• Automotive: SN74LVC125A-Q1
• Enhanced Product: SN74LVC125A-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Apr-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC125ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVC125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
SN74LVC125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
SN74LVC125ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC125ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC125APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC125APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC125APWRG3 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC125APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC125APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Apr-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC125ADBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LVC125ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LVC125ADR SOIC D 14 2500 364.0 364.0 27.0
SN74LVC125ADR SOIC D 14 2500 333.2 345.9 28.6
SN74LVC125ADRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74LVC125ADRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74LVC125ADRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74LVC125ADT SOIC D 14 250 367.0 367.0 38.0
SN74LVC125ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LVC125APWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC125APWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC125APWRG3 TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC125APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC125APWT TSSOP PW 14 250 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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