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TPS22967
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TPS22967 Single-Channel, Ultra-Low Resistance Load Switch

1 Features 3 Description
•
1 Integrated Single-Channel Load Switch The TPS22967 device is a small, ultra-low RON,
single-channel load switch with controlled turnon. The
• Input Voltage Range: 0.8 V to 5.5 V device contains an N-channel MOSFET that can
• Low RON Resistance operate over an input voltage range of 0.8 V to 5.5 V
– RON = 22 mΩ at VIN = 5 V (VBIAS = 5 V) and can support a maximum continuous current of
– RON = 22 mΩ at VIN = 3.6 V (VBIAS = 5 V) 4 A. The switch is controlled by an on/off input (ON),
which can interface directly with low-voltage control
– RON = 22 mΩ at VIN = 1.8 V (VBIAS = 5 V) signals. In the TPS22967, a 225-Ω pulldown resistor
• 4-A Maximum Continuous Switch Current is added for quick output discharge when the switch
• Low Quiescent Current (50 µA) is turned off.
• Low Control Input Threshold Enables Use of The TPS22967 is available in a small, space-saving
1.2-V, 1.8-V, 2.5-V, and 3.3-V Logic 2-mm × 2-mm 8-pin WSON package (DSG) with
integrated thermal pad allowing for high power
• Configurable Rise Time
dissipation. The device is characterized for operation
• Quick Output Discharge (QOD) over the free-air temperature range of –40°C to 85°C.
• WSON 8-Pin Package With Thermal Pad
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)

• Ultrabooks™ TPS22967 WSON (8) 2.00 mm × 2.00 mm

• Notebooks and Netbooks (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Tablet PCs
• Consumer Electronics
• Set-Top Boxes and Residental Gateways
• Telecom Systems
• Solid-State Drives (SSD)

4 Typical Application Schematic

Power VIN VOUT

Supply
ON
CIN ON CL
CT RL
OFF

GND
VBIAS GND
TPS22967

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 14
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 14
3 Description ............................................................. 1 8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
4 Typical Application Schematic............................. 1
5 Revision History..................................................... 2 9 Application and Implementation ........................ 16
9.1 Application Information............................................ 16
6 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 17
7 Specifications......................................................... 4
10 Power Supply Recommendations ..................... 19
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
7.3 Recommended Operating Conditions....................... 4
11.2 Layout Example .................................................... 20
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics: VBIAS = 5 V ...................... 5 12 Device and Documentation Support ................. 20
7.6 Electrical Characteristics: VBIAS = 2.5 V ................... 6 12.1 Trademarks ........................................................... 20
7.7 Switching Characteristics .......................................... 7 12.2 Electrostatic Discharge Caution ............................ 20
7.8 Typical Characteristics .............................................. 8 12.3 Glossary ................................................................ 20
8 Detailed Description ............................................ 14 13 Mechanical, Packaging, and Orderable
Information ........................................................... 20

5 Revision History
Changes from Original (August 2013) to Revision A Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

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6 Pin Configuration and Functions

DSG Package
8-Pin WSON

VIN 1 8 VOUT VOUT 8 1 VIN

VIN 2 7 VOUT VOUT 7 2 VIN

ON 3 6 CT CT 6 3 ON

VBIAS 4 5 GND GND 5 4 VBIAS

TOP VIEW BOTTOM VIEW

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Switch slew rate control. Can be left floating. See Application and Implementation for more
CT 6 O
information.
GND 5 – Device ground.
ON 3 I Active high switch control input. Do not leave floating.
Bias voltage. Power supply to the device. Recommended voltage range for this pin is 2.5 V to 5.5 V.
VBIAS 4 I
See Application Information section for more information.
Switch input. Input capacitor recommended for minimizing VIN dip. Recommended voltage range for
VIN 1, 2 I
this pin for optimal RON performance is 0.8 V to VBIAS.
VOUT 7, 8 O Switch output.
Thermal pad (exposed center pad) to alleviate thermal stress. Tie to GND. See Layout Example for
Thermal Pad –
layout guidelines.

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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT (2)
VIN Input voltage –0.3 6 V
VOUT Output voltage –0.3 6 V
VBIAS Bias voltage –0.3 6 V
VON ON voltage –0.3 6 V
IMAX Maximum continuous switch current 4 A
IPLS Maximum pulsed switch current, pulse <300 µs, 2% duty cycle 6 A
TA Operating free-air temperature (3) –40 85 °C
TJ Maximum junction temperature 125 °C
TLEAD Maximum lead temperature (10-s soldering time) 300 °C
TSTG Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max)).

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Input voltage 0.8 VBIAS V
VBIAS Bias voltage 2.5 5.5 V
VON ON voltage 0 5.5 V
VOUT Output voltage VIN V
High-level input voltage,
VIH VBIAS = 2.5 V to 5.5 V 1.2 5.5 V
ON
Low-level input voltage,
VIL VBIAS = 2.5 V to 5.5 V 0 0.5 V
ON
(1)
CIN Input capacitor 1 µF

(1) Refer to Application Information.

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7.4 Thermal Information

TPS22967
THERMAL METRIC (1) DSG [WSON] UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 65.3
RθJC(top) Junction-to-case (top) thermal resistance 74.2
RθJB Junction-to-board thermal resistance 35.4
°C/W
ψJT Junction-to-top characterization parameter 2.2
ψJB Junction-to-board characterization parameter 36
RθJC(bot) Junction-to-case (bottom) thermal resistance 12.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: VBIAS = 5 V

Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40°C ≤ TA ≤
85°C (Full) and VBIAS = 5 V. Typical values are for TA = 25°C.
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
IOUT = 0,
IIN(VBIAS-ON) VBIAS quiescent current Full 50 75 µA
VIN = VON = VBIAS = 5 V
IIN(VBIAS-OFF) VBIAS shutdown current VON = GND, VOUT = 0 V Full 2 µA
VIN = 5 V 0.2 8
VON = GND, VIN = 3.3 V 0.02 3
IIN(VIN-OFF) VIN off-state supply current Full µA
VOUT = 0 V VIN = 1.8 V 0.01 2
VIN = 0.8 V 0.005 1
ION ON pin input leakage current VON = 5.5 V Full 0.5 µA
RESISTANCE CHARACTERISTICS
25°C 22 33
VIN = 5 V
Full 35
25°C 22 33
VIN = 3.3 V
Full 35
25°C 22 33
VIN = 1.8 V
IOUT = –200 mA, Full 35
RON ON-state resistance mΩ
VBIAS = 5 V 25°C 22 33
VIN = 1.5 V
Full 35
25°C 22 33
VIN = 1.2 V
Full 35
25°C 22 33
VIN = 0.8 V
Full 35
RPD Output pulldown resistance VIN = 5.0 V, VON = 0V, IOUT = 15 mA Full 225 300 Ω

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7.6 Electrical Characteristics: VBIAS = 2.5 V

Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40°C ≤ TA ≤
85°C (Full) and VBIAS = 2.5 V. Typical values are for TA = 25°C.
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
IOUT = 0,
IIN(VBIAS-ON) VBIAS quiescent current Full 20 30 µA
VIN = VON = VBIAS = 2.5 V
IIN(VBIAS-OFF) VBIAS shutdown current VON = GND, VOUT = 0 V Full 2 µA
VIN = 2.5 V 0.01 3
VON = GND, VIN = 1.8 V 0.01 2
IIN(VIN-OFF) VIN off-state supply current Full µA
VOUT = 0 V VIN = 1.2 V 0.005 2
VIN = 0.8 V 0.003 1
ION ON pin input leakage current VON = 5.5 V Full 0.5 µA
RESISTANCE CHARACTERISTICS
25°C 26 38
VIN = 2.5 V
Full 40
25°C 26 38
VIN = 1.8 V
Full 40
IOUT = –200 mA, 25°C 25 38
RON ON-state resistance VIN = 1.5 V mΩ
VBIAS = 2.5 V Full 40
25°C 24 38
VIN = 1.2 V
Full 40
25°C 24 38
VIN = 0.8 V
Full 40
RPD Output pulldown resistance VIN = 2.5 V, VON = 0 V, IOUT = 1 mA Full 275 325 Ω

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7.7 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN = VON = VBIAS = 5 V, TA = 25ºC (UNLESS OTHERWISE NOTED)
tON Turnon time 1325
tOFF Turnoff time 10
tR VOUT rise time RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF 1625 µs
tF VOUT fall time 3.5
tD ON delay time 500
VIN = 0.8 V, VON = VBIAS = 5 V, TA = 25ºC (UNLESS OTHERWISE NOTED)
tON Turnon time 600
tOFF Turnoff time 80
tR VOUT rise time RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF 300 µs
tF VOUT fall time 5.5
tD ON delay time 460
VIN = 2.5 V, VON = 5 V, VBIAS = 2.5 V, TA = 25ºC (UNLESS OTHERWISE NOTED)
tON Turnon time 2200
tOFF Turnoff time 9
tR VOUT rise time RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF 2275 µs
tF VOUT fall time 3.1
tD ON delay time 1075
VIN = 0.8 V, VON = 5 V, VBIAS = 2.5 V, TA = 25ºC (UNLESS OTHERWISE NOTED)
tON Turn-on time 1450
tOFF Turn-off time 60
tR VOUT rise time RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF 875 µs
tF VOUT fall time 5.5
tD ON delay time 1010

VIN VOUT
CIN = 1µF
ON CT
+ ON CL
(A)
- RL
OFF
VBIAS
GND
TPS22967
GND GND

TEST CIRCUIT

VON
50% 50%

tF
tOFF tR
tON
90% 90%
VOUT
VOUT 50% 50%
10% 10% 10%

tD

t ON/t OFF WAVEFORMS

(A) Rise and fall times of the control signal is 100ns.

Figure 1. Test Circuit and Timing Waveforms

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7.8 Typical Characteristics

Figure 2. VBIAS vs Quiescent Current Figure 3. VBIAS vs Shutdown Current

33
VIN = 0.8V
32 VIN = 1.05V
VIN = 1.2V
31 VIN = 1.5V
30 VIN = 1.8V
VIN =2.5V
29
28
27

RON (m )
26
25
24
23
22
21
20
19 VBIAS=2.5V, IOUT=-200mA

18
-40 -15 10 35 60 85
Temperature (ºC)
C002

Figure 4. VIN vs Off-State VIN Current Figure 5. Temperature vs RON (VBIAS = 2.5 V)
28 35
VIN = 0.8V -40C
27.5 VIN = 1.05V 34
27 VIN = 1.2V
26.5 33 25C
VIN = 1.5V
26 VIN = 1.8V 32 85C
25.5 VIN = 2.5V 31
25 VIN = 3.3V 70C
24.5 VIN = 3.6V 30
24 VIN = 4.2V 29
23.5 VIN =5V
VIN = 5.5V 28
23
RON (m )

RON (m )

22.5 27
22 26
21.5 25
21
20.5 24
20 23
19.5 22
19
18.5 21
18 20
17.5 19
17
16.5 VBIAS=5.5V, IOUT = -200mA 18 VBIAS=2.5V, IOUT = -200mA
16 17
-40 -15 10 35 60 85 0.8 1.2 1.6 2 2.4
Temperature (ƒC) VIN (V)
C002 C002

Figure 6. Temperature vs RON (VBIAS = 5.5 V) Figure 7. VIN vs RON (VBIAS = 2.5 V)

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Typical Characteristics (continued)

33 27
-40C VBIAS = 2.5V

31 25C VBIAS = 3.3V

26
70C VBIAS = 3.6V
29
85C VBIAS = 4.2V

27 25 VBIAS = 5V
VBIAS = 5.5V

RON (mΩ)
RON (m )

25
24
23

21 23

19
22
17
Temperature=25C, IOUT = -200mA
VBIAS=5.5V, IOUT = -200mA
15 21
0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6
VIN (V) VIN (V)
C002
C002

Figure 8. VIN vs RON (VBIAS = 5.5 V) Figure 9. VIN vs RON (TA = 25°C)

Figure 10. VIN vs RPD (VBIAS = 5.5 V) Figure 11. VON vs VOUT (TA = 25°C)

Figure 12. VIN vs tD (VBIAS = 2.5 V, CT = 1 nF) Figure 13. VIN vs tD (VBIAS = 5.5 V, CT = 1 nF)

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Typical Characteristics (continued)

Figure 14. VIN vs tF (VBIAS = 2.5 V, CT = 1 nF) Figure 15. VIN vs tF (VBIAS = 5.5 V, CT = 1 nF)

Figure 16. VIN vs tOFF (VBIAS = 2.5 V, CT = 1 nF) Figure 17. VIN vs tOFF (VBIAS = 5.5 V, CT = 1 nF)

Figure 18. VIN vs tON (VBIAS = 2.5 V, CT = 1 nF) Figure 19. VIN vs tON (VBIAS = 5.5 V, CT = 1 nF)

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Typical Characteristics (continued)

Figure 20. VIN vs tR (VBIAS = 2.5 V, CT = 1 nF) Figure 21. VIN vs tR (VBIAS = 5.5 V, CT = 1 nF)

Figure 22. VBIAS vs tR (VIN = 2.5 V, CT = 1 nF)

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7.8.1 Typical AC Scope Captures at TA = 25ºC, CT = 1 nF

Figure 23. Turnon Response Time Figure 24. Turnon Response Time
(VIN = 0.8 V, VBIAS = 2.5 V, CIN = 1 µF, CL = 0.1 µF, (VIN = 0.8 V, VBIAS = 5 V, CIN = 1 µF, CL = 0.1 µF, RL = 10 Ω)
RL = 10 Ω) CH1: VOUT, CH2: ON
CH1: VOUT, CH2: ON

Figure 25. Turnon Response Time Figure 26. Turnon Response Time
(VIN = 2.5 V, VBIAS = 2.5 V, CIN = 1 µF, CL = 0.1 µF, (VIN = 5 V, VBIAS = 5 V, CIN = 1 µF, CL = 0.1 µF, RL = 10 Ω)
RL = 10 Ω) CH1: VOUT, CH2: ON
CH1: VOUT, CH2: ON

Figure 27. Turnoff Response Time Figure 28. Turnoff Response Time
(VIN = 0.8 V, VBIAS = 2.5 V, CIN = 1 µF, CL = 0.1 µF, (VIN = 0.8 V, VBIAS = 5 V, CIN = 1 µF, CL = 0.1 µF, RL = 10 Ω)
RL = 10 Ω) CH1: VOUT, CH2: ON
CH1: VOUT, CH2: ON

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Typical AC Scope Captures at TA = 25ºC, CT = 1 nF (continued)

Figure 29. Turnoff Response Time Figure 30. Turnoff Response Time
(VIN = 2.5 V, VBIAS = 2.5 V, CIN = 1 µF, CL = 0.1 µF, (VIN = 5 V, VBIAS = 5 V, CIN = 1 µF, CL = 0.1 µF, RL = 10 Ω)
RL = 10 Ω) CH1: VOUT, CH2: ON
CH1: VOUT, CH2: ON

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8 Detailed Description

8.1 Overview
The TPS22967 device is a single-channel, 4-A load switch in an 8-pin WSON package. To reduce the voltage
drop in high current rails, the device implements an ultra-low resistance N-channel MOSFET. The device has a
programmable slew rate for applications that require specific rise time.
The device has very low leakage current during off state. This prevents downstream circuits from pulling high
standby current from the supply. Integrated control logic, driver, power supply, and output discharge FET
eliminates the need for any external components, which reduces solution size and bill of materials (BOM) count.

8.2 Functional Block Diagram

VIN

Charge
VBIAS Pump

Control
ON
Logic

VOUT
CT

GND

8.3 Feature Description

This section describes the integrated features for the TPS22967.

8.3.1 ON/OFF Control

The ON pin controls the state of the switch. Asserting ON high enables the switch. ON is active high and has a
low threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard
GPIO logic thresholds. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot
be left floating and must be driven either high or low for proper functionality.

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Feature Description (continued)

8.3.2 Adjustable Rise Time
A capacitor to GND on the CT pin sets the VOUT slew rate. The voltage on the CT pin can be as high as 12 V.
Therefore, the minimum voltage rating for the CT capacitor must be 25 V for optimal performance. An
approximate formula for the relationship between CT and slew rate is (Equation 1 accounts for 10% to 90%
measurement on VOUT and does NOT apply for CT = 0 pF. Use Table 1 to determine rise times for when CT = 0
pF):
SR = 0.39 ´ CT + 13.4
where
• SR = slew rate (in µs/V).
• CT = the capacitance value on the CT pin (in pF).
• The units for the constant 13.4 is in µs/V. The units for the constant 0.39 are in µs/(V × pF). (1)
Rise time can be calculated by multiplying the input voltage by the slew rate. Table 1 contains rise time values
measured on a typical device. Rise times shown below are only valid for the power-up sequence where VIN and
VBIAS are already in steady state condition, and the ON pin is asserted high.

Table 1. Rise Times On a Typical Device

RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω
CTx (pF) TYPICAL VALUES at 25°C, 25 V X7R 10% CERAMIC CAPACITOR
5V 3.3 V 1.8 V 1.5 V 1.2 V 1.05 V 0.8 V
0 127 93 62 55 51 46 42
220 475 314 188 162 141 125 103
470 939 637 359 304 255 218 188
1000 1869 1229 684 567 476 414 344
2200 4020 2614 1469 1211 1024 876 681
4700 8690 5746 3167 2703 2139 1877 1568
10000 18360 12550 6849 5836 4782 4089 3449

8.3.3 Quick Output Discharge

The TPS22967 includes a Quick Output Discharge (QOD) feature. When the switch is disabled, a discharge
resistor is connected between VOUT and GND. This resistor has a typical value of 225 Ω and prevents the
output from floating while the switch is disabled.

8.4 Device Functional Modes

Table 2 describes the functional state of the load switch as determined by the ON pin.

Table 2. Functional Table

ON VIN to VOUT VOUT to GND
L Off On
H On Off

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

This section describes design considerations for the TPS22967 which can vary depending on the specific
application.

9.1.1 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a
discharged load capacitor or short circuit, a capacitor must be placed between VIN and GND. A 1-µF ceramic
capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce
the voltage drop during high-current applications. When switching heavy loads, TI recommends having an input
capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.

9.1.2 Output Capacitor (Optional)

Because of the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current
flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN
dip caused by inrush currents during start-up; however, a 10-to-1 ratio for capacitance is not required for proper
functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VIN dip upon
turnon due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise
time (see below).

9.1.3 VIN and VBIAS Voltage Range

For optimal RON performance, make sure VIN ≤ VBIAS. The device will still be functional if VIN > VBIAS but it will
exhibit RON greater than what is listed in the Electrical Characteristics: VBIAS = 5 V table. See Figure 31 for an
example of a typical device. Notice the increasing RON as VIN exceeds VBIAS voltage. Never exceed the maximum
voltage rating for VIN and VBIAS.
50
VBIAS = 2.5V
VBIAS = 3.3V
45
VBIAS = 3.6V
VBIAS = 4.2V

40 VBIAS = 5V
RON (m )

VBIAS = 5.5V

35 Temperature=25C,
IOUT=-200mA

30

25

20
0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6
VIN (V)
C017

Figure 31. RON vs VIN (VIN > VBIAS)

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Application Information (continued)

9.1.4 Safe Operating Area (SOA)
The SOA curves show the continuous current carrying capability of the device versus ambient temperature (TA)
to ensure reliable operation over 70,000 hours of device lifetime. The different curves represent the percentage
On time over device lifetime and can be used as a reference to understand the current carrying capability of
TPS22967 under different use cases. TI recommends maintaining continuous current at or below the SOA
curves shown in Figure 32.
5

4
Continuous Current (A)

100% On time
1 90% On time
70% On time
50% On time VBIAS=5.0V
30% On time
0
-40 -15 10 35 60 85
Ambient Temperature (ºC)
C002

On time is the duration of time that the device is enabled (ON ≥ VIH) over 70,000 hour lifetime.

Figure 32. Safe Operating Area

9.2 Typical Application

Power VIN VOUT

Supply
ON
CIN ON CL
CT RL
OFF

GND
VBIAS GND
TPS22967

Figure 33. Typical Application Schematic

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Typical Application (continued)

9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN 3.3 V
VBIAS 5V
CL 22 μF
Maximum Acceptable Inrush Current 400 mA

9.2.2 Detailed Design Procedure

9.2.2.1 Inrush Current

When the switch is enabled, the output capacitors must be charged up from 0 V to the set value (3.3 V in this
example). This charge arrives in the form of inrush current. Inrush current can be calculated using Equation 2:
Inrush Current = C × dV/dt
where
• C = output capacitance.
• dV = output voltage.
• dt = rise time. (2)
The TPS22967 offers adjustable rise time for VOUT. This feature lets the user control the inrush current during
turnon. The appropriate rise time can be calculated using the design requirements and the inrush current
equation.
400 mA = 22 μ F × 3.3 V/dt (3)
dt = 181.5 μs (4)
To ensure an inrush current of less than 400 mA, choose a CT value that will yield a rise time of more than 181.5
μs. See Application Curves for an example of how the CT capacitor can be used to reduce inrush current.

9.2.3 Application Curves

VBIAS = 5 V VIN = 3.3 V CL = 22 μF VBIAS = 5 V VIN = 3.3 V CL = 22 μF

Figure 34. Inrush Current With CT = 0 pF Figure 35. Inrush Current with CT = 220 pF

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 TPS22967
www.ti.com SLVSC42A – AUGUST 2013 – REVISED APRIL 2015

10 Power Supply Recommendations

The device is designed to operate from a VBIAS range of 2.5 V to 5.5 V and a VIN range of 0.8 V to 5.5 V. The
power supply must be well regulated and placed as close to the device terminals as possible. It must be able to
withstand all transient and load current steps. In most situations, using an input capacitance of 1 μF is sufficient
to prevent the supply voltage from dipping when the switch is turned on. In cases where the power supply is slow
to respond to a large transient current or large load current step, additional bulk capacitance may be required on
the input.
The requirements for larger input capacitance can be mitigated by adding additional capacitance to the CT pin.
This additional capacitance causes the load switch to turn on more slowly. Not only will this reduce transient
inrush current, but it will also give the power supply more time to respond to the load current step.

11 Layout

11.1 Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects
along with minimizing the case to ambient thermal impedance.
The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To
calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use
Equation 5 as a guideline:
TJ(max) - TA
PD(max) =
θJA
where
• PD(max) = maximum allowable power dissipation.
• TJ(max) = maximum allowable junction temperature (125°C for the TPS22967).
• TA = ambient temperature of the device.
• ΘJA = junction to air thermal impedance. See Thermal Information. This parameter is highly dependent upon
board layout. (5)
Figure 36 shows an example of a layout. Notice the thermal vias under the exposed thermal pad of the device.
This allows for thermal diffusion away from the device.

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TPS22967
SLVSC42A – AUGUST 2013 – REVISED APRIL 2015 www.ti.com

11.2 Layout Example

Figure 36. Layout Example

12 Device and Documentation Support

12.1 Trademarks
Ultrabooks is a trademark of Intel.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS22967DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTU

TPS22967DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ZTU

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS22967DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS22967DSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS22967DSGR WSON DSG 8 3000 210.0 185.0 35.0
TPS22967DSGT WSON DSG 8 250 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DSG 8 WSON - 0.8 mm max height
2 x 2, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224783/A

www.ti.com
 PACKAGE OUTLINE
DSG0008A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2.1 B
A
1.9

PIN 1 INDEX AREA

2.1
1.9

0.32
0.18

0.4
0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8 MAX C

SEATING PLANE
0.05
0.08 C
0.00

EXPOSED
THERMAL PAD 0.9 0.1 (0.2) TYP

4 5

6X 0.5

2X
9
1.5 1.6 0.1

8
1
0.32
8X
PIN 1 ID 0.4 0.18
8X
0.2 0.1 C A B
0.05 C

4218900/D 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DSG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.9) ( 0.2) VIA

8X (0.5)
TYP
1
8

8X (0.25)
(0.55)
SYMM 9
(1.6)

6X (0.5)
5
4

(R0.05) TYP SYMM

(1.9)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218900/D 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DSG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5) SYMM METAL

1
8

8X (0.25)
(0.45)
SYMM
9

6X (0.5) (0.7)

5
4

(R0.05) TYP (0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4218900/D 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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