IC sn74lvc1g3157

SN74LVC1G3157
SCES424M – JANUARY 2003 – REVISED AUGUST 2022
SN74LVC1G3157 Single-Pole Double-Throw Analog Switch
1 Features 3 Description
• ESD protection exceeds JESD 22 This single channel single-pole double-throw (SPDT)
– 2000-V Human Body Model (A114-A) analog switch is designed for 1.65-V to 5.5-V VCC
– 1000-V Charged-Device Model (C101) operation.
• 1.65-V to 5.5-V VCC operation The SN74LVC1G3157 device can handle both analog
• Qualified for 125°C operation and digital signals. The SN74LVC1G3157 device
• Specified break-before-make switching permits signals with amplitudes of up to VCC (peak)
• Rail-to-rail signal handling to be transmitted in either direction.
• Operating frequency typically 340 MHz at room
temperature Applications include signal gating, chopping,
• High speed, typically 0.5 ns modulation or demodulation (modem), and signal
(VCC = 3 V, CL = 50 pF) multiplexing for analog-to-digital and digital-to-analog
• Low ON-state resistance, typically ≉6 Ω conversion systems.
(VCC = 4.5 V) Device Information(1)
• Latch-up performance exceeds 100 mA Per JESD
PART NUMBER PACKAGE BODY SIZE (NOM)
78, class II
SOT-23 (DBV) (6) 2.90 mm × 1.60 mm
2 Applications SC70 (DCK) (6) 2.00 mm × 1.25 mm
• Wearables and mobile devices SOT (DRL) (6) 1.60 mm × 1.20 mm
• Portable computing SN74LVC1G3157 SON (DRY) (6) 1.45 mm × 1.00 mm
• Internet of things (IoT) DSBGA (YZP) (6) 1.41 mm × 0.91 mm
• Audio signal routing SON (DSF) (6) 1.00 mm × 1.00 mm
• Remote radio unit
X2SON (DTB) (6) 0.80 mm × 1.00 mm
• Portable medical equipment
• Surveillance (1) For all available packages, see the orderable addendum at
• Home automation the end of the data sheet.
• I2C/SPI/UART bus multiplexing
• Wireless charging
1
B2
6 4
S A
3
B1
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G3157
SCES424M – JANUARY 2003 – REVISED AUGUST 2022 www.ti.com
Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................16
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................16
3 Description.......................................................................1 9 Application and Implementation.................................. 17
4 Revision History.............................................................. 2 9.1 Application Information............................................. 17
5 Pin Configuration and Functions...................................4 9.2 Typical Application.................................................... 17
6 Specifications.................................................................. 6 10 Power Supply Recommendations..............................19
6.1 Absolute Maximum Ratings........................................ 6 11 Layout........................................................................... 19
6.2 ESD Ratings............................................................... 6 11.1 Layout Guidelines................................................... 19
6.3 Recommended Operating Conditions.........................7 11.2 Layout Example...................................................... 19
6.4 Thermal Information....................................................7 12 Device and Documentation Support..........................20
6.5 Electrical Characteristics.............................................8 12.1 Documentation Support.......................................... 20
6.6 Analog Switch Characteristics.................................... 9 12.2 Receiving Notification of Documentation Updates..20
6.7 Switching Characteristics 85°C.................................10 12.3 Support Resources................................................. 20
6.8 Switching Characteristics 125°C...............................10 12.4 Trademarks............................................................. 20
6.9 Typical Characteristics.............................................. 10 12.5 Electrostatic Discharge Caution..............................20
7 Parameter Measurement Information.......................... 11 12.6 Glossary..................................................................20
8 Detailed Description......................................................16 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 16 Information.................................................................... 20
8.2 Functional Block Diagram......................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (May 2017) to Revision M (August 2022) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Pin Configuration and Functions section........................................................................................4
• Updated the equation in the Detailed Design Procedure section..................................................................... 18
Changes from Revision K (January 2017) to Revision L (May 2017) Page

• Deleted Feature "Useful for Both Analog and Digital Applications" ................................................................... 1
• Deleted Feature "High Degree of Linearity" .......................................................................................................1
• Changed the first sentence of the Description From: "This single-pole double-throw (SPDT)..." To: "This single
channel single pole double-throw (SPDT)..." ..................................................................................................... 1
• Added the X2SON (DTB) package to the Device Information ........................................................................... 1
• Added the X2SON (DTB) Package, to the Pin Configuration and Functions .................................................... 4
• Changed II/O To: II/OK for I/O port diode current in the Absolute Maximum Ratings ...........................................6
• Added the DTB (X2SON) package to the Thermal Information table................................................................. 7
• Changed Note 1 and Note 2 n the Analog Switch Characteristics table.............................................................9
• Deleted Note 3 "Specified by design" from the Analog Switch Characteristics tables........................................9
• Deleted Note 4 "Specified by design" from the Switch Characteristics 85°C tables.........................................10
• Deleted Note 4 "Specified by design" from the Switch Characteristics 125°C tables.......................................10
• Changed Figure 7-2, From: SW1 = VIL to SW1 = VIH, From: SW2 = VIH to: SW2 = VIL .................................. 11
• Changed Figure 7-5 ......................................................................................................................................... 11
• Added a series 50-Ω resistor on B1 in Figure 7-6 ............................................................................................11
• Changed Figure 7-7 ......................................................................................................................................... 11
Changes from Revision J (June 2016) to Revision K (January 2017) Page

• Added new applications to Applications section ................................................................................................ 1
• Added Operating free-air temperature, TA for BGA and all other packages in Recommended Operating
Conditions ..........................................................................................................................................................7
• Added 125°C data to Electrical Characteristics table. ....................................................................................... 8
• Added 85°C to title to differentiate from new 125°C Switching Characteristics section. ..................................10
2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G3157

SN74LVC1G3157
www.ti.com SCES424M – JANUARY 2003 – REVISED AUGUST 2022
• Added 125°C Switching Characteristics section and data. ..............................................................................10
Changes from Revision I (June 2015) to Revision J (June 2016) Page

• Deleted 200-V Machine Model (A115-A) from Features ....................................................................................1
• Changed Feature From: "Operating Frequency Typically 300 MHz at Room Temperature" To: "Operating
Frequency Typically 340 MHz at Room Temperature"........................................................................................1
• Updated Device Information table...................................................................................................................... 1
• Updated pinout images for all Packages............................................................................................................ 4
• Added temperature ranges for Storage temperature, Tstg and Junction temperature, TJ in Absolute Maximum
Ratings ...............................................................................................................................................................6
• Changed MAX value ±1 to ±0.1 for Ioff and IIN in Electrical Characteristics table............................................... 8
• Added Receiving Notification of Documentation Updates section....................................................................20
Changes from Revision H (May 2012) to Revision I (June 2015) Page

• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................1
• Updated Features............................................................................................................................................... 1
Changes from Revision G (September 2011) to Revision H (May 2012) Page

• Changed YZP with correct pin labels. ................................................................................................................4
• Added Thermal Information table....................................................................................................................... 7
• Changed to correct Pin Label "S"....................................................................................................................... 8
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

SN74LVC1G3157
5 Pin Configuration and Functions
B2 1 6 S B2 1 6 S
GND 2 5 VCC GND 2 5 VCC
B1 3 4 A B1 3 4 A
Not to scale Not to scale
Figure 5-1. DBV Package, 6-Pin SOT-23 (Top View) Figure 5-2. DCK Package, 6-Pin SC70 (Top View)
B2 1 6 S
B2 1 6 S
GND 2 5 VCC
GND 2 5 VCC
B1 3 4 A
B1 3 4 A
Not to scale
Not to scale Figure 5-4. DRL Package, 6-Pin SOT (Top View)
Figure 5-3. DRY Package, 6-Pin SON (Top View)
1 6
B2 S
B2 1 6 S
GND 2 5 VCC GND 2 5 VCC

B1 3 4 A
B1 A
3 4
Not to scale Figure 5-6. DTB Package, 6-Pin X2SON (Top View)
Figure 5-5. DSF Package, 6-Pin SON (Top View)
Table 5-1. Pin Functions

PIN
SOT-23, SC70, SON, TYPE(1) DESCRIPTION
NAME
X2SON, or SOT
B2 1 I/O Switch I/O. Set S high to enable.
GND 2 P Ground
B1 3 I/O Switch I/O. Set S low to enable.
A 4 I/O Common terminal
VCC 5 P Power supply
S 6 I Select
(1) I = input, O = output, P = power

SN74LVC1G3157
1 2
C B1 A
B GND V
CC
A B2 S
Not to scale
Figure 5-7. YZP Package, 6-Pin DSBGA (Bottom View)
Legend
Input Input or Output
Power
Table 5-2. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
A1 B2 I/O Switch I/O. Set S high to enable.
A2 S I Select
B1 GND P Ground
B2 VCC P Power supply
C1 B1 I/O Switch I/O. Set S low to enable.
C2 A I/O Common terminal
(1) I = input, O = output, P = power

SN74LVC1G3157
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(2) –0.5 6.5 V
VIN Control input voltage(2) (3) –0.5 6.5 V
VI/O Switch I/O voltage(2) (3) (4) (5) –0.5 VCC + 0.5 V
IIK Control input clamp current VIN < 0 –50 mA
II/OK I/O port diode current VI/O < 0 or VI/O > VCC ±50 mA
II/O On-state switch current(6) VI/O = 0 to VCC ±128 mA
Continuous current through VCC or GND ±100 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground unless otherwise specified.
(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
(5) VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
(6) II, IO, IA, and IBn are used to denote specific conditions for II/O.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

SN74LVC1G3157
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VI/O Switch input or output voltage 0 VCC V
VIN Control input voltage 0 5.5 V
VCC = 1.65 V to 1.95 V VCC × 0.75
VIH High-level input voltage, control input V
VCC = 2.3 V to 5.5 V VCC × 0.7
VCC = 1.65 V to 1.95 V VCC × 0.25
VIL Low-level input voltage, control input V
VCC = 2.3 V to 5.5 V VCC × 0.3
VCC = 1.65 V to 1.95 V 20
VCC = 2.3 V to 2.7 V 20
Δt/Δv Input transition rise or fall rate ns/V
VCC = 3 V to 3.6 V 10
VC C = 4.5 V to 5.5 V 10
BGA package (YZP) –40 85 °C
TA Operating free-air temperature All other packages (DBV, DCK,
–40 125 °C
DRL, DRY, DSF)
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information

SN74LVC1G3157
DTB YZP
THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) DRL (SOT) DRY (SON) UNIT
(X2SON) (DSBGA)
6 PINS 6 PINS 6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 234.9 269.5 244.1 284.2 324.5 129.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 150.4 189.5 112.5 138.6 150.5 1.9 °C/W
RθJB Junction-to-board thermal resistance 86.4 84.7 109.9 170.9 239.0 40.0 °C/W
Junction-to-top characterization
ψJT 60.8 62.7 9.3 13.7 17.2 0.6 °C/W
parameter
Junction-to-board characterization
ψJB 86.1 84.0 109.3 167.9 238.3 40.2 °C/W
parameter
Junction-to-case (bottom) thermal
RθJC(bot) n/a n/a n/a n/a n/a n/a °C/W
resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

SN74LVC1G3157
6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = -40 to 85°C TA = -40 to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP(1) MAX MIN TYP(1) MAX
VI = 0 V IO = 4 mA 11 20 11 20
1.65 V
VI = 1.65 V IO = –4 mA 15 50 15 50
VI = 0 V IO = 8 mA 8 12 8 12
2.3 V
VI = 2.3 V IO = –8 mA 11 30 11 30
See Figure 6-1
ron ON-state switch resistance(2) VI = 0 V IO = 24 mA 7 9 7 9 Ω
and Figure 7-1 3V
VI = 3 V IO = –24 mA 9 20 9 20
VI = 0 V IO = 30 mA 6 7 6 7
VI = 2.4 V IO = –30 mA 4.5 V 7 12 7 12
VI = 4.5 V IO = –30 mA 7 15 7 15
IA = –4 mA 1.65 V 140 140
ON-state switch resistance over 0 ≤ VBn ≤ VCC IA = –8 mA 2.3 V 45 45

rrange Ω
signal range(2) (3) (see Figure 6-1 and Figure 7-1) IA = –24 mA 3V 18 18
IA = –30 mA 4.5 V 10 10
VBn = 1.15 V IA = –4 mA 1.65 V 0.5 0.5
Difference of ON-state VBn = 1.6 V IA = –8 mA 2.3 V 0.1 0.3

Δron See Figure 7-1 Ω
resistance between switches(2) (4) (5) VBn = 2.1 V IA = –24 mA 3V 0.1 0.3
VBn = 3.15 V IA = –30 mA 4.5 V 0.1 0.2
IA = –4 mA 1.65 V 110 110
IA = –8 mA 2.3 V 26 40
ron(flat) ON resistance flatness(2) (4) (6) 0 ≤ VBn ≤ VCC Ω
IA = –24 mA 3V 9 10
IA = –30 mA 4.5 V 4 5
0 ≤ VI, VO ≤ VCC 1.65 V to ±1 ±1

Ioff (7) OFF-state switch leakage current µA
(see Figure 7-2 ) 5.5 V ±0.05 ±0.1(1) ±0.05 ±0.1
VI = VCC or GND, VO = Open ±1 ±1

IS(on) ON-state switch leakage current 5.5 V µA
(see Figure 7-3) ±0.1(1) ±0.1(1)
0 V to 5.5 ±1 ±1
IIN Control input current 0 ≤ VIN ≤ VCC µA
V ±0.05 ±0.1(1) ±0.05 ±0.1
ICC Supply current S = VCC or GND 5.5 V 1 10 35 µA
ΔICC Supply-current change S = VCC – 0.6 V 5.5 V 500 500 µA
Ci Control input capacitance S 5V 2.7 2.7 pF
Switch input/output
Cio(off) Bn 5V 5.2 5.2 pF
capacitance
Switch input/output Bn 17.3 17.3

Cio(on) 5V pF
capacitance A 17.3 17.3
(1) TA = 25°C
(2) Measured by the voltage drop between I/O pins at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages on the two (A or B) ports.
(3) Specified by design
(4) Δron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels
(5) This parameter is characterized, but not production tested.
(6) Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of
conditions.
(7) Ioff is the same as IS(off) (off-state switch leakage current).

SN74LVC1G3157
6.6 Analog Switch Characteristics

TA = 25°C
FROM TO
PARAMETER TEST CONDITIONS VCC TYP UNIT
(INPUT) (OUTPUT)
1.65 V 340
Frequency response(1) RL = 50 Ω, fin = sine wave 2.3 V 340

A or Bn Bn or A MHz
(switch on) (see Figure 7-5) 3V 340
4.5 V 340
1.65 V –54
Crosstalk(2) RL = 50 Ω, fin = 10 MHz (sine wave) 2.3 V –54

B1 or B2 B2 or B1 dB
(between switches) (see Figure 7-6) 3V –54
4.5 V –54
1.65 V –57
Feed through CL = 5 pF, RL = 50 Ω, 2.3 V –57
attenuation(2) A or Bn Bn or A fin = 10 MHz (sine wave) dB
(switch off) (see Figure 7-7) 3V –57
4.5 V –57
CL = 0.1 nF, RL = 1 MΩ 3.3 V 3

Charge injection S A pC
(see Figure 7-8) 5V 7
1.65 V 0.1%
VI = 0.5 Vp-p, RL = 600 Ω, 2.3 V 0.025%
Total harmonic distortion A or Bn Bn or A fin = 600 Hz to 20 kHz (sine wave)
(see Figure 7-9) 3V 0.015%
4.5 V 0.01%
(1) Set fin to 0 dBm and provide a bias of 0.4 V. Increase fin frequency until the gain is 3 dB below the insertion loss.
(2) Set fin to 0 dBm and provide a bias of 0.4 V.

SN74LVC1G3157
6.7 Switching Characteristics 85°C

TA = –40 to +85°C (see Figure 7-4 and )Figure 7-10
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd (1) A or Bn Bn or A 2 1.2 0.8 0.3 ns
ten (2) 7 24 3.5 14 2.5 7.6 1.7 5.7
S Bn ns
tdis (3) 3 13 2 7.5 1.5 5.3 0.8 3.8
tB-M 0.5 0.5 0.5 0.5 ns
(1) tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical ON-state resistance of the switch
and the specified load capacitance when driven by an ideal voltage source (zero output impedance).
(2) ten is the slower of tPZL or tPZH.
(3) tdis is the slower of tPLZ or tPHZ.
6.8 Switching Characteristics 125°C

TA = –40 to +125°C (see Figure 7-4 and Figure 7-10)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd (1) A or Bn Bn or A 2 1.2 0.8 0.5 ns
ten (2) 1 24.5 1 14.5 2.5 8 1.7 6
S Bn ns
tdis (3) 2.5 13.5 2 8 1.5 5.5 0.8 4
tB-M 0.5 0.5 0.5 0.5 ns
6.9 Typical Characteristics

120
VCC = 1.65 V
100
80
ron
60
40
VCC = 2.3 V
20 VCC = 3 V
VCC = 4.5 V
0
0 1 2 3 4 5
VI - V
Figure 6-1. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC

SN74LVC1G3157
7 Parameter Measurement Information
VI – V O
ron = Ω
IO
Figure 7-1. ON-State Resistance Test Circuit

VCC
SW S
1 VIH
VCC
2 VIL
S
VIL or VIH
B1 1
SW
VO
B2
2
A
VI A
GND
Condition 1: VI = GND, VO = VCC

Condition 2: VI = VCC, VO = GND
Figure 7-2. OFF-State Switch Leakage-Current Test Circuit
VCC SW S
1 VIL
VCC 2 VIH
S
VIL or VIH
B1 1
SW
VO
VO = Open
B2 2
A
VI A
GND
VI = VCC or GND
Figure 7-3. ON-State Switch Leakage-Current Test Circuit

SN74LVC1G3157
VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND
LOAD CIRCUIT
INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V
3.3 V ± 0.3 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V
VI
Timing Input VM
0V
tW
VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES
VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-4. Load Circuit and Voltage Waveforms

SN74LVC1G3157
VCC
SW S
1 VIL
VCC
2 VIH
S
VIL or VIH
B1 1
SW
VO
B2
2
50 A RL = 50
fin GND
Figure 7-5. Frequency Response (Switch On)

VCC
S TEST CONDITION
VCC
B1 50 VB1 VIL 20log10(VO2/VI)

S
VIL or VIH VIH 20log10(VO1/VI)
fin
VB2
Analyzer
B2 2
RL = 50
GND
Figure 7-6. Crosstalk (Between Switches)
VCC
SW S
1 VIL
VCC
2 VIH
S
VIL or VIH
B1 1
SW
Analyzer
B2
2
50 A RL = 50
fin GND
Figure 7-7. Feed Through

SN74LVC1G3157
VCC
VCC
S
B1 1
LOGIC RGEN
SW
INPUT
B2 2 VGE
VOUT A
GND
RL CL RL/CL = 1 MΩ/100 pF
LOGIC
OFF ON OFF
INPUT
∆VOUT
VOUT
Q = (∆VOUT) (CL)
Figure 7-8. Charge-Injection Test
10 kΩ
600 Ω
Figure 7-9. Total Harmonic Distortion

SN74LVC1G3157
VCC
VCC
S
B1
VI = VCC/2
B2
VO A
GND
VS
RL CL RL/CL = 50 Ω/35 pF
VO
0.9 x VO
tD
Figure 7-10. Break-Before-Make Internal Timing

SN74LVC1G3157
8 Detailed Description
8.1 Overview
The SN74LVC1G3157 device is a single-pole double-throw (SPDT) analog switch designed for 1.65-V to 5.5-V
VCC operation. The SN74LVC1G3157 device can handle analog and digital signals. The device permits signals
with amplitudes of up to VCC (peak) to be transmitted in either direction.
8.2 Functional Block Diagram
1
B2
6 4
S A
3
B1
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description

The 1.65-V to 5.5-V supply operation allows the device to function in many different systems comprised of
different logic levels, allowing rail-to-rail signal switching. Either the B1 channel or the B2 channel is activated
depending upon the control input. If the control input is low, B1 channel is selected. If the control input is high, B2
channel is selected.
8.4 Device Functional Modes
Table 8-1 lists the ON channel when one of the control inputs is selected.
Table 8-1. Function Table
CONTROL ON
INPUTS CHANNEL
L B1
H B2

SN74LVC1G3157
9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information

The SN74LVC1G3157 SPDT analog switch is flexible enough for use in a variety of circuits such as
analog audio routing, power-up monitor, memory sharing, and so on. For details on the applications, see
SN74LVC1G3157 and SN74LVC2G53 SPDT Analog Switches.
9.2 Typical Application
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements

The inputs can be analog or digital, but TI recommends waiting until VCC has ramped to a level in Section 6.3
before applying any signals. Appropriate termination resistors should be used depending on the type of signal
and specification. The Select pin should not be left floating; either pull up or pull down with a resistor that can be
overdriven by a GPIO.

SN74LVC1G3157
9.2.2 Detailed Design Procedure

Using this circuit idea, a system designer can ensure a component or subsystem power has ramped up before
allowing signals to be applied to its input. This is useful for integrated circuits that do not have overvoltage
tolerant inputs. The basic idea uses a resistor divider on the VCC1 power rail, which is ramping up. The RC
time constant of the resistor divider further delays the voltage ramp on the select pin of the SPDT bus switch.
By carefully selecting values for R1, R2, and C, it is possible to ensure that VCC1 will reach its nominal value
before the path from A to B2 is established, thus preventing a signal being present on an I/O before the device/
system is powered up. To ensure the minimum desired delay is achieved, the designer should use Equation 1 to
calculate the time required from a transition from ground (0 V) to half the supply voltage (VCC1/2).
 R2 
Set   VCC1  VIH of the select pin
 R1 + R2  (1)
Choose Rs and C to achieve the desired delay.

When VS goes high, the signal will be passed.
9.2.3 Application Curve
Figure 9-2. VS Voltage Ramp

SN74LVC1G3157
10 Power Supply Recommendations

Most systems have a common 3.3-V or 5-V rail that can supply the VCC pin of this device. If this is not available,
a Switch-Mode-Power-Supply (SMPS) or a Linear Dropout Regulator (LDO) can be used to provide supply to
this device from another voltage rail.
11 Layout
11.1 Layout Guidelines
TI recommends keeping signal lines as short as possible. TI also recommends incorporating microstrip or
stripline techniques when signal lines are greater than 1 inch in length. These traces must be designed with a
characteristic impedance of either 50 Ω or 75 Ω, as required by the application. Do not place this device too
close to high-voltage switching components, as they may interfere with the device.
11.2 Layout Example
Figure 11-1. Recommended Layout Example

SN74LVC1G3157
12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs
• Texas Instruments, SN74LVC1G3157 and SN74LVC2G53 SPDT Analog Switches
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 12-Jan-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
74LVC1G3157DBVRE4 LIFEBUY SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5F, CC5R)
74LVC1G3157DBVRG4 LIFEBUY SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (CC5F, CC5R)
74LVC1G3157DCKRE4 LIFEBUY SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C55, C5F, C5J, C5
R)
74LVC1G3157DCKRG4 LIFEBUY SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C55, C5F, C5J, C5
R)
74LVC1G3157DRYRG4 LIFEBUY SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C5
SN74LVC1G3157DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CC55, CC5F, CC5K, Samples
CC5R)
CC5S
SN74LVC1G3157DCK3 LIFEBUY SC70 DCK 6 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 C5Z
Non-Green
SN74LVC1G3157DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C55, C5F, C5J, C5 Samples
R)
SN74LVC1G3157DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (C57, C5R) Samples
SN74LVC1G3157DRY2 LIFEBUY SON DRY 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 C5
SN74LVC1G3157DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C5 Samples
SN74LVC1G3157DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 C5 Samples
SN74LVC1G3157DTBR ACTIVE X2SON DTB 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7X Samples
SN74LVC1G3157YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C5N Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 12-Jan-2024
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G3157 :
• Automotive : SN74LVC1G3157-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Oct-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
74LVC1G3157DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G3157DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G3157DRLR SOT-5X3 DRL 6 4000 180.0 8.4 2.0 1.8 0.75 4.0 8.0 Q3
SN74LVC1G3157DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3
SN74LVC1G3157DRY2 SON DRY 6 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3
SN74LVC1G3157DRYR SON DRY 6 5000 180.0 9.5 1.2 1.65 0.7 4.0 8.0 Q1
SN74LVC1G3157DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G3157DSFR SON DSF 6 5000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G3157DTBR X2SON DTB 6 3000 180.0 9.5 0.94 1.13 0.41 2.0 8.0 Q2
SN74LVC1G3157YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Oct-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74LVC1G3157DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
SN74LVC1G3157DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G3157DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0
SN74LVC1G3157DRY2 SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G3157DRY2 SON DRY 6 5000 202.0 201.0 28.0
SN74LVC1G3157DRYR SON DRY 6 5000 189.0 185.0 36.0
SN74LVC1G3157DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G3157DSFR SON DSF 6 5000 210.0 185.0 35.0
SN74LVC1G3157DTBR X2SON DTB 6 3000 189.0 185.0 36.0
SN74LVC1G3157YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1
6
2X 0.95
3.05
2.75
1.9 5
2
4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45 MAX
0 -10
0.25
GAGE PLANE 0.22
TYP 0 -10
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
0 -10
-10 -10
ALTERNATIVE PACKAGE SINGULATION VIEW
4214840/D 09/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/D 09/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/D 09/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0006 SCALE 9.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
0.5 MAX C
SEATING PLANE
0.19 BALL TYP 0.05 C
0.15
0.5 TYP
SYMM
1 D: Max = 1.418 mm, Min =1.357 mm
B TYP
0.5 E: Max = 0.918 mm, Min =0.857 mm
TYP
A
0.25 1 2
6X SYMM
0.21
0.015 C A B
4219524/A 06/2014
NOTES: NanoFree Is a trademark of Texas Instruments.
per ASME Y14.5M.
TM
3. NanoFree package configuration.
www.ti.com
YZP0006 DSBGA - 0.5 mm max height
(0.5) TYP
6X ( 0.225)
1 2
(0.5) TYP
B SYMM
SYMM

SCALE:40X
( 0.225) 0.05 MAX 0.05 MIN METAL

METAL UNDER
MASK
SOLDER MASK ( 0.225)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4219524/A 06/2014
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
YZP0006 DSBGA - 0.5 mm max height
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
1 2
A
(0.5)
TYP
B SYMM
METAL
TYP
SYMM

SCALE:40X
4219524/A 06/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DRL0006A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1 A
ID AREA
1
6
4X 0.5
1.7
1.5
2X 1 NOTE 3
4
3
1.3 0.3 0.05

B 6X TYP
1.1 0.1 0.00
0.6 MAX
C
SEATING PLANE
0.18
6X 0.05 C
0.08 SYMM
SYMM
0.27
6X
0.15
0.1 C A B
0.4
6X 0.05
0.2
4223266/C 12/2021
NOTES:
per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
DRL0006A SOT - 0.6 mm max height
6X (0.67)
SYMM
1
6X (0.3) 6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)

SCALE:30X
0.05 MAX 0.05 MIN

AROUND AROUND
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
DEFINED DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
DRL0006A SOT - 0.6 mm max height
6X (0.67)
SYMM
1
6X (0.3) 6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)

SCALE:30X
4223266/C 12/2021
NOTES: (continued)
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A SCALE 8.500
USON - 0.6 mm max height
1.05 A
B
0.95
PIN 1 INDEX AREA

1.5
1.4
0.6 MAX C
SEATING PLANE
0.05
0.00 0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.4 0.15
0.3 0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL) 0.35
5X
0.25
4222894/A 01/2018
NOTES:
per ASME Y14.5M.
www.ti.com
DRY0006A USON - 0.6 mm max height
SYMM
(0.35)
5X (0.3)
1 6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)

1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
EXPOSED
EXPOSED
METAL
METAL

NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
DRY0006A USON - 0.6 mm max height
SYMM
(0.35) 5X (0.3)
1 6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP (0.6)

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DRY0006B SCALE 8.500
USON - 0.55 mm max height
1.05 A
B
0.95
PIN 1 INDEX AREA

1.5
1.4
0.55 MAX C
SEATING PLANE
0.05
0.00 0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.15
PIN 1 ID 0.1 C A B
(OPTIONAL)
0.05 C
0.35
6X
0.25
4222207/B 02/2016
NOTES:
per ASME Y14.5M.
www.ti.com
DRY0006B USON - 0.55 mm max height
SYMM
6X (0.3)
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)

1:1 RATIO WITH PKG SOLDER PADS
SCALE:40X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK
DEFINED SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222207/B 02/2016
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
DRY0006B USON - 0.55 mm max height
SYMM
6X (0.3)
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP (0.6)

BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222207/B 02/2016
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DSF0006A SCALE 10.000
X2SON - 0.4 mm max height
1.05
B A
0.95
PIN 1 INDEX AREA

1.05
0.95
0.4 MAX C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM 0.05
0.00
3
4
2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C B A
6X
0.35 0.05 C
4220597/B 06/2022
NOTES:
per ASME Y14.5M.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
DSF0006A X2SON - 0.4 mm max height
6X (0.6)
(R0.05) TYP
1
6X (0.17) 6
SYMM
4X (0.35)
4
3
SYMM
(0.8)

EXPOSED METAL SHOWN
SCALE:40X
0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL


DEFINED DEFINED
SOLDER MASK DETAILS
4220597/B 06/2022
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
DSF0006A X2SON - 0.4 mm max height
6X (0.6)
(R0.05) TYP
1
6X (0.15) 6
SYMM
4X (0.35)
4
3
SYMM
(0.8)

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:40X
4220597/B 06/2022
www.ti.com
PACKAGE OUTLINE
DTB0006A SCALE 12.000
X2SON - 0.35 mm max height
1.05 A
B
0.95
PIN 1 INDEX AREA 0.85

0.75
0.35 MAX
C
SEATING PLANE
(0.1) TYP
0.05 C
2X 0.6 (0.1)
(0.027) TYP 0.05
0.4 0.00
3 4
2X EQUILATERAL
TRIANGLES
+0.05 PKG
0.25 TYP
-0.03 2 5
(0.08)
0.25
4X
0.17
PIN 1 ID 1 6
PKG
(OPTIONAL) 0.30
4X
NOTE 5 0.22
0.1 C A B
0.05 C
4223406/C 02/2019
NOTES:
per ASME Y14.5M.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
www.ti.com
DTB0006A X2SON - 0.35 mm max height
0.05 MIN
SOLDER MASK OPEING
ALL AROUND
TYP
TYP
SYMM
4X (0.25)
6 (0.25)
1
TYP
4X (0.4)
SYMM
(0.8)
2 5
(0.2) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER 3
SOLDER MASK 4 (0.2)
TYP TYP
(0.027) TYP (R0.05) TYP

(0.4)
(0.6)

SOLDER MASK DEFINED
SCALE:50X
4223406/C 02/2019
NOTES: (continued)
6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
DTB0006A X2SON - 0.35 mm max height
4X (0.25)
SYMM
(0.03) TYP
6 (0.28)
1 TYP
4X (0.4)
SYMM
2 5 (0.80)
(0.20) TYP
SOLDER MASK
EDGE, 2X
METAL UNDER 3
SOLDER MASK 4 (0.20)
TYP TYP
(R0.05) TYP
(0.21)
(0.37)
4X (0.60)

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:50X
4223406/C 02/2019
NOTES: (continued)
www.ti.com
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SN74LVC1G3157

SCES424M – JANUARY 2003 – REVISED AUGUST 2022

SN74LVC1G3157 Single-Pole Double-Throw Analog Switch

Changes from Revision K (January 2017) to Revision L (May 2017) Page

Changes from Revision J (June 2016) to Revision K (January 2017) Page

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• Added 125°C Switching Characteristics section and data. ..............................................................................10

Changes from Revision I (June 2015) to Revision J (June 2016) Page

Changes from Revision H (May 2012) to Revision I (June 2015) Page

Changes from Revision G (September 2011) to Revision H (May 2012) Page

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

5 Pin Configuration and Functions

GND 2 5 VCC GND 2 5 VCC

Not to scale Not to scale

GND 2 5 VCC GND 2 5 VCC

Table 5-1. Pin Functions

(1) I = input, O = output, P = power

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Figure 5-7. YZP Package, 6-Pin DSBGA (Bottom View)

Table 5-2. Pin Functions

(1) I = input, O = output, P = power

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6.2 ESD Ratings

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6.3 Recommended Operating Conditions

6.4 Thermal Information

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6.5 Electrical Characteristics

ON-state switch resistance over 0 ≤ VBn ≤ VCC IA = –8 mA 2.3 V 45 45

Difference of ON-state VBn = 1.6 V IA = –8 mA 2.3 V 0.1 0.3

0 ≤ VI, VO ≤ VCC 1.65 V to ±1 ±1

VI = VCC or GND, VO = Open ±1 ±1

Switch input/output Bn 17.3 17.3

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6.6 Analog Switch Characteristics

Frequency response(1) RL = 50 Ω, fin = sine wave 2.3 V 340

Crosstalk(2) RL = 50 Ω, fin = 10 MHz (sine wave) 2.3 V –54

CL = 0.1 nF, RL = 1 MΩ 3.3 V 3

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6.7 Switching Characteristics 85°C

6.8 Switching Characteristics 125°C

6.9 Typical Characteristics

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7 Parameter Measurement Information

Figure 7-1. ON-State Resistance Test Circuit

Condition 1: VI = GND, VO = VCC

Figure 7-2. OFF-State Switch Leakage-Current Test Circuit

Figure 7-3. ON-State Switch Leakage-Current Test Circuit

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NOTES: A. CL includes probe and jig capacitance.

Figure 7-4. Load Circuit and Voltage Waveforms

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Figure 7-5. Frequency Response (Switch On)

B1 50 VB1 VIL 20log10(VO2/VI)