P82B715 I C Bus Extender: 2 1 Features 2 Applications
P82B715 I C Bus Extender: 2 1 Features 2 Applications
P82B715 I C Bus Extender: 2 1 Features 2 Applications
P82B715
SCPS145B – DECEMBER 2007 – REVISED FEBRUARY 2016
P82B715
GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
P82B715
SCPS145B – DECEMBER 2007 – REVISED FEBRUARY 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 7
2 Applications ........................................................... 1 8.3 Feature Description................................................... 7
3 Description ............................................................. 1 8.4 Device Functional Modes.......................................... 8
4 Revision History..................................................... 2 9 Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application .................................................... 9
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 13
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 13
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 13
6.4 Thermal Information .................................................. 4 11.2 Layout Example .................................................... 13
6.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 14
6.6 Switching Characteristics .......................................... 5 12.1 Community Resource............................................ 14
6.7 Typical Characteristics .............................................. 6 12.2 Trademarks ........................................................... 14
7 Parameter Measurement Information .................. 6 12.3 Electrostatic Discharge Caution ............................ 14
12.4 Glossary ................................................................ 14
8 Detailed Description .............................................. 7
8.1 Overview ................................................................... 7 13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
P Package
8-Pin PDIP D Package
Top View 8-Pin SOIC
Top View
NC 1 8 VCC NC 1 8 VCC
Lx 2 7 Ly Lx 2 7 Ly
Sx 3 6 Sy
Sx 3 6 Sy 4 5
GND NC
GND 4 5 NC
NC – No internal connection
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 NC — No connection
2 Lx I/O Buffered serial data bus or LDA
3 Sx I/O Serial data bus or SDA. Connect to VCC of I2C master through a pullup resistor.
4 GND — Ground
5 NC — No connection
6 Sy I/O Serial clock bus or SCL. Connect to VCC of I2C master through a pullup resistor.
7 Ly I/O Buffered serial clock bus or LCL
8 VCC I Supply voltage
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.3 12 V
2
I C bus voltage Sx or Sy 0 VCC
Vb V
Buffered bus voltage Lx or Ly 0 VCC
Sx or Sy 60
IO Continuous output current mA
Lx or Ly 60
ICC Continuous current through VCC or GND 60 mA
Tstg Storage temperature –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) Operation with reduced performance is possible down to 3 V. Typical static sinking performance is not degraded at 3 V, but the dynamic
sink currents while the output is being driven through VCC/2 are reduced and can increase fall times. Timing-critical designs should
accommodate the specified minimums.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) Buffer is passive in this test. The Sx/Sy sink current flows through an internal resistor to the driver connected at the Lx/Ly I/O.
(1) A conventional input-output delay is not observed in the Sx/Lx voltage waveforms, because the input and output pins are internally tied
with a 30-Ω resistor so they show equal logic voltage levels to within 100 mV. When connected in an I2C system, an Sx/Sy input pin
cannot rise/fall until the buffered bus load at the output pin has been driven by the internal amplifier. This test measures the bus
propagation delay caused to falling or rising voltages at the Lx/Ly output (as well as the Sx/Sy input) by the amplifier’s response time.
The figure given is measured with a drive current as shown in Figure 2. Because this is a dynamic bus test in which a corresponding
bus driving IC has an output voltage well above 0.4 V, 6 mA is used instead of the static 3 mA.
(2) The signal path Lx to Sx and Ly to Sy is passive through the internal 30-Ω resistor. There is no amplifier involved and essentially no
signal propagation delay.
0.15
VOL (V)
0.1
0.05
0
0 5 10 15 20 25 30
ILX (mA) D001
Sx Lx Lx Sx 5V
P82B715 P82B715
Input Output Input and
Output
Voltage 0V
I = 6 mA td td
8 Detailed Description
8.1 Overview
The I2C bus capacitance limit of 400 pF restricts practical communication distances to a few meters. One of the
advantages of the P82B715 is that it can isolate bus capacitance such that the total loading (devices,
connectors, traces and wires) of the new bus or remote I2C nodes are not apparent to other I2C buses (or
nodes). This is achieved by using one P82B715 device at each end of a long cable. The pin Lx of one P82B715
device must be connected to Lx of the second P82B715 (similarly for Ly). This allows the total system
capacitance load to be around 3000 pF. The P82B715 uses unidirectional analog current amplification to
increase the current sink capability of I2C chips to change the 400-pF I2C bus specification limit into a 3-nF bus
wiring capacitance limit. That means longer cables or lower-cost general-purpose wiring may be used to connect
two separate I2C-based systems, without worrying about the special voltage levels associated with other I2C bus
buffers.
Multiple P82B715s can be connected together in a star or multipoint architecture by their Lx/Ly ports, without
limit, as long as the total capacitance of the system remains less than about 3000 pF (400 pF or less when
referenced to any Sx/Sy connection). In that arrangement, the master and/or slave devices are attached to the
Sx/Sy port of each P82B715. In normal use, the power-supply voltages at each end of the low-impedance
buffered bus line should be the same. If these differ by a significant amount, noise margin is sacrificed.
Two or more Sx or Sy I/Os can be interconnected and are also fully compatible with bus buffers that use voltage-
level offsets (such as the TCA9517) because it duplicates and transmits the offset voltage.
VCC
P82B715
GND
8.3.2 Lx and Ly
The Lx and Ly pins are designed to interface with the high capacitance bus. This port of the device features
circuitry to assist in sinking large amounts of currents required to operate a large capacitance bus at high
speeds. More on this circuitry can be found in Lx/Ly Buffered Bus Circuitry.
+
–
GND
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
P82B715 P82B715
LDA SDA
SDA ½ ½
2
Long IC
Cable Device
LCL SCL
SCL ½ ½
VCC = 5 V
R4
SDA
Lx Sx 2
IC3
SCL
Ly Sy
If only a single pullup is used, it must be placed on the buffered bus (as R2 in Figure 5) and the associated total
system capacitance calculated by combining the individual bus capacitances into an equivalent capacitive
loading on the buffered bus.
This equivalent capacitance is the sum of the capacitance on the buffered bus plus ten times the sum of the
capacitances on all the connected I2C nodes. The calculated value should not exceed 4 nF. The single buffered
bus pullup resistor is then calculated to achieve the 1-μs rise time, and it provides the pullup for the buffered bus
and for all other connected I2C bus nodes included in the calculation.
R1 R2 R3
2
SDA
IC
Sx Lx LDA SDA 2
Lx IC
Sx
2
IC
SDA 3 nF = Cable Wiring Capacitance
GND 0V
2 × I C Devices
2
20 pF 2
1 × I C Devices 10 pF
Wiring Capacitance 3000 pF
Strays 20 pF Strays 10 pF
P82B715 10 pF P82B715 10 pF
Total 3000 pF
Total 50 pF Total 30 pF
2 2
Local I C Pullup Buffered Bus Pullup Remote I C Pullup
1 µs 1 µs 1 µs
R1 = = 20 kΩ R2 = = 330 Ω R3 = = 33 kΩ
50 pF 3000 pF 30 pF
3.5
Lx/Ly
3 Sx/Sy
2.5
Voltage (V)
1.5
0.5
0
Time
D002
11 Layout
To high-capacitance bus
0603 Cap
NC VCC
Lx Ly
Sx Sy
GND NC
To low-capacitance bus
Figure 8. D Package Example Layout
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2016
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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