LTC1052/LTC7652

Zero-Drift
Operational Amplifier
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FEATURES DESCRIPTIO
■ Guaranteed Max Offset: 5µV The LTC®1052 and LTC7652 are low noise zero-drift op
■ Guaranteed Max Offset Drift: 0.05µV/°C amps manufactured using Linear Technology’s enhanced
■ Typ Offset Drift: 0.01µV/°C LTCMOSTM silicon gate process. Chopper-stabilization
■ Excellent Long Term Stability: 100nV/√Month constantly corrects offset voltage errors. Both initial offset
■ Guaranteed Max Input Bias Current: 30pA and changes in the offset due to time, temperature and
■ Over Operating Temperature Range: common mode voltage are corrected. This, coupled with
Guaranteed Min Gain: 120dB picoampere input currents, gives these amplifiers
Guaranteed Min CMRR: 120dB unmatched performance.
Guaranteed Min PSRR: 120dB
Low frequency (1/f) noise is also improved by the
■ Single Supply Operation: 4.75V to 16V
chopping technique. Instead of increasing continuously
(Input Voltage Range Extends to Ground)
at a 3dB/octave rate, the internal chopping causes noise to
■ External Capacitors can be Returned to V – with No
decrease at low frequencies.
Noise Degradation
The chopper circuitry is entirely internal and completely
U transparent to the user. Only two external capacitors
APPLICATIO S are required to alternately sample-and-hold the offset
■ Thermocouple Amplifiers correction voltage and the amplified input signal. Control
■ Strain Gauge Amplifiers circuitry is brought out on the 14-pin and 16-pin versions
■ Low Level Signal Processing to allow the sampling of the LTC1052 to be synchronized
■ Medical Instrumentation with an external frequency source.
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
Teflon is a trademark of DuPont.

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TYPICAL APPLICATIO
Ultralow Noise, Low Drift Amplifier Noise Spectrum
5V 160
3 7
+
6 140
VOLTAGE NOISE DENSITY (nV/√Hz)

LTC1052
2 8 120
– 4
1 0.1µF 100
0.1µF
0.1µF
–5V 80

5V 60
100k 3K 1 5V 68k
1.5k
3 7 5V 40
INPUT + 8
®
LT 1007 OUTPUT 20
6
2
– 4 100k 0
– 5V 0 100 200 300 400 500

VOS = 3µV FREQUENCY (Hz)

100Ω
VOS∆T = 50nV/°C LTC1052/7652 • TA02

NOISE = 0.06µVP-P 0.1Hz TO 10Hz LTC1052/7652 • TA01

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LTC1052/LTC7652
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ABSOLUTE AXI U RATI GS (Notes 1 and 2)

Total Supply Voltage (V + to V –) ............................... 18V Operating Temperature Range

Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V) LTC1052C/LTC7652C ..........................–40°C to 85°C
Output Short Circuit Duration .......................... Indefinite LTC1052M (OBSOLETE).....................–55°C to 125°C
Storage Temperature Range .................. –55°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C

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PACKAGE/ORDER I FOR ATIO
TOP VIEW TOP VIEW
CEXTB
CEXTB
1 14 INT/EXT
8
CEXTA + CEXTA 2 13 CLK IN
1 7 V /CASE
NC (GUARD) 3 12 CLK OUT
– – IN 4 – 11 V +
– IN 2 6 OUTPUT
+ + IN 5 + 10 OUTPUT

+ IN 3 5 LTC1052 OUTPUT CLAMP NC (GUARD) 6 9 OUTPUT CLAMP

4 LTC7652 CRETURN
V– 7 8 CRETURN
V–
METAL CAN H PACKAGE N PACKAGE, 14-LEAD CERDIP
TJMAX = 110°C, θJA = 130°C/W
J PACKAGE, 14-LEAD CERDIP

OBSOLETE PACKAGE OBSOLETE PACKAGE

Consider the N8 Package for Alternate Source Consider the N14 Package for Alternate Source

ORDER PART NUMBER REPLACES ORDER PART NUMBER REPLACES

LTC7652CH ICL7652CTV LTC1052CN ICL7652CPD
ICL7652ITV ICL7650CPD
ICL7650CTV-1 LTC1052CJ ICL7652IJD
ICL7650ITV-1 ICL7650IJD
LTC1052CH ICL7650CTV LTC1052MJ ICL7650MJD
ICL7650ITV
LTC1052MH ICL7650MTV
TOP VIEW
TOP VIEW
CEXTB 1 16 INT/EXT
CEXTA
1 8 CEXTB
CEXTA 2 15 CLK IN
– IN 2 – 7 V+
NC (GUARD) 3 14 CLK OUT
+N 3 + 6 OUTPUT
4
OUTPUT – IN 13 V +
V– 4 5
CLAMP + IN 5 12 OUTPUT
N8 PACKAGE NC (GUARD) 6 11 OUTPUT CLAMP
8-LEAD PDIP
V– 7 10 CRETURN
TJMAX = 110°C, θJA = 150°C/W
NC 8 9 NC
J8 PACKAGE, 8-LEAD CERDIP SW PACKAGE
OBSOLETE PACKAGE 16-LEAD PLASTIC (WIDE) SO
TJMAX = 110°C, θJA = 150°C/W
Consider the N8 Package for Alternate Source

ORDER PART NUMBER REPLACES ORDER PART NUMBER REPLACES

LTC1052CN8 ICL7650CPA LTC1052CSW LTC1052CS
LTC1052CJ8 ICL7650IJA
LTC1052MJ8
Consult LTC Marketing for parts specified with wider operating temperature ranges. 1052fa

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 LTC1052/LTC7652
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, test circuit TC1, unless otherwise noted.
LTC1052M LTC1052C/LTC7652C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 3) ±0.5 ±5 ±0.5 ±5 µV
∆VOS/∆Temp Average Input Offset Drift (Note 3) ● ±0.01 ±0.05 ±0.01 ±0.05 µV/°C
∆VOS/∆Time Long-Term Offset Voltage Stability 100 100 nV/√Month
IOS Input Offset Current ±30 ±90 ±30 ±90 pA
● ±2000 ±350 pA
IB Input Bias Current ±1 ±30 ±1 ±30 pA
● ±1000 ±175 pA
enP-P Input Noise Voltage RS = 100Ω, DC to 10HZ, TC3 1.5 1.5 µVP-P
RS = 100Ω, DC to 1HZ, TC3 0.5 0.5 µVP-P
In Input Noise Current f = 10Hz (Note 5) 0.6 0.6 fA/√Hz
CMRR Common Mode Rejection Ratio VCM = V – to 2.7V ● 120 140 120 140 dB
PSRR Power Supply Rejection Ratio VSUPPLY = ±2.375V to ±8V ● 120 150 120 150 dB
AVOL Large-Signal Voltage Gain RL = 10k, VOUT = ±4V ● 120 150 120 150 dB
VOUT Maximum Output Voltage Swing RL = 10k ● ±4.7 ±4.85 ±4.7 ±4.85 V
(Note 4) RL = 100k ±4.95 ±4.95 V
SR Slew Rate RL = 10k, CL = 50pF 4 4 V/µs
GBW Gain Bandwidth Product 1.2 1.2 MHz
IS Supply Current No Load 1.7 2.0 1.7 2.0 mA
● 3.0 3.0 mA
fS Internal Sampling Frequency 330 330 Hz
Clamp On Current RL = 100k ● 25 100 25 100 µA
Clamp Off Current –4V < VOUT < 4V 10 100 10 100 pA
● 2 1 nA
Note 1: Absolute Maximum Ratings are those values beyond which the life testing. VOS is measured to a limit determined by test equipment
of a device may be impaired. capability. Voltages on CEXTA and CEXTB, AVOL, CMRR and PSRR are
Note 2: Connecting any terminal to voltages greater than V +, or less than measured to insure proper operation of the nulling loop to ensure meeting
V –, may cause destructive latch-up. It is recommended that no sources the VOS and VOS drift specifications. See Package-Induced VOS in the
operating from external supplies be applied prior to power-up of the Applications Information section.
LTC1052/LTC7652. Note 4: Output clamp not connected.
Note 3: These parameters are guaranteed by design. Thermocouple effects Note 5: Current noise is calculated from the formula: in = (2q IB)1/2, where
preclude measurement of the voltage levels in high speed automatic q = 1.6 • 10 –19 coulomb.

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TYPICAL PERFOR A CE CHARACTERISTICS
Input Noise Voltage
VS = ±5V, TEST CIRCUIT (TC3)
5µV

DC TO 1Hz
0

5µV

DC TO 10Hz
0

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LTC1052/LTC7652
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TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage vs Sampling 1OHzP-P Noise vs Sampling Input Bias Current vs
Frequency Frequency Temperature
12 5 1000
VSUPPLY= ± 5V
VSUPPLY= ±5V
900
GUARANTEED

10Hz PEAK-TO-PEAK NOISE (µV)

10

INPUT BIAS CURRENT, IB (pA)

4 800
700
8
VOS (µV)

3 600
6 500
2 400
4 300
1 200 GUARANTEED
2
100
0 0 0
0 500 1000 1500 2000 100 1k 10k –50 –25 0 25 50 75 100 125
SAMPLING FREQUENCY, fS (Hz) SAMPLING FREQUENCY, fS (Hz) AMBIENT TEMPERATURE, TA(°C)
LTC1052/7652 • TPC03
LTC1052/7652 • TPC01 LTC1052/7652 • TPC02

Common Mode Input Range vs Overload Recovery

Aliasing Error Supply Voltage (Output Clamp Not Used)
8
VS = ±5V VS = ±5V
AV = –1 6
OUTPUT SPECTRUM (dB)

TEST CIRCUIT TC2

COMMON MODE RANGE (V)
(3Hz BANDWIDTH)

IV/DIV
2

–2
VCM = V –
–4

fI–fS fS fI –6 OVERDRIVE 50ms/DIV

50Hz/DIV REMOVED
–8 AV = –100
0 1 2 3 4 5 6 7 8
SUPPLY VOLTAGE (±V)

LTC1052/7652 • TPC04

Small-Signal Transient Response* Large-Signal Transient Response* Gain Phase vs Frequency

120 60
VS = ± 5V
OUTPUT VOLTAGE (20mV/DIV)

100 CL= 100pF 80

OUTPUT VOLTAGE (2mV/DIV)

PHASE SHIFT (DEGREES)

80 100
VOLTAGE GAIN (dB)

PHASE
60 120
GAIN
40 140

20 160

0 180

AV = 1 2µs/DIV AV = 1 2µs/DIV –20 200

RL = 10k RL = 10k
CL = 100pF CL = 100pF –40 220
VS = ±5V VS = ±5V 100 103 104 105 106 107
*RESPONSE IS NOT DEPENDENT ON PHASE OF CLOCK FREQUENCY (Hz)
LTC1052/LTC7652 • TPC06

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TYPICAL PERFOR A CE CHARACTERISTICS
Broadband Noise, CEXT = 0.1µF Broadband Noise, CEXT = 1.0µF Broadband Noise Test Circuit (TC2)
R2
1M
INPUT REFERRED NOISE

INPUT REFERRED NOISE

R1 5V
1k 2 7
–
(5µV/DIV)

(5µV/DIV)
R3 6
LTC1052
1k 3 8
+ 4
1
CEXTA CEXTB

AV = – 1000 1ms/DIV AV = –1000 1ms/DIV

– 5V LTC1052/7652 • TPC07

Output Short-Circuit Current vs

Supply Current vs Supply Voltage Supply Current vs Temperature Supply Voltage
2.5 3.0 8

SHORT-CIRCUIT OUTPUT CURRENT, IOUT (mA)

SUPPLY VOLTAGE = ± 5V
6
2.0 ISOURCE VOUT = V –
SUPPLY CURRENT, IS(mA)
SUPPLY CURRENT, IS(mA)

4
2.0
1.5 2

0
1.0
1.0
– 10

0.5
– 20 ISINK VOUT = V +

0 0 – 30
4 5 6 8 10 12 14 16 –50 –25 0 25 50 75 100 125 4 5 6 8 10 12 14 16
TOTAL SUPPLY VOLTAGE, V + TO V – (V) AMBIENT TEMPERATURE, TA (°C) TOTAL SUPPLY VOLTAGE, V + TO V – (V)
LTC1052/LTC7652 • TPC08 LTC1052/LTC7652 • TPC09 LTC1052/LTC7652 • TPC10

Sampling Frequency vs
Sampling Frequency vs Voltage Temperature Comparator Operation
600 600
TA = 25°C SUPPLY VOLTAGE = ± 5V
SAMPLING FREQUENCY, fS (Hz)

500 500
SAMPLING FREQUENCY, fS (Hz)

1k 5 5V
VREF* 2
– 7
400 400 6
LTC1052
1k
3 8
300
VIN + 4
300
1
0.1µF 0.1µF
200 200

100 100 * – 5V ≤ VREF ≤ 2.7 V – 5V

0 0 LTC1052/7652 • TPC13
4 5 6 8 10 12 14 16 – 50 – 25 0 25 50 75 100 125
TOTAL SUPPLY VOLTAGE, V + TO V – (V) AMBIENT TEMPERATURE, TA (°C)
LTC1052/LTC7652 • TPC11 LT1052/LTC7652 • TPC12

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LTC1052/LTC7652
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TYPICAL PERFOR A CE CHARACTERISTICS
Response Time vs Overdrive

VREF + OVERDRIVE
INPUT
{ VREF – 1mV

10µV
5V
OUTPUT
{ –5V
50µV
5µV

20ms/DIV

TEST CIRCUITS
Electrical Characteristics Test Circuit (TC1) DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
C2 C3
R2
1M

R1 R2 R4
V+ 3
1k 2
+
7 V+
– C4 LT1001
6 OUTPUT
6 2 7 R3 (NOISE x 20,000)
LTC1052 OUTPUT – 2
–
3 8 6
+ 4 RL R1 LTC1052
3 8 34k
1 + 4
0.1µF 0.1µF 1
34k
0.1µF 0.1µF

V–
LTC1052/7652 • TC01 V–
BANDWIDTH R1 R2 R3 R4 C2 C3 C4
10Hz 16.2Ω 162k 16.2k 16.2k 0.1µF 1.0µF 1.0µF
1Hz 16.2Ω 162k 162k 162k 1.0µF 1.0µF 1.0µF

LTC1052/7652 • TC02

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THEORY OF OPERATIO
DC OPERATION
The shaded portion of the LTC1052 block diagram stage. CEXTB and S2 act as a sample-and-hold to store the
(Figure 1a) entirely determines the amplifier’s DC amplified input signal during the auto zero cycle.
characteristics. During the auto zero portion of the cycle, By switching between these two states at a frequency
the gm1 inputs are shorted together and a feedback path is much higher than the signal frequency, a continuous
closed around the input stage to null its offset. Switch S2 output results.
and capacitor CEXTA act as a sample-and-hold to store the Notice that during the auto zero cycle the gm1 inputs are
nulling voltage during the next step—the sampling cycle. not only shorted together, but are also shorted to the
In the sampling cycle, the zeroed amplifier is used to inverting input. This forces nulling with the common mode
amplify the differential input voltage. Switch S2 connects voltage present and accounts for the extremely high
the amplified input voltage to CEXTB and the output gain CMRR of the LTC1052. In the same fashion, variations in
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 LTC1052/LTC7652
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THEORY OF OPERATIO
power supply are also nulled. For nulling to take place, the For frequencies above this pole, I2 is:
offset voltage, common mode voltage and power supply I2 = VIN gm6 • 1 • SC1
must not change at a frequency which is high compared to SC2
the frequency response of the nulling loop. and
C1
I1 – I2 = VIN gm1 – VIN gm6 •
AC OPERATION AND ALIASING ERRORS C2
The LTC1052 is very carefully designed so that gm1 = gm6
So far, the DC performance of the LTC1052 has been and C1 = C2. Substituting these values in the above equa-
explained. As the input signal frequency increases, the tion shows I1 – I2 = 0.
problem of aliasing must be addressed. Aliasing is the
spurious formation of low and high frequency signals The gm6 input stage, with Cl and C2, not only filters the
caused by the mixing of the input signal with the sampling input to the sampling loop, but also acts as a high
frequency, fS. The frequency of the error signals, fE, is: frequency path to give the LTC1052 good high frequency
response. The unity-gain cross frequencies for both the
fE = fS ±fI DC path and high frequency path are identical
where fI = input signal frequency.
[f3dB = 1 (gm1/C1) = 1 (gm6/C2)]
Normally it is the difference frequency (fS – fI ) which is of 2π 2π
thereby making the frequency response smooth and con-
concern because the high frequency (fS + fI) can be easily tinuous while eliminating sampling noise in the output as
filtered. As the input frequency approaches the sampling the loop transitions from the high gain DC loop to the high
frequency, the difference frequency approaches zero and frequency loop.
will cause DC errors—the exact problem that the zero-drift
amplifier is meant to eliminate. The typical curves show just how well the amplifier works.
The output spectrum shows that the difference frequency
The solution is simple; filter the input so the sampling loop (fI –fS = 100Hz) is down by 80dB and the frequency
never sees any frequency near the sampling frequency. response curve shows no abnormalities or perturbations.
At a frequency well below the sampling frequency, the Also note the well-behaved small and large-signal step
LTC1052 forces I1 to equal I2 (see Figure 1b). This makes responses and the absence of the sampling frequency in
δ l zero, thus the gain of the sampling loop zero at this and the output spectrum. If the dynamics of the amplifier
higher frequencies (i.e., a low pass filter). The corner (i.e., slew rate and overshoot), depend on the sampling
frequency of this low pass filter is set by the output stage clock, the sampling frequency will appear in the output
pole (1/RL4 gm5 RL5 C2). spectrum.
C1
S3
VREF

C2

+ IN
S1 + S2
gm1 – gm2 –
+ gm4 + gm5 VOUT
– +
– IN – RL1 RL2 CEXT B RL4 RL5

VNULL CEXT A
gm3

– V–
gm6
LTC1052/7652 • TPC13
+
Figure 1a. LTC1052 Block Diagram
Auto Zero Cycle
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LTC1052/LTC7652
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THEORY OF OPERATIO
C1
S3
VREF

C2
l2
+ IN
S1 + δl S2
gm1 – gm2 –
+ gm4 + gm5 VOUT
– +
– IN – l1 RL1 RL2 CEXT B RL4 RL5
CEXT A
gm3

– V–
l3
gm6 LTC1052/7652 • TO02

+ Figure 1b. LTC1052 Block Diagram

Sampling Cycle

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APPLICATIO S I FOR ATIO
EXTERNAL CAPACITORS
CEXTA and CEXTB are the holding elements of a sample- On competitive devices, connecting CEXTA and CEXTB to
and-hold circuit. The important capacitor characteristics V – causes an increase in amplifier noise. Design changes
are leakage current and dielectric absorption. A high have eliminated this problem on the LTC1052. On the
quality film-type capacitor such as mylar or polypropylene 14-pin LTC1052 and 8-pin LTC7652, the capacitors can
provides excellent performance. However, low grade be returned to V – or CRETURN with no change in noise
capacitors such as ceramic are suitable in many performance.
applications.
Capacitors with very high dielectric absorption (ceramic) ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE
can take several seconds to settle after power is first
turned on. This settling appears as clock ripple on the Picoamperes
output and, as the capacitor settles, the ripple gradually In order to realize the picoampere level of accuracy of the
disappears. If fast settling after power turn-on is LTC1052, proper care must be exercised. Leakage
important, mylar or polypropylene is recommended. currents in circuitry external to the amplifier can
Above 85°C, leakage, both from the holding capacitors significantly degrade performance. High quality insulation
and the printed circuit board, becomes important. To should be used (e.g., Teflon, Kel-F); cleaning of all
maintain the capabilities of the LTC1052 it may be insulating surfaces to remove fluxes and other residues
necessary to use Teflon™ capacitors and Teflon standoffs will probably be necessary—particularly for high
when operating at 125°C (see Achieving Picoampere/ temperature performance. Surface coating may be
Microvolt Performance). necessary to provide a moisture barrier in high humidity
environments.
CEXTA and CEXTB are normally in the range of 0.1µF
to 1.0µF. All specifications are guaranteed with 0.1µF and Board leakage can be minimized by encircling the input
the broadband noise (refer to Typical Performance Char- connections with a guard ring operated at a potential
acteristics) is only very slightly degraded with 0.1µF. close to that of the inputs: in inverting configurations, the
Output clock ripple is not present for capacitors of 0.1µF guard ring should be tied to ground; in noninverting
or greater at any temperature. Teflon is a trademark of Dupont.
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APPLICATIO S I FOR ATIO
connections, to the inverting input. Guarding both sides Figure 2 is an example of the introduction of an
of the printed circuit board is required. Bulk leakage unnecessary resistor to promote differential thermal
reduction depends on the guard ring width. balance. Maintaining compensating junctions in close
physical proximity will keep them at the same temperature
and reduce thermal EMF errors.
NOMINALLY UNNECESSARY
RESISTOR USED TO
THERMALLY BALANCE OTHER LEAD WIRE/SOLDER/COPPER
INPUT RESISTOR TRACE JUNCTION

+
LTC1052 OUTPUT

RESISTOR LEAD, SOLDER,

–
COPPER TRACE JUNCTION

Microvolts
Thermocouple effects must be considered if the LTC1052’s LTC1052/7652 • AI03

ultralow drift is to be fully utilized. Any connection

Figure 2
of dissimilar metals forms a thermoelectric junction
producing an electric potential which varies with When connectors, switches, relays and/or sockets are
temperature (Seebeck effect). As temperature sensors, necessary they should be selected for low thermal EMF
thermocouples exploit this phenomenon to produce activity. The same techniques of thermally balancing and
useful information. In low drift amplifier circuits the effect coupling the matching junctions are effective in reducing
is a primary source of error. the thermal EMF errors of these components.
Connectors, switches, relay contacts, sockets, resistors, Resistors are another source of thermal EMF errors.
solder, and even copper wire are all candidates for Table 1 shows the thermal EMF generated for different
thermal EMF generation. Junctions of copper wire from resistors. The temperature gradient across the resistor is
different manufacturers can generate thermal EMFs of important, not the ambient temperature. There are two
200nV/°C—4 times the maximum drift specification of junctions formed at each end of the resistor and if these
the LTC1052. The copper/kovar junction, formed when junctions are at the same temperature, their thermal EMFs
wire or printed circuit traces contact a package lead, has will cancel each other. The thermal EMF numbers are
a thermal EMF of approximately 35µV/°C– 700 times the approximate and vary with resistor value. High values give
maximum drift specification of the LTC1052. higher thermal EMF.
Minimizing thermal EMF-induced errors is possible if
Table 1. Resistor Thermal EMF
judicious attention is given to circuit board layout and
component selection. It is good practice to minimize the RESISTOR TYPE THERMAL EMF/°C GRADIENT
number of junctions in the amplifier’s input signal path. Tin Oxide ~mV/’C
Avoid connectors, sockets, switches and relays where Carbon Composition ~450µV/°C
possible. In instances where this is not possible, attempt Metal Film ~20µV/°C
to balance the number and type of junctions so that Wire Wound
differential cancellation occurs. Doing this may involve Evenohm ~2µV/°C
deliberately introducing junctions to offset unavoidable Manganin ~2µV/°C
junctions.
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APPLICATIO S I FOR ATIO
When all of these errors are considered, it may seem Figure 4 shows the response of this circuit under
impossible to take advantage of the extremely low drift temperature transient conditions. Metal film resistors and
specifications of the LTC1052. To show that this is not the an 8-pin DIP socket were used. Care was taken in the
case, examine the temperature test circuit of Figure 3. The construction to thermally balance the inputs to the
lead lengths of the resistors connected to the amplifier’s amplifier. The units were placed in an oven and allowed to
inputs are identical. The thermal capacity and thermal stabilize at 25°C. The recording was started and after
resistance each input sees is balanced because of the 100 seconds the oven, preset to 125°C, was switched on.
symmetrical connection of resistors and their identical The test was first performed on an 8-pin plastic package
size. Thermal EMF-induced shifts are equal in phase and and then was repeated for a TO-5 package plugged into the
amplitude, thus cancellation occurs. same test board. It is significant that the change in VOS,
50k
even under these severe thermal transient conditions,
is quite good. As temperature stabilizes, note that the
5V
2 7 steady-state change of VOS is well within the maximum
–
100Ω LTC1052
6 ±0.05µV/°C drift specification.
3 8
+ 4 VOS • 1000 Very slight air currents can still affect even this
1
0.1µF 50k 0.1µF 0.1µF
arrangement. Figure 5 shows strip charts of output noise
–5V
both with the circuit covered and with no cover in “still” air.
LTC1052/7652 • AI04 This data illustrates why it is often prudent to enclose the
LTC1052 and its attendant components inside some form
Figure 3. Offset Drift Test Circuit of thermal baffle.

0 MIN 5 MIN 20 MIN 25 MIN

10
25°C TO 125°C
PLASTIC
OFFSET VOLTAGE, VOS (10µV/DIV)

0 ±0.05µV/°C

10
25°C TO 125°C
METAL CAN
0 ±0.05µV/°C

OVEN SWITCHED OVEN STABILIZED

ON (25°C) AT 12 MIN
100 SECONDS/IN

Figure 4. Transient Response of Offset Drift Test Circuit with 100°C Temperature Step

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APPLICATIO S I FOR ATIO

#1 COVERED

1µV

#1 UNCOVERED

#2 UNCOVERED

20 SEC

Figure 5. DC to 1Hz (Test Circuit TC3)

PACKAGE-INDUCED OFFSET VOLTAGE CLOCK

Since the LTC1052 is constantly fixing its own offset, it The LTC1052 has an internal clock, setting the nominal
may be asked why there is any error at all, even under sampling frequency at 330Hz. On 8-pin devices, there is
transient temperature conditions. The answer is simple. no way to control the clock externally. In some applica-
The LTC1052 can only fix offsets inside its own nulling tions it may be desirable to control the sampling clock and
loop. There are many thermal junctions outside this loop this is the function of the 14-pin device.
that cannot be distinguished from legitimate signals. CLK IN, CLK OUT and INT/EXT are provided to accomplish
Some have been discussed previously, but the package this. With no external connection, an internal pull-up holds
thermal EMF effects are an important source of errors. INT/EXT at the V + supply and the 14-pin device self-
Notice the difference in the thermal response curves of oscillates at 330Hz. In this mode there is a signal on the
CLK IN pin of 660Hz (2 times sampling frequency) with a
Figure 4. This can only be attributed to the package since
30% duty cycle. A divide-by-two drives the CLK OUT pin
everything else is identical. In fact, the VOS specification is
and sets the sampling frequency.
set by the package-induced warm-up drift, not by the
LTC1052. TO-99 metal cans exhibit the worst warm-up To use an external clock, connect INT/EXT to V – and the
drift and Linear Technology sample tests TO-99 lots to external clock to CLK IN. The logic threshold of CLK IN is
minimize this problem. 2.5V below the positive supply; this allows CMOS logic to
drive it directly with logic supplies of V+ and ground. CLK
Two things make 100% screening costly: (1) The extreme
IN can be driven from V+ to V – if desired. The duty cycle of
precision required on the LTC1052 and (2) the thermal
the external clock is not particularly critical but should be
time constant of the package is 0.5 to 3 minutes, depend-
kept between 30% and 60%.
ing on package type. The first precludes the use of auto-
matic handling equipment and the second takes a long Capacitance between CLK IN and CLK OUT (pins 13 and
time. Bench test equipment is available to 100% test for 12) can cause the divide-by-two circuit to malfunction. To
warmed-up drift if offsets of less than ±5µV are required. avoid this, keep this capacitance below 5pF.

1052fa

11
LTC1052/LTC7652
U U W U
APPLICATIO S I FOR ATIO
OUTPUT CLAMP within approximately 1V of either supply rail. This switch
is in parallel with the amplifier’s feedback resistor. As the
If the LTC1052 is driven into saturation, the nulling loop,
output moves closer to the rail, the switch on
attempting to force the differential input voltage to zero,
resistance decreases, reducing the closed loop gain. The
will drive CEXTA and CEXTB to a supply rail. After the
output swing is reduced when the clamp function is used.
saturating drive is removed, the capacitors take a finite
time to recover—this is the overload recovery time. The How much current the output clamp leaks when off
overload recovery is longest when the capacitors are is important because, when used, it is connected to the
driven to the negative rail (refer to Overload Recovery in amplifier’s negative input. Any current acts like input bias
the Typical Performance Characteristics section). The current and will degrade accuracy. At the other extreme,
overload recovery time in this case is typically 225ms. In the maximum current the clamp conducts when on deter-
the opposite direction (i.e., CEXTA and CEXTB at positive mines how much overdrive the clamp will take, and still
rail), it is about ten times faster (25ms). The overload keep the amplifier from saturating. Both of these numbers
recovery time for the LTC1052 is much faster than com- are guaranteed in the Electrical Characteristics section.
petitive devices; however, if a faster overload recovery
time is necessary, the output clamp function can be used. LOW SUPPLY OPERATION
When the output clamp is connected to the negative input The minimum supply voltage for proper operation of the
it prevents the amplifier from saturating, thus keeping LTC1052 is typically 4.0V (±2.0V). In single supply
CEXTA and CEXTB at their nominal voltages. The output applications, PSRR is guaranteed down to 4.7V (±2.35V).
clamp is a switch that turns on when the output gets to This assures proper operation down to the minimum TTL
specified voltage of 4.75V.

U
TYPICAL APPLICATIO S
5V Powered Ultraprecision Instrumentation Amplifier Fast Precision Inverter
5V

4 5V 10k* 10k*
3 7 INPUT
+ IN 7 8 +
6 10k
LTC1052 VOUT 8pF
2 8
11 –
1
4 1N4148
C1 C2
1µF 1µF 0.1µF
0.1µF 1000pF
12 R2 300pF
100k
R1 5V
100
13 2 7
– IN 14 5V +
LTC1043 0.22µF 2 7 6
+ LT318A OUTPUT
6 3
5V 6 5
10k 3
LTC1052 – 4
43k 8
– 4
10k
–5V
1
2 + C4
1µF 10k 0.1µF 0.1µF
1N914 C3
1µF

3 – 5V

*1% METAL FILM

≈ – 0.5V
18 15 FULL POWER BANDWIDTH = 2MHz
SLEW RATE = 40V/µs
0.0047µF SETTLING (10V STEP) = 12µs TO 0.01%
CIRCUITRY WITHIN DASHED LINES MAY BE DELETED IF OUTPUT
BIAS CURRENT DC = 30pA
DOES NOT HAVE TO SWING ALL THE WAY TO GROUND
17 16 OFFSET DRIFT = 50nV/°C
DRIFT = 50nV/°C OFFSET VOLTAGE = 5µV LTC1052/7652 • TA04
VOS = 3µV
GAIN = R2 + 1
R1
CMRR = >120dB DC – 20kHz
BANDWIDTH = 10Hz LTC1052/7652 • TA03

1052fa

12
 LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Offset Stabilized Comparator
5V

4
5V
+ 14 13

330Ω 150Ω 2k
8
2
12 + 6
COMPARATOR 7 COMPARATOR
INPUTS LT1011
3 OUTPUT (± 5V)
5
11 – 1
4
10k
– 5V
GROUND OR – 8 7
1µF
INPUT COMMON-
MODE VOLTAGE
LTC1043 5V
1M 2 7
5 6 +
6
LTC1052
3 8
– 4
2 1
3 0.1µF 0.1µF

– 5V STATUS OUTPUT
5V 15 18 OV = ZERO
5V = COMPARE
ZERO COMMAND
5V = ZERO 16 17
– 5V = COMPARE
–5V LTC1052/7652 • TA05

1HZ to 1.25MHz Voltage-to-Frequency Converter (5V Supply)

5V 470Ω

0.01µF
470Ω
10k
3
+ 7
6 3.3k Q1 NC
LTC1052
2N2907
2 8
– 4 2N3904
1
5V 74C04
0.1µF 0.1µF 330pF
10k
OUTPUT
1H to 1.25MHz
0.01µF

10k
FULL-SCALE TRIM 2k 5V 3.3pF
(1.25MHz) 5V
VIN 30.1k*
10k
OV TO 5V 4
8 7
0.22µF

11

100pF** LT1004-1.2V 0.1µF

*TRW MTR–5/ +1200ppm/°C 12

**POLYSTYRENE–WESCO #32–P/ – 120ppm/°C

± 0.05% LINEARITY
>120dB DYNAMIC RANGE 14 13
0.01Hz/°C ZERO POINT DRIFT 1/2 LTC1043
20ppm/°C GAIN DRIFT 16
LTC1052/7652 • TA06

17

1052fa

13
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
No VOS Adjust* CMOS DAC Buffer—Single Supply Air Flow Detector
15V
CF * 10k 5V
5
RFB 1k 15V
2
lOUT1 + 7
6 100k
12–BIT CMOS DAC LTC1052 VOUT ± 1%
3 5
8 2
lOUT2 – 4 FOR HIGHER SPEED, REFER TO + 7
1 “FAST PRECISION INVERTER” 1k 6 5V = NO AIR FLOW
LT1004-1.2 LTC1052
15V UNDER TYPICAL APPLICATIONS 0V = AIR FLOW
0.1µF 0.1µF 3 8
43.2Ω – 4
± 1% 1
43k 0.1µF 0.1µF
4

6 5
AMBIENT – –
10k
TEMPERATURE 240Ω
TYPE K
STILL AIR + +
LTC1052/7652 • TA08
11
+ 1µF
1N914 0.1µF NON POLARIZED
*OFFSET VOLTAGE CAUSES
AIR FLOW
12 NONLINEARITY ERRORS.
SEE: “APPLICATION GUIDE
TO CMOS MULTIPLYING D/A
CONVERTERS,”
≈ – 0.5V
15 15 ANALOG DEVICES, INC.
1pF LTC1052/7652 • TA07

1/2 LTC1043
16

17

1Hz to 30MHz Voltage-to-Frequency Converter

5V

120Ω

CURRENT
12k
STABILIZING SOURCE
0.1µF
AMP
120Ω
3
+ 7
6 7.5k
LTC1052 2N3906
2 8 NC
– 4 FET BUFFER
1 2N5486
RESET DIODE 1Hz TO 30MHz
0.1µF 0.1µF 2N3904 OUTPUT
100pF 5V
50Ω 74S132
0.0.1µF
– 5V
OUT
2k
10k 2N5486
30MHz
TRIM 0.22µF
16.2k* 5V
IN
CHARGE 50Ω TRIGGER
OV TO 3V
PUMP HP5082-2810
2k
5V
8 7 – 5V

100k

1000M 11 LT1004–1.2V
10k
1Hz TRIM
100pF † 0.22µF

100k 12 10

– 5V
*TRW MTR-5/ + 120ppm/°C
†WESCO #32-P/ – 120ppm/°C
14 13 0.3Hz/°C ZERO-DRIFT
5V 5V
±0.08% LINEARITY
5 14
20ppm/°C GAIN DRIFT
11 14 5 3
1/2 LTC1043 16 7490 1/2 74S74 150dB DYNAMIC RANGE

10 11 12 7
LTC1052/7652 • TA09

1052fa

14
 LTC1052/LTC7652
U
TYPICAL APPLICATIO S
±100mA Output Drive Increasing Output Current
5V
100k 220pF
VIN
74C04
5V 5V
2 7 100pF 1M
– 5V
6 10k 2
LTC1052 LTC1010 VOUT INPUT – 7
3 8 6 OUTPUT
+ 4 ±100mA
LTC1052
1 3 8
– 5V + 4
RL
1
0.1µF 0.1µF
0.1µF 0.1µF

– 5V
100k
VOS = 5µV
VOS/∆T = 50µV/°C
GAIN = 10 LOAD OUTPUT SWING 100Ω
FULL POWER BANDWIDTH = 1kHz LTC1052/7652 • TA10
10k 5k ± 4.92V
2.5k ± 4.84V 2000pF
1k ± 4.65V
220Ω ± 3.65V LTC1052/7652 • TA11

Single 5V Thermocouple Amplifier with Cold Junction Compensation

5V
VT +
– 1k
100k

LT1004-1.2 R1

5V
1690Ω
5k AT 25°C†
4 5V
3 7
7 8 –
187Ω 1820Ω
2
LTC1052
8
6
( )
R
VOUT = VT 1 + F
Rl
+ 4
11
1
1µF 1µF 0.1µF 0.1µF
RF CF*
12

13 14
43k
5V 6 5 Rl

2
+ 1µF
IN914 1µF
NONPOLARIZED

≈ – 0.5V 10k
18 15
LTC1052/7652 • TA12
THERMOCOUPLE
LTC1043 TYPE R1
16 † YELLOW SPRINGS INST. CO. PART #44007 J 232k
0.0047µF *CHOOSE CF TO FILTER NOISE K 301k
17 T 301k
S 2.1M

1052fa

15
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Increasing Output Current and Voltage (VSUPPLY = ±15V) DC Stabilized FET Probe
INPUT CAPACITANCE BOOTSTRAP
5V
FAST SOURCE
Q1 FOLLOWER
INPUT
7V 2N3904 2N5486
15V 5V
0.1µF 30k 33pF 1N4148
3k 2 NC
7
INPUT – LT1010 OUTPUT
6 3 7
LTC1052 + 10M V+ 10M
3 8 6 OUTPUT – 5V
+ 4 LT318A
±12V AT 20mA | LIMIT
7 3
1 2 DRAIN CURRENT SINK +
– 4 3k Q2 10k 6
0.1µF 0.1µF LTC1052 0.1µF
2N2222
8 2
2N3904
0.01µF
4
–
– 7V –15V 100Ω
1
1k
0.1µF – 5V 0.1µF 0.1µF
NC
2000pF
DC STABILIZATION
STABLE FOR ALL GAINS, INVERTING
AND NONINVERTING, OBSERVE
LTC1052 COMMON MODE INPUT LIMITS LTC1052/7652 • TA13
0.1µF 1k BANDWIDTH: 20MHz
†RISE: 100ns
DELAY: 5ns LTC1052/7652 • TA14

Precision Multiplexed Differential Thermocouple Amplifier

5V

COLD JUNCTION
COMPENSATOR 100k

R1 4
LT1004–1.2V
3
7 8 – 7
6
LTC1052 VOUT = 1001 • VTHERMOCOUPLE
5k AT 8
2
25°C† + 4
1690Ω 11
1

1µF 1µF 0.1µF 0.1µF 0.1µF

187Ω 1820Ω
12
– 5V 1M

13 14
5V
6 5 1k
16

12 13 2

1 3 1µF 1µF

3
14 † YELLOW SPRINGS INST. CO. PART #44007

5 18 15
LTC1043
THERMOCOUPLE
16 TYPE R1
15 J 232k
0.0047µF 17 K 301k
2 T 301k
S 2.1M
– 5V
11 9
ADDRESS
4 10
8 7
CD4052B
– 5V LTC1052/7652 • TA15

1052fa

16
 LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Direct Thermocouple-to-Frequency Converter

RT COLD JUNCTION TEMPERATURE TRACKING

–
TYPE K 1N4148
STABILIZING AMP 1.8k* 470Ω
+ THERMOCOUPLE 41.4µV/°C 5V
3 7
+ A
6 33k 10k B C D E
100k 1N914 LTC1052
2 8 74C04
– 4
1µF 1 0.68µF

OPTIONAL INPUT 0.1µF 0.1µF

FILTER-AND-OVERLOAD 820pF
CLAMP
– 5V
3300pF
150k**
5V 5V
50k 74C04 OUTPUT
60°C TRIM F
0Hz TO 600Hz
5V 0°C TO 60°C
33k** 16 – 5V
3k
A† LTC1043 74C903
4.75k*
5 6
1µF *0.01% FILM-TRW MAR-6
0.1µF 1k* LT1004–1.2V **TRW/MTR/5/ + 120
2 RT = YELLOW SPRINGS INST. #44007
100pF = POLYSTYRENE
100pF †
FOR GENERAL PURPOSE (1mV FULL-SCALE)
COLD JUNCTION BIAS 10-BIT A-TO-D, REMOVE THERMOCOUPLE—
487Ω* 301k* COLD JUNCTION NETWORK, GROUND POINT A,
AND DRIVE LTC1052 POSITIVE INPUT

187Ω*
LTC1052/7652 • TA16

Direct 10-Bit Strain Gauge Digitizer

5V
74C00
5V
1000pF
20Ω STRAIN GAUGE – 5V
28k 14k 0.003µF
20Ω TRANSDUCER
1 CLOCK 5V
3 ZIN = 350Ω
+ 8 6 ZOUT = 350Ω
1k
LM301A 2N2905 INTEGRATOR
5V
2 4 1000pF 5V FREQUENCY
– 2 OUT B
7 – 5V
– 7
14 1 4 3 10k
470k* 6 2 5 1/2 74C903
LTC1052 1/2 74C74 5V
5V
3 8
+ 4 7 6 FREQUENCY
3.3MΩ* 1 – 5V OUT A
– 5V
1/2 LTC1043 0.01µF 0.01µF
BRIDGE DRIVE OUTPUT
7 8 GATING
SW1 – 5V OUT A = 1000 COUNTS FULL-SCALE
DATA OUTPUT =
1N4148 OUT B
*0.1% METAL FILM TRW MAR-5
1N4148 11 SW1 = MAIN CURRENT SWITCH
16 SW2 = CURRENT LOADING COMPENSATION SWITCH
– 5V 3.3M
12

SW2 CONNECT DIRECTLY 100k

CONNECT TO BRIDGE
ACROSS BRIDGE
13 14 10k END OF 470k RESISTOR
DRIVE POINTS
(OPTIONAL)
TRANSDUCER ZERO NETWORK

22.3k* + LTC1052/7652 • TA17

1k* 33µF

1052fa

17
LTC1052/LTC7652
U
TYPICAL APPLICATIO S
16-Bit A/D Converter

74C00

28k 14k 820pF 5V

CLOCK
0.01µF BOUT

10k
5V
5V
EIN 95k* 2 1/3 74C903
– 7
OV TO 5V 14 1 4 2
10k 6 2 10pF 5V
LTC1052 1/2 74C74
FULL-SCALE
3 A2
TRIM + 8 INTEGRATOR 7 5 6 AOUT
4
1
– 5V
0.1µF 0.1µF
5V
– 5V 5V
1k 16 4
7 3
+ 13 14
6
2N4338 LTC1052
2
8 – 12
4
1
LT1009 1µF 0.01µF 39pF
0.1µF 0.1µF
11
– 5V

75k* 20k 7 8
LINEARITY
TRIM 18 15
CURRENT SINK
– 5V

3
A
DATA OUTPUT = OUT
BOUT
LTC1043
100,000 COUNTS FULL-SCALE
NO ZERO TRIM 17
20ppm/°C GAIN DRIFT
– 5V
*VISHAY S-102 RESISTOR
CURRENT SWITCH LTC1052/7652 • TA18

1052fa

18
 LTC1052/LTC7652
U
TYPICAL APPLICATIO S
Precision Isolation Amplifier

1k* INPUT SIDE OUTPUT SIDE

74C04
10k 10k
20k
ZERO TRIM
4 – 15V 15V
– 100k*
4 1
2N5434 2N5434 30pF
22M
1
LTC1052 10 5 2 100k 3
14–PIN
+
2 L2 8
STANCOR PCT-39 6
7 1000pF LTC1052 OUT
2
5 1 – 4
2N5434 2N5434 1k GAIN TRIM
INPUT + 14
6 3
7 – 15V
100k 0.1µF 0.1µF
13 15V
10k 13.3k*
11
5 5
74C04
10k IN4148
11 74C90 14 11 74C90 14
÷10 ÷10 100pF
10M
2k 2k (SELECT) 10k*
10 1 12 10 1 12 330Ω
15V 68pF

1N4148 1N4148 1.8k

NC 2N3904 1k
– 15V
25mA 7 1
FLOATING 2.2µF 74C04
+ 2N2222
SUPPLY NC 2N3904 L1
OUTPUTS 11k POWER
DALE TC–10–11
15V DRIVER – 15V
8 1000pF 20k
1N4148 15V
25mA + 2
4.3k
2.2µF
20k
FLOATING COMMON 68pF
2N2222
9 3

LTC1052/7652 • TA19
1k
250V ISOLATION 1.8k
0.03% ACCURACY
*1% FILM RESISTOR 15V

1052fa

19
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
H Package
8-Lead TO-5 Metal Can (.200 Inch PCD)
(Reference LTC DWG # 05-08-1320)

.335 – .370
(8.509 – 9.398)
DIA
.305 – .335
(7.747 – 8.509)
.040
(1.016) .050
MAX (1.270) .165 – .185
MAX (4.191 – 4.699)
REFERENCE
SEATING PLANE
PLANE GAUGE
PLANE .500 – .750
.010 – .045* (12.700 – 19.050)
(0.254 – 1.143)
.016 – .021**
(0.406 – 0.533)

.027 – .045
(0.686 – 1.143)
45°TYP PIN 1
.028 – .034
(0.711 – 0.864)

.200
(5.080)
TYP

.110 – .160
(2.794 – 4.064)
INSULATING
STANDOFF

*LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE

AND THE SEATING PLANE
.016 – .024
**FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS
(0.406 – 0.610) H8(TO-5) 0.200 PCD 0801

OBSOLETE PACKAGE

1052fa

20
 LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
J Package
14-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)

.785
(19.939)
.005
MAX
(0.127)
MIN 14 13 12 11 10 9 8

.025 .220 – .310

(0.635) (5.588 – 7.874)
RAD TYP

1 2 3 4 5 6 7 .200
.300 BSC
(5.080)
(7.62 BSC) MAX

.015 – .060
(0.381 – 1.524)

.008 – .018
0° – 15°
(0.203 – 0.457)

.045 – .065 .100 .125

(1.143 – 1.651) (2.54) (3.175)
.014 – .026 BSC MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS (0.360 – 0.660) J14 0801

OBSOLETE PACKAGE

1052fa

21
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)

CORNER LEADS OPTION .405

(4 PLCS) (10.287)
.005 MAX
(0.127)
MIN
8 7 6 5
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION .025 .220 – .310
.045 – .068 (0.635) (5.588 – 7.874)
(1.143 – 1.650) RAD TYP
FULL LEAD
OPTION
1 2 3 4 .200
.300 BSC
(5.080)
(7.62 BSC) MAX

.015 – .060
(0.381 – 1.524)

.008 – .018
0° – 15°
(0.203 – 0.457)

.045 – .065
.125
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143 – 1.651)
OR TIN PLATE LEADS 3.175
.014 – .026 MIN
.100
(0.360 – 0.660) (2.54)
BSC J8 0801

OBSOLETE PACKAGE

N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)

.400*
(10.160)
MAX

8 7 6 5

.255 ± .015*
(6.477 ± 0.381)

1 2 3 4

.300 – .325 .045 – .065 .130 ± .005

(7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127)

.065
(1.651)
.008 – .015 TYP
(0.203 – 0.381) .120
(3.048) .020
+.035 MIN (0.508)
.325 –.015
.100 .018 ± .003 MIN

( 8.255
+0.889
–0.381 ) (2.54)
BSC
(0.457 ± 0.076)
N8 1002

NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1052fa

22
 LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.770*
(19.558)
MAX
14 13 12 11 10 9 8

.255 ± .015*
(6.477 ± 0.381)

1 2 3 4 5 6 7

.300 – .325 .130 ± .005 .045 – .065

(7.620 – 8.255) (3.302 ± 0.127) (1.143 – 1.651)

.020
(0.508)
MIN .065
.008 – .015 (1.651)
(0.203 – 0.381) TYP

+.035
.325 –.015 .005
.120 .018 ± .003
(0.125) .100
(8.255
+0.889
–0.381 ) (3.048)
MIN MIN (2.54)
BSC
(0.457 ± 0.076)

NOTE:
INCHES
1. DIMENSIONS ARE N14 1002
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

1052fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23
LTC1052/LTC7652
U
PACKAGE DESCRIPTIO
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)

.030 ±.005 .050 BSC .045 ±.005 .398 – .413

TYP (10.109 – 10.490)
NOTE 4
N 16 15 14 13 12 11 10 9

.420 .325 ±.005

MIN
NOTE 3 .394 – .419
(10.007 – 10.643)

1 2 3 N/2 N/2

RECOMMENDED SOLDER PAD LAYOUT

1 2 3 4 5 6 7 8

.291 – .299
(7.391 – 7.595)
NOTE 4 .037 – .045
.093 – .104
.010 – .029 × 45° (0.940 – 1.143)
(2.362 – 2.642)
(0.254 – 0.737)
.005
(0.127)
RAD MIN 0° – 8° TYP

.050
.009 – .013 (1.270) .004 – .012
(0.229 – 0.330) NOTE 3 BSC (0.102 – 0.305)
.014 – .019
.016 – .050
(0.356 – 0.482)
(0.406 – 1.270)
TYP
NOTE:
INCHES
1. DIMENSIONS IN S16 (WIDE) 0502
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

1052fa

LW/TP 1202 1K REV A • PRINTED IN USA

Linear Technology Corporation
24 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ●
www.linear.com  LINEAR TECHNOLOGY CORPORATION 1985