bq30z554-r1 Charger

bq30z554-R1
www.ti.com SLUSBD4 – OCTOBER 2013
2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

Check for Samples: bq30z554-R1
1FEATURES DESCRIPTION
2• Fully Integrated 2-Series, 3-Series, and 4- The bq30z554-R1 device is a fully integrated
Series Li-Ion or Li-Polymer Cell Battery Pack Impedance Track™ gas gauge and analog monitoring
Manager and Protection single-package solution that provides protection and
monitoring with authentication for 2-series, 3-series,
• High Side N-CH Protection FET Drive and 4-series cell Li-Ion battery packs. The bq30z554-
• Impedance Track™ Gas Gauging R1 device incorporates sophisticated algorithms that
• Integrated Cell Balancing While Charging or At offer cell balancing while charging or at rest.
Rest The device communicates via an SBS v1.1 interface,
• PF Snapshot and Black Box Technology providing high accuracy cell parameter reporting and
Analyze Returned Packs control of battery pack operation, and can be
designed into systems that require AC peak power
• AC Peak Power Information Capability (TURBO mode), using a method to ensure that
(TURBO Mode) system performance is not disrupted.
• SBS v1.1 Interface
An optimum balance of quick response hardware-
• Low Power Modes based protection along with intelligent CPU control
– Low Power: < 180 μA delivers an ideal pack solution. The device has
– Sleep < 76 μA flexible user-programmable settings of critical system
parameters, such as voltage, current, temperature,
• Complete Set of Advanced Protections: and cell imbalance, among other conditions.
– Internal Cell Short
The bq30z554-R1 device has advanced charge
– Cell Imbalance algorithms, including JEITA support, enhanced cell
– Cell Voltage charging, and adaptive charging compensating
– Overcurrent charge losses, enabling faster charging. In addition,
the bq30z554-R1 device can monitor critical
– Temperature parameters over the life of the battery pack, tracking
– FET Protection usage conditions.
• Sophisticated Charge Algorithms A general purpose output is used for power
– JEITA interruption, employing an external push button
– Enhanced Charging switch.
– Adaptive Charging The advanced snapshot and black box functionality
show critical information for analysis of returned
– Cell Balancing While Charging or At Rest
battery packs.
• General Purpose Output for Power Interrupt
SHA-1 authentication with secure memory for
• Diagnostic Lifetime Data Monitor authentication keys enables identification for genuine
• SHA-1 Authentication battery packs beyond doubt.
• Small Package: TSSOP
APPLICATIONS
• Notebook/Netbook PCs
• Medical and Test Equipment
• Portable Instrumentation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq30z554-R1
SLUSBD4 – OCTOBER 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PACKAGE PACKAGE ORDERING INFORMATION (1)
TA PART NUMBER PACKAGE
DESIGNATOR MARKING TUBE (2) TAPE AND REEL (3)
–40°C to 85°C bq30z554-R1 TSSOP–30 DBT bq30z554-R1 bq30z554DBT-R1 bq30z554DBTR-R1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 50 units.
(3) A single reel quantity is 2000 units.
THERMAL INFORMATION
bq30z554-R1
(1)
THERMAL METRIC TSSOP UNITS
30 PINS
θJA, High K Junction-to-ambient thermal resistance (2) 73.1
(3)
θJC(top) Junction-to-case(top) thermal resistance 17.5
(4)
θJB Junction-to-board thermal resistance 34.5
(5)
°C/W
ψJT Junction-to-top characterization parameter 0.3
(6)
ψJB Junction-to-board characterization parameter 30.3
(7)
θJC(bottom) Junction-to-case(bottom) thermal resistance n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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bq30z554-R1
TYPICAL IMPLEMENTATION
PACK +
3MΩ
3MΩ
5.1kΩ
5.1kΩ
5.1kΩ
10kΩ
FUSE
CHG
DSG
VCC
PACK
BAT
High Side
FUSE Cell
N-CH FET
Control Balancing
Drive
VC1
CD VH 1kΩ
VC2
OUT VM 1kΩ
16-bit Impedance SHA-1 REG33
Voltage
Voltage Track Authenti- 3.3V LDO
Protections
Sensing Gauging cation
VC3
16-bit Internal Cell JEITA REG25
Current
VDD VL 1kΩ Current
Protections
Short Charging 2.5V LDO
Sensing Detection Algorithm
VC4 16-bit Lifetime SMBD

Voltage Black Box
Temperature Data SMBus 1.1 SMBD
GND Sensing
Protections
Collection
Recorder
VB 1kΩ
SMBC 200Ω 100Ω
PTC SMBC
SBD 1.1 ¯¯¯¯¯
PRES 200Ω 100Ω
¯¯¯¯¯
PRES
10kΩ
100Ω 1kΩ
TS1
TS2
VSS SRP SRN
10kΩ
10kΩ
10kΩ
0.1μF 0.1μF 0.1μF
PACK–
5mΩ
Figure 1. bq30z554-R1 Implementation
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3

bq30z554-R1
TERMINAL FUNCTIONS
PIN NAME PIN NUMBER TYPE DESCRIPTION
CHG 1 O Discharge N-FET gate drive
BAT 2 P Alternate power source
VC1 3 I Sense input for positive voltage of the top-most cell in the series, and cell balancing input for the
top-most cell in the series
VC2 4 I Sense input for positive voltage of the third lowest cell in the series, and cell balancing input for
the third lowest cell in the series
VC3 5 I Sense input for positive voltage of the second lowest cell in the series, and cell balancing input
for the second lowest cell in the series
VC4 6 I Sense input for positive voltage of the lowest cell in the series, and cell balancing input for the
lowest cell in the series
VSS 7 P Device ground
TS1 8 AI Temperature sensor 1 thermistor input
SRP 9 AI Differential coulomb counter input
TS2 11 AI Temperature sensor 2 thermistor input
SRN 10 AI Differential coulomb counter input
PRES 12 I Host system present input
SMBD 13 I/OD SBS 1.1 data line
NC 14 — Not connected, connect to VSS
SMBC 15 I/OD SBS 1.1 clock line
GPIO 16 I/OD General Purpose Input-Output
NC 17,18,19,20 — Not connected
RBI 21 P RAM backup
REG25 22 P 2.5-V regulator output
VSS 23 P Device ground
REG33 24 P 3.3-V regulator output
PTC 25 — Test pin connect to VSS
FUSE 26 O Fuse drive
VCC 27 P Power supply voltage
GPOD 28 I/OD High voltage general purpose I/O
PACK 29 P Alternate power source
DSG 30 O Charge N-FET gate drive

bq30z554-R1
PINOUT DIAGRAM
CHG 1 30 DSG
BAT 2 29 PACK
VC1 3 28 GPOD
VC2 4 27 VCC
VC3 5 26 FUSE
VC4 6 25 PTC
VSS 7 24 REG33
TS1 8 23 VSS
SRP 9 22 REG25
SRN 10 21 RBI
TS2 11 20 NC
PRES
¯¯¯¯¯ 12 19 NC
SMBD 13 18 NC
NC 14 17 NC
SMBC 15 16 GPIO
Figure 2. bq30z554-R1 Pinout Diagram
PIN EQUIVALENT DIAGRAMS

Power FET Drive GPOD
BAT
GPOD
CHG
Charge Pump
VCC
DSG
Charge Pump
PACK
Figure 3. Pin Equivalent Diagram 1

bq30z554-R1
SMB Power Supply
SMBC BAT
SBS
Engine FUSE,
VCC PTC
SMBD
CHG Charge
Pump
1MΩ 1MΩ
REG33 Regulator
REG25 Regulator
Thermistor input
REG25
PTC
PTC
18kΩ
80Ω
TSx ADC
FUSE PACK
DSG
PACK Charge-
pump
BAT
FUSE

bq30z554-R1
V1, V2, V3, V4 PRES
V1, V2,
ADC MUX
V3, V4 REG25
880kΩ
PRES
180kΩ
Cell Balancing
SRN, SRP
V4
SRN SC, OL
comparator
V3 Coulomb
SRP Counter
V2
RBI
REG25
RBI
V1
VSS

bq30z554-R1
ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted) (1)
DESCRIPTION PINS VALUE
Supply voltage range, VMAX VCC, PTC, PACK w.r.t. Vss –0.3 V to 34 V
VVC2 – 0.3 V to VVC2 + 8.5 or 34 V, whichever is
VC1, BAT
lower
VC2 VVC3 – 0.3 V to VVC3 + 8.5 V
VC3 VVC4 – 0.3 V to VVC4 + 8.5 V
Input voltage range, VIN
VC4 VSRP– 0.3 V to VSRP + 8.5 V
SRP, SRN –0.3 V to 0.3 V
SMBC, SMBD VSS – 0.3 V to 6.0 V
TS1, TS2, PRES, GPIO –0.3 V to VREG25 + 0.3 V
–0.3 V to VPACK + 20 V or VSS + 34 V, whichever
DSG
is lower
–0.3 V to VBAT + 20 V or VSS+ 34 V, whichever
CHG
is lower
Output voltage range, VO
GPOD, FUSE –0.3 V to 34 V
RBI, REG25 –0.3 V to 2.75 V
REG33 –0.3 V to 5.0 V
Maximum VSS current, ISS 50 mA
Current for cell balancing, ICB 10 mA
ESD Rating HBM, VCx Only 1 kV
Functional Temperature, TFUNC –40 to 110 °C
Storage temperature range, TSTG –65 to 150 °C
Lead temperature (soldering, 10 s), TSOLDER 300 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS

Typical values stated where TA = 25 °C and VCC = 14.4 V, Min/Max values stated where TA = –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted)
MIN TYP MAX UNIT
VCC, PACK 25 V
Supply voltage
BAT 3.8 VVC2 + 5.0
VSTARTUP Start up voltage at PACK 3.0 5.5 V
VC1, BAT VVC2 VVC2 + 5.0
VC2 VVC3 VVC3 + 5.0
VC3 VVC4 VVC4 + 5.0
V
VC4 VSRP VSRP + 5.0
VIN Input voltage range
VCn – VC(n+1), (n=1, 2, 3, 4) 0 5.0
PACK 25
PTC 0 2 V
SRP to SRN –0.2 0.2 V
CREG33 External 3.3-V REG capacitor 1 µF
CREG25 External 2.5-V REG capacitor 1 µF
TOPR Operating temperature –40 85 °C

bq30z554-R1
ELECTRICAL CHARACTERISTICS: Supply Current

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Normal CHG on, DSG on, no Flash write 410 µA
Sleep CHG off, DSG on, no SBS 129 µA
Communication
CHG off, DSG off, no SBS 83 µA
Communication
Shutdown 1 µA
ELECTRICAL CHARACTERISTICS: Power On Reset (POR)

VIT– Negative-going voltage input At REG25 1.9 2.0 2.1 V
VHYS POR Hysteresis At REG25 65 125 165 mV
ELECTRICAL CHARACTERISTICS: WAKE FROM SLEEP

VWAKE = 1.2 mV 0.2 1.2 2.0 mV
VWAKE = 2.4 mV 0.4 2.4 3.6
VWAKE VWAKE Threshold
VWAKE = 5 mV 2.0 5.0 6.8
VWAKE = 10 mV 5.3 10 13
Temperature drift of VWAKE
VWAKE_TCO 0.5 %/°C
accuracy
Time from application of current
tWAKE 0.2 1 ms
and wake of bq30z554-R1
ELECTRICAL CHARACTERISTICS: RBI RAM Backup

VRB > V(RB)MIN, VCC < VIT 20 1100 nA
I(RBI) RBI data-retention input current VRB > V(RB)MIN, VCC < VIT,
500
TA = 0 °C to 70 °C
V(RBI) RBI data-retention voltage 1 V
ELECTRICAL CHARACTERISTICS: 3.3-V Regulator

3.8 V < VCC or BAT ≤ 5 V,
2.4 3.5 V
ICC ≤4 mA
5 V < VCC or BAT ≤ 6.8 V,
VREG33 Regulator output voltage 3.1 3.3 3.5 V
ICC ≤13 mA
6.8 V < VCC or BAT ≤ 20 V,
3.1 3.3 3.5 V
ICC ≤ 30 mA
IREG33 Regulator Output Current 2 mA

bq30z554-R1
ELECTRICAL CHARACTERISTICS: 3.3-V Regulator (continued)

Regulator output change with VCC or BAT = 14.4 V,
V(VDDTEMP) 0.2 %
temperature IREG33 = 2 mA
VCC or BAT = 14.4 V,
ΔV(VDDLINE) Line regulation 1 13 mV
IREG33 = 2 mA
ΔV(VDDLOAD) Load regulation 5 18 mV
IREG33 = 2 mA
70 mA
REG33 = 3 V
I(REG33MAX) Current limit
33
REG33 = 0 V
ELECTRICAL CHARACTERISTICS: 2.5-V Regulator

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted
VREG25 Regulator output voltage 2.35 2.5 2.55 V
IREG25 = 10 mA
IREG25 Regulator Output Current 3 mA
Regulator output change with VCC or BAT = 14.4 V,
ΔV(VDDTEMP) 0.25 %
temperature IREG25 = 2 mA
ΔV(VDDLINE) Line regulation 1 4 mV
IREG25 = 2 mA
ΔV(VDDLOAD) Load regulation 20 40 mV
IREG25 = 2 mA
65 mA
REG25 = 2.3 V
I(REG33MAX) Current limit
23
REG25 = 0 V
ELECTRICAL CHARACTERISTICS: PRES, SMBD, SMBC, GPIO

VIH High-level input PRES, SMBD, SMBC, GPIO 2.0 V
PRES, SMBD, SMBC, GPIO
VIL Low-level input 0.8 V
IL = –0.5 mA
VOL Low-level output voltage SMBD, SMBC, GPIO, IL = 7 mA 0.4 V
CIN Input capacitance PRES, SMBD, SMBC, GPIO 5 pF
ILKG Input leakage current PRES, SMBD, SMBC, GPIO 1 μA
IWPU Weak Pull Up Current PRES, GPIO, VOH = VREG25 – 0.5 V 60 120 μA
RPD(SMBx) SMBC, SMBD Pull-Down TA = –40 ˚C to 100 ˚C 550 775 1000 kΩ

bq30z554-R1
ELECTRICAL CHARACTERISTICS: CHG, DSG FET Drive

VO(FETONDSG) = V(DSG) – VPACK,
VGS connect 10 MΩ, VCC 3.8 V to 8.0 9.7 12 V
8.4 V
VO(FETONDSG) = V(DSG) – VPACK,
Output voltage, charge, and 9.0 11 12 V
V(FETON) VGS connect 10 MΩ, VCC > 8.4 V
discharge FETs on
VO(FETONCHG) = V(CHG) – VBAT, VGS
8.0 9.7 12 V
connect 10 MΩ, VCC 3.8 V to 8.4 V
VO(FETONCHG) = V(CHG) – VBAT, VGS
9.0 11 12 V
connect 10 MΩ, VCC > 8.4 V
Output voltage, charge and VO(FETOFFDSG) = V(DSG) – VPACK –0.4 0.4 V
V(FETOFF)
discharge FETs off VO(FETOFFCHG) = V(CHG) – VBAT –0.4 0.4 V
CL = 4700 pF
RG= 5.1 kΩ
VCC <8.4 800 1400 μs
VDSG: VBAT to VBAT + 4 V,
VCHG: VPACK to VPACK + 4 V
tr Rise time
CL = 4700 pF
RG= 5.1 kΩ
VCC >8.4 200 500 μs
VDSG: VBAT to VBAT + 4 V,
VCHG: VPACK to VPACK + 4 V
CL = 4700 pF
RG= 5.1 kΩ
VDSG: VBAT+ VO(FETONDSG) to VBAT +
tf Fall time 80 200 μs
1V
VCHG: VPACK + VO(FETONCHG) to
VPACK + 1 V
ELECTRICAL CHARACTERISTICS: GPOD

VPU_GPOD GPOD Pull Up Voltage VCC V
VOL_GPOD GPOD Output Voltage Low IOL = 1 mA 0.3 V
ELECTRICAL CHARACTERISTICS: FUSE

VCC = 3.8 V to 9 V 2.4 8.5 V
VOH(FUSE) High Level FUSE Output
VCC = 9 V to 25 V 7 8 9 V
2.8 V
VIH(FUSE) Ensured by design. Not production
Weak Pull Up Current in off state 100 nA
tested.
CL = 1 nF, VCC = 9 V to 25V,
tR(FUSE) FUSE Output Rise Time 5 20 μs
VOH(FUSE) = 0 V to 5 V
ZO(FUSE) FUSE Output Impedance 2 5 kΩ

bq30z554-R1
ELECTRICAL CHARACTERISTICS: PTC Thermistor Support

VPTC = 0 to 2 V,
RPTC PTC
TA = –40 °C to 110 °C 1.3 2 2.7 MΩ
VPTC = 0 to 2 V
IO(PTC) PTC
TA = –40 °C to 110 °C –450 –370 –230 nA
tPTC PTC Blanking Delay TA = –40 °C to 110 °C 60 80 110 ms
ELECTRICAL CHARACTERISTICS: COULOMB COUNTER

Input voltage range SRP – SRN –0.20 0.25 V
Conversion time Single conversion 250 ms
Resolution (no missing codes) 16 bits
Effective resolution Single conversion, signed 15 bits
VIN Offset error Post Calibrated 10 µV
Offset error drift 0.3 0.5 µV/°C
Full-scale error –0.8% 0.2% 0.8%
Full-scale error drift 150 PPM/°C
Effective input resistance 2.5 MΩ
ELECTRICAL CHARACTERISTICS: VC1, VC2, VC3, VC4

VC4 – VC3, VC3 – VC2, VC2 –
Input voltage range –0.20 8 V
VC1, VC1 – VSS
VIN Conversion time Single conversion 32 ms
Resolution (no missing codes) 16 bits
Effective resolution Single conversion, signed 15 bits
RDS(ON) for internal FET at VDS > VDS = VC4 – VC3, VC3 – VC2,
200 310 430 Ω
2V VC2 – VC1, VC1 – VSS
R(BAL)
RDS(ON) for internal FET at VDS > VDS = VC4 – VC3, VC3 – VC2,
60 125 230 Ω
4V VC2 – VC1, VC1 – VSS
ELECTRICAL CHARACTERISTICS: TS1, TS2

R Internal Pull Up Resistor 16.5 17.5 19.0 KΩ
Internal Pull Up Resistor Drift from
RDRIFT 200 PPM/°C
25 °C
RPAD Internal Pin Pad resistance 84 Ω

bq30z554-R1
ELECTRICAL CHARACTERISTICS: TS1, TS2 (continued)

0.8×VREG2
Input voltage range TS1 – VSS, TS2 – VSS –0.20 V
5
VIN Conversion Time 16 ms

Resolution (no missing codes) 16 Bits
Effective resolution 11 12 Bits
ELECTRICAL CHARACTERISTICS: Internal Temperature Sensor

Temperature sensor voltage –1.9 –2.0 –2.1 mV/°C
Conversion Time 16 ms
V(TEMP)
Resolution (no missing codes) 16 Bits
Effective resolution 11 12 Bits
ELECTRICAL CHARACTERISTICS: Internal Thermal Shutdown

TMAX Maximum REG33 temperature 125 175
TRECOVER Recovery hysteresis temperature 10 °C
tPROTECT Protection time 5 µs
ELECTRICAL CHARACTERISTICS: High Frequency Oscillator

f(OSC) Operating frequency of CPU Clock 4.194 MHz
TA = –20 °C to 70 °C –2% ±0.25% 2%
f(EIO) Frequency error (1) (2)
TA = –40 °C to 85 °C –3% ±0.25% 3%
(3)
t(SXO) Start-up time TA = –25 °C to 85 °C 3 6 ms
(1) The frequency error is measured from 4.194 MHz.

(2) The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.
ELECTRICAL CHARACTERISTICS: Low Frequency Oscillator

f(LOSC) Operating frequency 32.768 kHz
TA = –20 °C to 70 °C –1.5% ±0.25% 1.5%
f(LEIO) Frequency error (1) (2)
TA = –40 °C to 85 °C –2.5% ±0.25% 2.5%
t(LSXO) Start-up time (3) TA = –25 °C to 85 °C 100 μs
(1) The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25 °C.
(2) The frequency error is measured from 32.768 kHz.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3 %.

bq30z554-R1
ELECTRICAL CHARACTERISTICS: Internal Voltage Reference

VREF Internal Reference Voltage 1.215 1.225 1.230 V
TA = –25 °C to 85 °C ±80 PPM/°C
VREF_DRIFT Internal Reference Voltage Drift
TA = 0 °C to 60 °C ±50 PPM/°C
ELECTRICAL CHARACTERISTICS: Flash

PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Data Flash 20k Cycles
Flash programming write-cycles
Instruction Flash 1k Cycles
ICC(PROG_DF) Data Flash-write supply current TA = –40°C to 85°C 3 4 mA
ICC(ERASE_DF) Data Flash-erase supply current TA = –40°C to 85°C 3 18 mA
(1) Assured by design. Not production tested.
ELECTRICAL CHARACTERISTICS: OCD Current Protection

OCD detection threshold voltage RSNS = 0 50 200 mV
V(OCD)
range, typical RSNS = 1 25 100 mV
OCD detection threshold voltage RSNS = 0 10 mV
ΔV(OCDT)
program step RSNS = 1 5 mV
V(OFFSET) OCD offset –10 10 mV
V(Scale_Err) OCD scale error –10 10 %
t(OCDD) Overcurrent in Discharge Delay 1 31 ms
t(OCDD_STEP) OCDD Step options 2 ms
VSRP – SRN = VTHRESH +
t(DETECT) Current fault detect time 160 µs
12.5 mV
Overcurrent and Short Circuit
tACC Accuracy of typical delay time –20 20 %
delay time accuracy
ELECTRICAL CHARACTERISTICS: SCD1 Current Protection

SCD1 detection threshold voltage RSNS = 0 100 450 mV
V(SDC1)
SCD1 detection threshold voltage RSNS = 0 50 mV
ΔV(SCD1T)
V(OFFSET) SCD1 offset –10 10 mV
V(Scale_Err) SCD1 scale error –10 10 %
AFE.STATE_CNTL[SCDDx2] = 0 0 915 µs
t(SCD1D) Short Circuit in Discharge Delay
AFE.STATE_CNTL[SCDDx2] = 0 61 µs
t(SCD1D_STEP) SCD1D Step options

bq30z554-R1
ELECTRICAL CHARACTERISTICS: SCD1 Current Protection (continued)

t(DETECT) Current fault detect time VSRP-SRN = VTHRESH + 12.5 mV 160 µs
delay time accuracy
ELECTRICAL CHARACTERISTICS: SCD2 Current Protection

SCD2 detection threshold voltage RSNS = 0 100 450 mV
V(SDC2)
SCD2 detection threshold voltage RSNS = 0 50 mV
ΔV(SCD2T)
V(OFFSET) SCD2 offset –10 10 mV
V(Scale_Err) SCD2 scale error –10 10 %
t(SCD1D) Short Circuit in Discharge Delay
AFE.STATE_CNTL[SCDDx2] = 0 30.5 µs
t(SCD2D_STEP) SCD2D Step options
12.5 mV
delay time accuracy
ELECTRICAL CHARACTERISTICS: SCC Current Protection

SCC detection threshold voltage RSNS = 0 –100 –300 mV
V(SCCT)
range, typical RSNS = 1 –50 –225 mV
SCC detection threshold voltage RSNS = 0 –50 mV
ΔV(SCCDT)
program step RSNS = 1 –25 mV
V(OFFSET) SCC offset –10 10 mV
V(Scale_Err) SCC scale error –10 10 %
t(SCCD) Short Circuit in Charge Delay 0 915 ms
t(SCCD_STEP) SCCD Step options 61 ms
12.5 mV
delay time accuracy
ELECTRICAL CHARACTERISTICS: SBS Timing Characteristics

SLAVE mode, SMBC 50% duty
fSMB SMBus operating frequency 10 100 kHz
cycle
MASTER mode, no clock low slave
fMAS SMBus master clock frequency 51.2 kHz
extend

bq30z554-R1
ELECTRICAL CHARACTERISTICS: SBS Timing Characteristics (continued)

Bus free time between start and
tBUF 4.7 µs
stop
tHD:STA Hold time after (repeated) start 4.0 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4.0 µs
tHD:DAT Data hold time 300 ns
tSU:DAT Data setup time 250 ns
(1)
tTIMEOUT Error signal/detect See 25 35 ms
tLOW Clock low period 4.7 µs
(2)
tHIGH Clock high period See Disabled
(2)
tHIGH Clock high period See 4.0 50 µs
Cumulative clock low slave extend (3)
tLOW:SEXT See 25 ms
time
Cumulative clock low master (4)
tLOW:MEXT See 10 ms
extend time
(5)
tF Clock/data fall time See 300 ns
(6)
tR Clock/data rise time See 1000 ns
(1) The bq30z554-R1 times out when any clock low exceeds tTIMEOUT.
(2) tHIGH, Max, is the minimum bus idle time. SMBC = 1 for t > 50 µs causes reset of any transaction involving bq30z554-R1 in progress.
This specification is valid when the THIGH_VAL = 0. If THIGH_VAL = 1 then the value of THIGH is set by THIGH_1,2 and the timeout is
not SMBus standard.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tF = 0.9 VDD to (VILMAX – 0.15)
ELECTRICAL CHARACTERISTICS: SBS XL Timing Characteristics

fSMBXL SMBus XL operating frequency SLAVE mode 40 400 kHz
Bus free time between start and
tBUF 4.7 µs
stop
tHD:STA Hold time after (repeated) start 4.0 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4.0 µs
(1)
tTIMEOUT Error signal/detect See 5 20 ms
tLOW Clock low period 20 µs
(2)
tHIGH Clock high period See 20 µs
(1) The bq30z554-R1 times out when any clock low exceeds tTIMEOUT.
(2) tHIGH, Max, is the minimum bus idle time.

bq30z554-R1
tR tF tF tR
tSU(STOP) T(BUF) tDH(STA)
tW(H)
SMBC SMBC tW(L)
SMBD SMBD
P S tHD(DATA) tSU(DATA)
tSU(STA)
t(TIMEOUT)
SMBC SMBC
SMBD SMBD
S
Figure 6. SMBus Timing Diagram

bq30z554-R1
FEATURE SET
Protections Safety Features

The bq30z554-R1 supports a wide range of battery and system protection features that can easily be configured.
The Protections safety features include:
• Cell Undervoltage Protection
• Cell Undervoltage I*R Compensated Protection
• Cell Overvoltage Protection
• Overcurrent in Charge Protection 1 and 2
• Overcurrent in Discharge Protection 1 and 2
• Overload in Discharge Protection
• Short Circuit in Charge Protection
• Short Circuit in Discharge Protection 1 and 2
• Overtemperature in Charge Protection
• Overtemperature in Discharge Protection
• Overtemperature FET protection
• SBS Host Watchdog Protection
• Precharge Timeout Protection
• Fast Charge Timeout Protection
• Overcharge Protection
• Overcharging Current Protection
• Overcharging Voltage Protection
Permanent Fail Safety Features

The FUSE pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. Upon a Permanent Fail event trigger, critical system information is written to non-volatile memory to
simplify failure analysis. In addition, the black box stores the sequence of safety events also into non-volatile
memory to simplify failure analysis. The Permanent Fail safety features include:
• Cell Undervoltage Protection
• Cell Overvoltage Protection
• Copper Deposition
• Overtemperature Cell
• Overtemperature FET
• QMAX Imbalance
• Cell Balancing
• Capacity Degradation
• Impedance
• Voltage Imbalance at Rest
• Voltage Imbalance Active
• Charge FET and Discharge FET
• Thermistor
• Chemical FUSE
• AFE Register
• AFE Communication
• 2nd-Level Protection
• PTC
• Instruction Flash
• Open Cell Tab Connection
• Data Flash

bq30z554-R1
Charge Control Features

The bq30z554-R1 Charge Control features include:
• Supports JEITA temperature ranges T1, T2, T3, T4, T5, T6. Reports charging voltage and charging current,
according to the active temperature range.
• Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-
ranges, and allows for varying the charging current according to the cell voltage.
• Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
• Determines the chemical state of charge of each battery cell using Impedance Track and can reduce the
charge difference of the battery cells in a fully charged state of the battery pack, gradually using the cell
balancing algorithm during rest and charging. This prevents fully charged cells from overcharging and causing
excessive degradation, and also increases the usable pack energy by preventing premature charge
termination.
• Supports precharging/zero-volt charging
• Supports charge inhibit and charge suspend if the battery pack temperature is out of temperature range.
• Reports charging fault and also indicates charge status via charge and discharge alarms.
Gas Gauging
The bq30z554-R1 uses the Impedance Track technology to measure and calculate the available charge in
battery cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full
charge or discharge learning cycle required. See the Theory and Implementation of Impedance Track Battery
Fuel-Gauging Algorithm application report (SLUA364B) for further details.
Lifetime Data Logging Features

The bq30z554-R1 offers extended lifetime data logging where important measurements are stored for warranty
and analysis purposes. The data monitored includes lifetime:
• Maximum cell voltage cell0, cell1, cell2, cell3
• Minimum cell voltage cell0, cell1, cell2, cell3
• Maximum cell voltage delta
• Maximum charge and discharge current
• Maximum average discharge current
• Maximum average discharge power
• Maximum cell temperature
• Minimum cell temperature
• Maximum cell temperature delta
• Maximum device temperature
• Minimum device temperature
• Maximum FET temperature
• Total accumulated safety events and last safety event in term of charging cycle
• Total accumulated charging events and charging events
• Total accumulated gauging events and gauging events
• Total accumulated cell balancing time cell0, cell1, cell2, cell3
• Total device firmware runtime
• Accumulated runtime in JEITA undertemperature range
• Accumulated runtime in JEITA low temperature range
• Accumulated runtime in JEITA standard temperature range
• Accumulated runtime in JEITA recommended temperature range
• Accumulated runtime in JEITA high temperature range
• Accumulated runtime in JEITA overtemperature range

bq30z554-R1
Authentication
• The bq30z554-R1 supports authentication by the host using SHA-1.
• SHA-1 authentication by the gas gauge is required for unsealing and full access.
Power Modes
The bq30z554-R1 supports five power modes to reduce power consumption:
• In NORMAL mode, the bq30z554-R1 performs measurements, calculations, protection decisions, and data
updates in 0.25-s intervals. Between these intervals, the bq30z554-R1 is in a reduced power stage. In
addition, the device will provide information for peak TURBO mode power operation.
• The bq30z554-R1 supports a TURBO mode operation by providing information to the host MCU about the
battery pack's ability to deliver peak power. The method of operation is based on the host MCU reading
register 0x59 (TURBO_POWER) to determine if the selected power level for TURBO mode operation of the
MCU is below the max power reported by the gas gauge. Additionally, the device reports current information
during the power pulse by reading register 0x5E (TURBO_CURRENT). The information reported by these two
registers allows the MCU to determine if the selected TURBO mode operation is safe and will not cause any
system reset due to transient power pulses.
• In SLEEP mode, the bq30z554-R1 performs measurements, calculations, protection decisions, and data
updates in adjustable time intervals. Between these intervals, the bq30z554-R1 is in a reduced power stage.
The bq30z554-R1 has a wake function that enables exit from SLEEP mode when current flow or failure is
detected.
• In SHUTDOWN mode, the bq30z554-R1 is completely disabled.
• In SHIP mode, the bq30z554-R1 enters a low-power mode with no voltage, current, and temperature
measurements, the FETs are turned off, and the MCU is in a halt state. The device wakes up upon SMBus
communication detection.
NOTE
For a detailed description of the SBS Commands and Data Flash (DF) Registers, refer to
the bq30z554-R1 Technical Reference Manual (SLUUA79).
Configuration
System Present Operation

The bq30z554-R1 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external
system, the bq30z554-R1 detects this as system present.
Battery Power Interrupt Operation

The bq30z554-R1 can interrupt the battery power by using an external push-button switch and detecting a low-
level threshold signal on the GPIO terminal (pin should be configured with an internal pull-up). Once the push
button is pressed, there is a delay of 1 s (default) for debounce to detect the low-level threshold. There is also a
data flash command for the battery power interrupt timeout. The default value is 30 minutes. If the push-button
switch is selected before this timeout, the battery power is restored based on this action.
Timeout Configuration
The timeout feature allows the battery power to be restored once the timer expires. Alternatively, if the value is
set to 0, this feature is disabled.
Subclass
Class Subclass Offset Name Type Min Max Default Unit
ID
Power 248 Power Off 0 Timeout U2 0 65535 30 min

bq30z554-R1
BATTERY PARAMETER MEASUREMENTS
Charge and Discharge Counting

The bq30z554-R1 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement,
and a second delta-sigma ADC for individual cell and battery voltage and temperature measurements.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from –0.25 V to 0.25 V. The bq30z554-R1 detects charge activity when VSR = V(SRP) – V(SRN) is positive,
and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq30z554-R1 continuously integrates the
signal over time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
Voltage
The bq30z554-R1 updates the individual series cell voltages at 0.25-s intervals. The internal ADC of the
bq30z554-R1 measures the voltage, and scales and calibrates it appropriately. This data is also used to
calculate the impedance of the cell for the Impedance Track gas gauging.
Current
The bq30z554-R1 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 5-mΩ to 20-mΩ typ. sense resistor.
Auto Calibration
The bq30z554-R1 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq30z554-R1 performs auto-calibration when the SMBus lines
stay low continuously for a minimum of 5 s.
Temperature
The bq30z554-R1 has an internal temperature sensor and inputs for four external temperature sensors. All five
temperature sensor options are enabled individually and configured for cell or FET temperature. Two
configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET
temperature, which may be of a higher temperature type.
CELL BALANCING
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device
internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time.
Higher cell balance current can be achieved by using an external cell balancing circuit. In EXTERNAL CELL
BALANCING mode, only one cell at a time can be balanced.
The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.

bq30z554-R1
Internal Cell Balancing

When internal cell balancing is configured, the cell balance current is defined by the external resistor RVC at the
VCx input.
RVC
VC1
RVC
VC2
RVC VC3
RVC
VC4
VSS
External Cell Balancing

When internal cell balancing is configured, the cell balance current is defined by RB. Only one cell at a time can
be balanced.
RVC
VC1
RB
RVC
VC2
RB
RVC VC3
RB
RVC
VC4
RB
VSS

bq30z554-R1
bq30z554-R1 Application Schematic
Push Button Switch
Figure 7. bq30z554-R1 Schematic

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
BQ30Z554DBT-R1 ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ30Z554
BQ30Z554DBTR-R1 ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ30Z554
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ30Z554DBTR-R1 TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ30Z554DBTR-R1 TSSOP DBT 30 2000 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBT0030A SCALE 2.000
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.55 TYP
A 6.25
0.1 C
PIN 1 INDEX AREA
28X 0.5
30
1
2X
7.85 7.15
7.75
NOTE 3
15
16
30X 0.23
0.17
4.5 1.2 MAX
B
4.3 0.1 C A B
NOTE 4
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A 0.75
0 -8 0.50
DETAIL A
A 20
TYPICAL
4220214/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DBT0030A TSSOP - 1.2 mm max height
30X (1.5) SYMM
1 (R0.05) TYP
30X (0.3) 30
30X (0.5)
SYMM
15 16
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4220214/A 05/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBT0030A TSSOP - 1.2 mm max height
30X (1.5) SYMM

(R0.05) TYP
1
30X (0.3) 30
30X (0.5)
SYMM
15 16
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220214/A 05/2020
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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www.ti.com SLUSBD4 – OCTOBER 2013

2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links :bq30z554-R1

VC4 16-bit Lifetime SMBD

Figure 1. bq30z554-R1 Implementation

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links :bq30z554-R1

Figure 2. bq30z554-R1 Pinout Diagram

PIN EQUIVALENT DIAGRAMS

Figure 3. Pin Equivalent Diagram 1

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5

SMB Power Supply

Figure 4. Pin Equivalent Diagram 2

6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links :bq30z554-R1

V1, V2, V3, V4 PRES

Figure 5. Pin Equivalent Diagram 3

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links :bq30z554-R1

ELECTRICAL CHARACTERISTICS: Supply Current

ELECTRICAL CHARACTERISTICS: Power On Reset (POR)

ELECTRICAL CHARACTERISTICS: WAKE FROM SLEEP

ELECTRICAL CHARACTERISTICS: RBI RAM Backup

ELECTRICAL CHARACTERISTICS: 3.3-V Regulator

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9

ELECTRICAL CHARACTERISTICS: 3.3-V Regulator (continued)

ELECTRICAL CHARACTERISTICS: 2.5-V Regulator

ELECTRICAL CHARACTERISTICS: PRES, SMBD, SMBC, GPIO

10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links :bq30z554-R1

ELECTRICAL CHARACTERISTICS: CHG, DSG FET Drive

ELECTRICAL CHARACTERISTICS: GPOD

ELECTRICAL CHARACTERISTICS: FUSE

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11

ELECTRICAL CHARACTERISTICS: PTC Thermistor Support

ELECTRICAL CHARACTERISTICS: COULOMB COUNTER

ELECTRICAL CHARACTERISTICS: VC1, VC2, VC3, VC4

ELECTRICAL CHARACTERISTICS: TS1, TS2

12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links :bq30z554-R1

ELECTRICAL CHARACTERISTICS: TS1, TS2 (continued)

VIN Conversion Time 16 ms

ELECTRICAL CHARACTERISTICS: Internal Temperature Sensor

ELECTRICAL CHARACTERISTICS: Internal Thermal Shutdown

ELECTRICAL CHARACTERISTICS: High Frequency Oscillator

(1) The frequency error is measured from 4.194 MHz.

ELECTRICAL CHARACTERISTICS: Low Frequency Oscillator

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 13

ELECTRICAL CHARACTERISTICS: Internal Voltage Reference

ELECTRICAL CHARACTERISTICS: Flash

(1) Assured by design. Not production tested.

ELECTRICAL CHARACTERISTICS: OCD Current Protection

ELECTRICAL CHARACTERISTICS: SCD1 Current Protection