Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 1/18

Tutorial-1
Low Noise Amplifier (LNA) Design
Complied by Rashad M. Ramzan

Objective:
Low noise amplifiers are one of the basic building blocks of any communication system.
The purpose of the LNA is to amplify the received signal to acceptable levels with
minimum self-generated additional noise. Gain, NF, non-linearity and impedance
matching are four most important parameters in LNA design.
The objective of this tutorial is to outline the basic tradeoffs between different amplifying
topologies w.r.t gain, NF and impedance matching. After this comparison it is concluded
that inductor degenerated common source topology gives the best performance to meet
the gain, NF, and impedance matching goals with minimum power consumption in case
of narrow band designs.
Goals:
After this tutorial, students should be able to
• Calculate the gain, input impedance and NF of common gate, common source,
and shunt feedback amplifiers.
• Understand the basic equations and tradeoff between different LNA topologies.
• Perform the calculation for inductor degenerated common source topology and
understand the tradeoff between the gain, NF, and impedance matching.
A supplement tutorial LNA lab is also part of this course which guides through
different analyses to design a practical LNA.

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 2/18

Problem-1.1(Tutorial)
NMOS transistor is racing horse in LNA design arena due to its higher mobility compared to
PMOS transistors. Calculate the IP3 of NMOS CS amplifier shown below. Assume that NMOS
transistor is in saturation.

a) Consider simplified square law model. (HW)

Kn
ID = (VGS − VT ) 2
2
b) Consider the short channel effects as:
K n  (VGS − VT ) 2 
ID =  
2 1 + θ (VGS − VT ) 
θ = Velocity Saturation, Mobility Degradation
VGS − VT = 0.2V and θ = 0.1V −1
Observe that this transistor is not a very “short channel” device as θ << 1.
c) What conclusion can be drawn from part b) about the bias current and transconductance
of the transistor for higher IP3?

Solution:

a). Homework answer: IP3 = ∞ VDD

b). RL

y ( x) = α 0 + α 1 x(t ) + α 2 x 2 (t ) + α 3 x 3 (t ) --------------(1) NMOS

x(t) VGS
4 α1
x(t ) = A cos ω 1 t + A cos ω 2 t ⇒ AIP 3 =
3 α3 DC-bias

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 3/18
K n (VGS − VT )
2

ID =
2 1 + θ (VGS − VT )
Here we assume a small signal x(t) around the bias (VGS – VT), so

K [(VGS − VT ) + x(t )]
2

ID = n
2 1 + θ (VGS − VT + x(t ))
we define VGS − VT = ∆V --------------- Bias voltage

K
ID = n
[x(t ) + ∆V ] 2

--------------------------------------------------------------(2)
2 θ ( x(t ) + ∆V ) + 1
K R ( x(t ) + ∆V )
2
K n RL
Vo = I D RL ⇒ Vo = n L and we put =K
2 1 + θ ( x(t ) + ∆V ) 2
1 ρ
θ << 1 so (x(t ) + ∆V ) is also small ⇒
1+ ρ
= 1−
2
1 θ ( x(t ) + ∆V )
≈1−
1 + θ ( x(t ) + ∆V ) 2
2 θ ( x(t ) + ∆V ) 
Vo = K ( x(t ) + ∆V ) 1 − 
 2 
3 Kθ
Vo = K ( x(t ) + ∆V ) − ( x(t ) + ∆V )
2

2
Kθ  3 Kθ 
V o = K ∆V 2 − ∆V 3 +  2 K ∆V − ∆V 2  x (t )
2  2 
 3 Kθ  Kθ 3 -----------------------------(3)
+K − ∆ V  x 2 (t ) − x (t )
 2  2

Comparing (1) & (3)

3 Kθ 3 Kθ Kθ
α1 = 2 K∆V − ∆V 2 , α 2 = K − ∆V , α3 = −
2 2 2
3
2 K∆v − Kθ∆V 2
4 α1 4 2 8  2∆V 
AIP 3 = = × =  − 3∆V 2 
3 α3 3 Kθ 3 θ 
2
8 2 ∆V 16 ∆V As θ << 1 3∆V can be ignored.
2
AIP 3 = =
3 θ 3 θ
Electrical Engineering Department (ISY), Linköping University
Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 4/18

16 ∆V 16 (VGS − VT )
AIP 3 = =
3 θ 3 θ -------------------------------(4)

Please, note that this formula only holds for small value of θ.

A large gate bias voltage (VGS – VT) improves IP3.

Put ∆V = 0.2V, θ = 0.1 V -1

16 0.2
AIP 3 = = 3.27Volts
3 0 .1
  3.27  2 1  

IIP3(dBm) = 10 log   .  1mW  ≅ 20dBm
  2  50  
  
K (VGS − VT )
2

c). From ID = n the NMOS transconductance can be found as

2 1 + θ (VGS − VT )
K n (VGS − VT )(2 + θ (VGS − VT ) )
gm =
2 (1 + θ (VGS − VT ))2 .

By comparison of those two formulas we find

ID 1 + θ (VGS − VT ) VGS − VT
= (VGS − VT ) × ≅
gm 2 + θ (VGS − VT ) 2
and hence, (4) can be rewritten as

32 I D
AIP 3 ≅
3θ g m
As shown, IIP3 is decided by the ratio ID/gm which is constant for a given gate bias voltage.
Using e.g. a wider transistor does not change this ratio and only the power consumption
is increased.

Problem-1.2 (Tutorial)
It is preferred in current RF designs that the input of LNA be matched to 50 Ω. The easiest way is
to shunt the gate with a resistor of 50 Ω.
a) Calculate the gain, input impedance and NF in absence of gate noise. Assume that Rsh=RL
for NF derivation.
b) What are the disadvantages of shunt resistor with reference to gain and NF?

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 5/18

Solution:
a). (Please read assumption in the problem statement carefully)
VDD
V 2 n , Rs Rs G D Vout RL
Rsh Rs Vout
V 2
n , Rsh
gmVgs i2d RL Vin
Rsh
S Zin
RL is noiseless (Biasing not shown)

Total output noise power

F=
Output noise due to input source

V 2 m , Rs = 4kTRs ∆f Gain Gate = − g m RL

 Rsh 
V 2 m ,Rsh = 4kTRsh ∆f A = g m RL   for Rsh = Rs
R
 s + R sh 

RL
i 2 d = 4kTγg m ∆f A = −gm
2
Using superposition, considering one at a time and shorting / opening other sources.
2
 Rsh 
= V n , Rs × g m RL ×  
2 2 2 2
V on , Rs
R
 s + R sh 

2
 Rs 
= V n , Rsh × g m RL ×  
2 2 2 2
V on , Rsh
R
 s + R sh 

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 6/18
V 2 no,d = i 2 d × R 2 L
V 2 on , Rs + V 2 on, Rsh + V 2 no ,d V 2 on , Rsh + V 2 o ,d
F= =1+
V 2 on , Rs V 2 on ,Rs
g 2 m R 2 L × R 2 sh
4kTRsh ∆f ×
(Rs + Rsh )2 4kTγg m ∆f × R 2 L
F =1+ +
g 2m R2L × R2s g 2m R2L × R2s
4kTRs ∆f × 4 kTR ∆f ×
(Rs + Rsh )2 S
(Rs + Rsh )2
In case of impedance match Rs = Rsh

R L2 γ g m R L2 γ g m 4γ
F = 1+1+ = 2 + = 2 +
g 2 R2 × R2 g 2 × R L2 g m Rs
Rs × m S 2 L Rs × m
4RS 4
b).
- Poor Noise Figure
- Input signal attenuated by voltage divider
- Rsh adds extra noise.
- At high frequency, shunt L is needed to tune out Cgs
- Reduced gain.

Problem-1.3 (Tutorial)
Another approach to get 50 Ω input impedance match is shunt feedback amplifier shown below.

a) Calculate the gain, input impedance and NF neglecting the gate noise. The gate-drain,
gate-bulk, and gate-source capacitance can be neglected as well.
b) What are the disadvantage of shunt feedback amplifier with reference to gain and NF?

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 7/18
Solution:
VDD
2
Rs V n , RF
RF Vout
RF RL
Rs Vout
V 2 n , Rs gmVgs I 2 nD RL
Vin
Zin

(Equivalent noise model ignoring gate noise), RL is noiseless (Biasing not shown)

I 2 nD = 4kTγg m ∆f ,V 2 RS = 4kTRS ∆f

V 2 n , out Total input noise power

F= =
A 2 v , tot V 2 RS Output noise power due to input source
Here Av,tot = Gain from Vin to Vout
Again using superposition theorem

+ Vn + Vn
2 2 2
V 2 n ,out Vn
F= =
RS , out RF , out D , out

A 2 v ,tot V 2 RS A 2 v ,tot V 2 RS

Gain Calculation
Vin = iin (RS + RF ) + Vout
Vout = (iin − g mVgs )RL Iin RF Vout

Rs
Vgs = iin RF + Vo Iin RL

Vout RL (1 − g m RL )
Av ,tot = =
Vin RS + RF + RL + g m RS RL
If RF>>RS & gmRF>>1
− g m RL iin Rs RF Vout
Av ,tot = ≅ − g m RL
RS 1 + g m RS
+ 1 + RL +
RF RF Vin Vgs gmVgs RL

Av ,tot ≅ − g m RL
RF + RL
Also Z in =
1 + g m RL
By ignoring Cgs, we have considered real part only.

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 8/18
For source resistance

V 2 nRS ,out = A 2 v ,tot V 2 nRS ---------------(1)

For feedback resistance

2
i Rs RF V RF
V 2 RF ,out

Vgs gmVgs RL

Vgs = −iRS = iRF − VRF + VRF ,out

VRF ,out = RL (i − g mVgs )
1 RL
VRF ,out = VRF = VRF (1 + g m RS )
RS + R F RF
1+
RL (1 + g m Rs )
2
R 
V 2
n , RF ,out = V n , RF  L (1 + g m RS )
2
---------------------(2)
 RF 
Similarly

i Rs RF V 2 nD ,out

Vgs gmVgs I 2 n,D RL

VnD ,out VnD ,out

+ I nD + g mVgs + =0
RL RS + R F
VnD ,out
Vgs = RS
RS + R F
I n,D
VnD ,out = ≈ I nD RL
1 1 g R
+ + m S
R L RS + R F RS + R F
So,

V 2 nD ,out = I 2 nD RL
2
------------------------------------------(3)
Combaining (1) (2) & (3)

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 9/18
2
R 
V 2 n , RF  L (1 + g m R S )
 RF  I 2 nD R 2 L
F = 1+ +
A 2 v ,tot V 2 n , RS A 2 v ,tot V 2 n , RS

Av ,tot = − g m RL , V 2 n , RS = 4kTRS ∆f , V 2 M ,RF = 4kTRF & I 2 nD = 4kTγg m

2
R  1  γ
F = 1+ S 1 +  +
RF  g m RS  g m RS

b).
NF ↓ gmRS ↑ & RF ↑ usually RS = 50Ω
- Better performance than CS amplifier
- RF induces noise

- At higher f ↑ a shunt inductor needed to tune out Cgs

- Broadband Amp @ Lower frequency

- To make NF ↓ RF > RS and gmRS >> 1

Problem-1.4 (HW)
Common gate amplifier also offers 50 Ω input impedance match and solves the input matching
problem.

c) Calculate the gain, input impedance and NF in absence of gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
a) What are the disadvantage of common gate amplifier with reference to gain and NF?

Problem-1.5 (Tutorial)
The disadvantages of the amplifiers discussed in Problem-2, 3 & 4 can be circumvented by using
the source degenerated LNA shown below.

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 10/18

a) Calculate the input impedance. This inductor source degenerated amplifier presents a
noiseless resistance for 50Ω for input power match. How we can cancel the imaginary
part of complex input impedance so that the LNA presents 50Ω real input resistance at
input port.
b) Calculate the NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to
source capacitance.
c) Cgd bridges the input and output ports. The reverse isolation of this LNA is very poor.
Why reverse isolation is important? Suggest the modification to improve reverse
isolation.

Solution:
a).
VDD
Rs Lg iin io Vout
VS
RL
gmVgs Vout
Rs Lg
Zin Vin VS
Vgs Ls
Ls

(Biasing not shown)

From model above we can write

 1 
Vin = iin ( jωLg + jωLs ) + iin   + io jωLs ---------------(1)
 jωc 
1
io = g mVgs = g m iin × --------------------------------------(2)
jωC gs
Substituting (2) in (1)
 g L 
Vin = iin  jω (Lg + Ls ) +
1
+ m s
 jωC gs C gs 

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 11/18

= jω (Lg + Ls ) +
Vin 1 g L
Z in = + m s
iin jωC gs C gs

Z in = jω (Lg + Ls ) +
1 g L
+ m s
jωC gs C gs
For matching Lg + Ls are canceled out by Cgs. So at frequency of interest

ωo (Lg + Ls ) =
1 1
⇒ ωo =
2

ωo C gs (Lg + Ls )C gs
gm
And RS = 50Ω = Ls
C gs

Notes:
a). Ls is typically small and may be realized by the bond wire for source.
b). Lg can be implemented by spiral/external inductor.

b).
From part a) Reference:
For series RLC Circuit
Z in = jω (Lg + Ls ) +
1 g L
+ m s
jωC gs C gs R L

We can draw this circuit as Vin C VC

Rs Lg + Ls
Ls 1 L ωo L 1
gm Qs = = =
Vin Zin C gs Cgs Vgs R C R ωo RC
and VC = QSVin
Here
ω o (L g + L s ) ω o (L g + L s )
Q in = =
g m LS R S + ω T LS
RS +
C gs
gm
Q ωT ≅ frequency of current gain equal 1
C gs
1 g m LS
Qin = for match load RS =
 g m LS  C gs
ωo  RS + C gs

 C gs 

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 12/18
1
Qin =
2ω o Rs C gs

Gain
Vgs = QinVin Vout
Rs Lg
I
g m = out Vgs RL
V gs Vin Ls
Zin
I out V gs g m
Gm = = = Qin g m
V in V in
G m = Qin g m

V out
so, = −G m R L where Gm = Qin g m
Vin

Noise Figure:
Total noise power at output
F=
noise power at output due to input source
For this calculation we ignore channel noise.

V 2 nRS ,OUT + V 2 nD ,OUT V 2 nD ,OUT

F= =1+
V 2 nRS ,OUT V 2 nRS ,OUT
V 2 nD ,OUT = i 2 n ,D R 2 L i 2 n , D = 4kTγg m ∆f
V 2 nRS ,OUT = V 2 n ,RS G 2 m R 2 L V 2 n , RS = 4kTRS ∆f & Gm = Qin g m
i n2, D R L2
F = 1+ i 2 n , D = 4kTγg m , V 2 n , RS = 4kTRS
2 2 2 2
V n , RS Q g R
in m L

γ
F = 1+
g m R S Qin2

Notes:
- Very good NF value
- Narrow band matching
- NF ↓ with Q 2
- The Q is dependent upon Lg + Ls, Ls usually small so Q depends mainly upon Lg

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 13/18

C). Drawbacks
i).
VDD VDD

RL generates noise so replace

RL LD CL
RL with LD so that’s
Rs Lg Vout 1 Rs Lg
VS ωo = VS
LD C L
Ls Ls

The CL can be considered the input capacitance of the following mixer or filter.

VDD

ii).
LD CL
Reverse Isolation Cgd
Vb
Vout Rs Lg

Ls
Lo
(Final Design)

Reverse isolation depends upon capacitance between output and input.

To make it less the cascode architecture can be used.

Problem-1.6 (HW)
Fill-in the Table below, use the data from Problem-1.2, 1.4, 1.3 and 1.5

Type of LNA Zin Noise Factor Gain NF (dB)

Shunt Resistor Rsh 4γ − g m RL

2+
g m RS 2

Common Gate

Shunt Feedback

Source Degenerated

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 14/18

a) Calculate the NF for all above amplifiers. Assume γ=2, gm = 20mS, Rs = 50Ω, RF =
500Ω, and Qin = 2.
b) Which is the best topology for Narrow Band LNA design at high frequency?

Problem-1.7 (Tutorial)
Real Design: We will design the inductor-source-degenerated LNA shown in Fig below to meet
the specification outlined for IEEE802.11b standard. The first cut approximate values are
calculated as a starting point for simulation.

LNA Specification:
NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, Centre Frequency = 2.4 GHz
Load Capacitance = 1pF
Technology Parameters for 0.35um CMOS:
Leff = 0.35µ m, µ n Cox = 170 µ A V 2 , Cox = 4.6 mF m2 , µ p Cox = 58 µ A V 2 , γ = 2

δ = 4, C = 0.395, α = 0.85

Solution:
µ o Cox = 170 µA V 2 , µ p Cox = 58 µA V 2 , 
 
Technology 0.35µm CMOS:
Cox = 4.6 mF m , γ = 2, Leff = 0.35µm 
2

δ = 4, C = 0.395, α = 0.85
Design Parameters

NF < 2.5 dB, Gain > 15dB, IIP3 > -5dBm, f0 = 2.4 GHz

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 15/18

VDD
RREF LD

M3 M2
RBIAS Vout
Lg
M1
RS CB CL = 10pF
Vin Ls

Component Description
Ls – Matches input impedance
Lg – Sets the Resonant Frequency fO = 2.4 GHz
M3 – Biasing transistor which forms current mirror with M1
Ld – Tuned output increases the gain and also work as band pass filter with CL
M2 – Isolates tuned input from output to increase reverse isolation, also reduces the effect of
Miller capacitance Cgd
CB – BC blocking capacitor chosen to have negligible reactance at fO = 2.4 GHz
RBIAS – Large enough so that its equivalent current noise is small enough to be ignored. (Don’t
consider it as voltage noise source. Why??)

Design Procedure
Size of M1:
From the noisy two-port theory (see the course book or lecture notes) the optimal input matching
and minimum noise figure is given by:

Gopt = αω C gs
δ
5γ
(
1− C =
2 1
50Ω
) ----------------------(A)

Fmin = 1 +
2 ω
5 ωT
(
γC 1 − C
2
) = 1 + 2.3 ωω -------(B)
T

From (A)

C gs ≅ 2.7 pF ⇒ WM 1 ≈ 3C gs / 2COX Leff ≈ 2.5mm ( not feasible – huge size, huge

power ! )
Conclusion: We will not go for the global minimum noise figure. Instead, we will look into the
constraint power design approach.
Solution:
LNA NF will be optimized for given power which is higher than the global minimum NF.

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 16/18
In this case the optimum transistor width is given by:
1
Wopt =
3ωo Leff Cox RS
while the minimum power-constraint NF :
γ ω ω
Fmin, p = 1 + 2.4 ⇒ Fmin, p = 1 + 5.6 ---------------(C)
α ωT ωT
(B) is the global minimum noise figure.
(C) is the minimum NF for a given power consumption.
In practice the difference is usually 0.5dB to 1dB (no big deal for Lower Power)

Step - 1:
I1 = I 2 = 5mA (Limited Power consumption)
Step - 2:

1
WM 1 =
3ω 0 L eff C ox R S

 RS = 50Ω, Cox = 4.6 mF m 2 , 

1  
WM 1 = µ n Cox = 170 µA V , Leff = 0.35µm, 
3 × 0.35µ × 4.6m × 50 × ωo ω = 2πf , f = 2.4GHz 
 o o o 
WM 1 = 3.9 × 10 −4
WM 1 = 3.9 × 10 −4 = 390µm
Step - 3:
2
C gs1 = WM 1 Leff Cox
3
2
C gs1 = × 390µ × 0.35µ × 4.6m = 0.41 pF
3

W  2 I DM 1
g m1 = 2 µ n C ox   I DM 1 g m1 =
 L M1 or V GS − VT (for short channel model)

 390 
g m1 = 2 × 170µ ×   × 5m = 43 mA V
 0.35 

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 17/18
g m1 43 mA V
ωT ≈ = = 104G rad Sec
C gs1 0.41 pF
Assuming γ =2
ωo
Now Fmin = 1 + 5.6
ωT
2π 2.4G
Fmin = 1 + 5.6 ≈ 2.55dB
104G
NF ≈ 2.55dB
This NF is very close to the specified value. If we increase ID then ωT should increase slightly as
well and hence, a lower NF value can be achieved at expense of more power.
Step - 4:
Source and gate inductance such that they cancel Cgs and set 50Ω input impedance
ωo = 2πf o = 2π 2.4 = 15G rad Sec
From previous problem
g m LS
R S = RTransformed = ≅ ω T LS
C gs

RS 50
LS = = ≅ 0.5nH
ωT 100G
LS = 0.5nH can be implemented using the bond wire.
1
L + L =
Now
ω 02 C gs1
g s

1
Lg + Ls = = 10.81nH
(15G ) × 0.41 pF
2

Lg ≈ 10nH
Step - 5:
1
Ld = Q C L = 1 pF
ωo 2C L
1
Ld = ≅ 4.4nH
(15G ) × 1 pF
2

Ld = 4.4nH

Electrical Engineering Department (ISY), Linköping University

Spring 2010: Radio Frequency Integrated Circuits (TSEK03) 18/18
Step - 6:
Size of M3 is chosen to minimize power consumption

W M 3 = 70µm, R REF = 2kΩ ⇒ I 3 = 0.6mA

R BIAS = 2kΩ (Large enough so that it’s equivalent current noise can be neglected)

1
C B = 10 pF ( X C ≈ 6.6Ω so good value @ 2.4G XB = = 6.6Ω )
2πf o C B
Step - 7:
Size M2 = M3
So that they can have shared Drain Area..
(Note: You will simulate same LNA circuit in LAB # 2)

Electrical Engineering Department (ISY), Linköping University