DATASHEET

ISL9113 FN8313
Low Input Voltage and High Efficiency Synchronous Boost Converter with 1.3A Rev 3.00
Switch February 23, 2015

The ISL9113 provides a power supply solution for devices

powered by three-cell alkaline, NiCd, NiMH or one-cell
Features
Li-Ion/Li-Polymer batteries. It offers either a fixed 5V or an • Up to 95% efficiency at typical operating conditions
adjustable output option for USB-OTG or portable HDMI • Input voltage range: 0.8V to 4.7V
applications. The device is guaranteed to supply 500mA from
• Output current: Up to 500mA (VBAT = 3.0V, VOUT = 5.0V)
a 3V input and 5V output and has a typical 1.3A peak current
limit. High 1.8MHz switching frequency allows for the use of • Low quiescent current: 20μA (typical)
tiny, low-profile inductors and ceramic capacitors to minimize • Logic control shutdown (IQ < 1µA)
the size of the overall solution.
• Fixed 5V, 5.1V or adjustable output
The ISL9113 is an internally compensated, fully integrated
• 1.2V EN high logic
synchronous converter optimized for efficiency with minimal
external components. At light load, the device enters skip • Output disconnect during shutdown
mode and consumes only 20µA of quiescent current, resulting • Skip mode under light load condition
in higher efficiency at light loads and maximum battery life.
• Undervoltage lockout
The device is available in an 8 Ld DFN package and a 6 bump • Fault protection: OVP (ADJ version only), OTP, short circuit
WLCSP.
• 8 Ld 2mmx2mm DFN package and 6 bump
Related Literature 0.8mmx1.36mm WLCSP

• AN1816, “ISL9113ERAZ-EVZ, ISL9113ER7Z-EVZ Evaluation Applications

Board User Guide” • Products including portable HDMI and USB-OTG
• Smartphones
• Tablet and mobile internet devices

100
VBAT = 4.2V
95 VBAT = 3.6V
VBAT = 3.0V
2.2µH 90

85
EFFICIENCY (%)

8 VOUT =
5V/500mA 80
SW 2
VBAT = VOUT 75
0.8V TO 4.7V 7
VBAT 3 70 VBAT = 2.3V
NC
4.7µF 4.7µF VBAT = 1.2V
5
EN 65
1
PGND
60
VFAULT 1k 4 6
FAULT AGND 55
VOUT = 5.0V
50
0.0001 0.001 0.01 0.1 1
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION (ISL9113ER7Z) FIGURE 2. FIXED 5V EFFICIENCY (ISL9113ER7Z)

FN8313 Rev 3.00 Page 1 of 15

February 23, 2015
ISL9113

Block Diagrams
ISL9113ER7Z

C1

VBAT VOUT
C2

7 2

VINT VOLTAGE
UVLO
SELECTOR

START-UP N-WELL
SWITCH
SW L1
GATE
DRIVER
VOUT 8
OVP AND

ANTI-CROSS
CONDUCTION

SW
ZCD
VOUT
4

FAULT CURRENT
CONTROL LOGIC SENSE

DIGITAL
AND VOUT
SOFT-START
CURRENT SLOPE COMP
LIMIT

FAULT
EN 5 MONITORING
gm
OFF ON

VOLTAGE
CLAMP
VINT

1.8MHz THERMAL REFERENCE

OSCILLATOR SHUTDOWN GENERATOR

1 6

FN8313 Rev 3.00 Page 2 of 15

February 23, 2015
ISL9113

Block Diagrams (Continued)

ISL9113ERAZ

C1

VBAT VOUT
C2

7 2

VINT VOLTAGE
UVLO
SELECTOR

START-UP N-WELL
SWITCH
SW L1
GATE
DRIVER
VOUT 8
OVP AND

ANTI-CROSS
CONDUCTION

SW
EN ZCD
5 VOUT

OFF ON
CURRENT
CONTROL LOGIC SENSE

R1

DIGITAL
AND SOFT-START
CURRENT SLOPE COMP
LIMIT
FB

FAULT
4
MONITORING
gm

VOLTAGE R2
CLAMP
VINT

1.8MHz THERMAL REFERENCE

OSCILLATOR SHUTDOWN GENERATOR

1 6

FN8313 Rev 3.00 Page 3 of 15

February 23, 2015
ISL9113

Pin Configurations
FIXED OUTPUT ADJUSTABLE OUTPUT
(8 LD DFN) (8 LD DFN)
TOP VIEW TOP VIEW

PGND 1 8 SW PGND 1 8 SW

VOUT 2 7 VBAT VOUT 2 7 VBAT

NC 3 6 AGND NC 3 6 AGND

FAULT 4 5 EN FB 4 5 EN

FIXED OUTPUT ADJUSTABLE OUTPUT

(6 BUMP WLCSP) (6 BUMP WLCSP)
TOP VIEW TOP VIEW

SW A1 A2 PGND SW A1 A2 PGND

VBAT B1 B2 VOUT VBAT B1 B2 VOUT

EN C1 C2 FAULT EN C1 C2 FB

Pin Descriptions
8 LD DFN 6 BUMP WLCSP
PIN NUMBERS PIN NUMBERS
SYMBOL PIN DESCRIPTIONS
FIXED ADJUSTABLE FIXED ADJUSTABLE
OUTPUT OUTPUT OUTPUT OUTPUT

1 1 A2 A2 PGND Power ground

2 2 B2 B2 VOUT Device output

3 3 - - NC No connection

4 - C2 - FAULT Fault output; outputs logic LOW under a number of fault conditions (see
Table 1 on page 9).

- 4 - C2 FB Feedback pin of the converter. Connect voltage divider resistors between

VOUT, FB and GND for desired output.

5 5 C1 C1 EN The EN pin is an active-HIGH logic input for enabling the device. When
asserted HIGH, the boost function begins. When asserted LOW, the device
is completely disabled, and current is blocked from flowing from the SW pin
to the output and vice versa. This pin should be tied either HIGH to enable
the device, or LOW to disable the device.

6 6 - - AGND Analog ground

7 7 B1 B1 VBAT Device input supply from a battery. Connect a 4.7µF ceramic capacitor to
the power ground.

8 8 A1 A1 SW The SW pin is the switching node of the power converter. Connect one
terminal of the inductor to the SW pin and the other to power input.

- - EPAD The exposed pad (available only in the 8 Ld DFN package) must be
connected to PGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for
optimal thermal performance.

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ISL9113

Ordering Information
PART NUMBER PART VOUT TEMP RANGE PACKAGE PKG.
(Notes 1, 4) MARKING (V) (°C) (RoHS Compliant) DWG. #

ISL9113ER7Z-T (Note 2) 137 5.0 -20 to +85 8 Ld DFN L8.2x2D

ISL9113ERAZ-T (Note 2) 13A Adjustable -20 to +85 8 Ld DFN L8.2x2D

ISL9113EI9Z-T (Note 3) 139 5.1 -20 to +85 6 Bump WLCSP W3x2.6

ISL9113EIAZ-T (Note 3) 13A Adjustable -20 to +85 6 Bump WLCSP W3x2.6

ISL9113ER7Z-EVZ Evaluation Board for ISL9113ER7Z

ISL9113ERAZ-EVZ Evaluation Board for ISL9113ERAZ

ISL9113EI9Z-EVZ Evaluation Board for ISL9113EI9Z

ISL9113EIAZ-EVZ Evaluation Board for ISL9113EIAZ

NOTES:
1. Please refer to Tech Brief TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and
SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL9113. For more information on MSL please see Tech Brief TB363.

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ISL9113

Absolute Maximum Ratings Thermal Information

VBAT, EN, FAULT, VOUT, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
SW Voltage 8 Ld DFN Package (Notes 5, 6). . . . . . . . . . 80 15
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V 6 Bump WLCSP (Note 5) . . . . . . . . . . . . . . . 116 -
Pulse < 10ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 8.0V Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-20°C to +125°C
ESD Ratings Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
*Other ESD Spec should meet Level 1 requirement Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Latch-up (Tested per JESD78; Class 2, Level A) . . . . . . . . . . . . . . . . 100mA

Recommended Operating Conditions

VBAT (After Start-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 4.7V
VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VBAT + 0.2V) to 5.2V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VBAT = 3.0V, VOUT = 5.0V, TA = +25°C (see “Typical Application Circuit” on page 7). Boldface limits apply
across the operating temperature range, -20°C to +85°C.

MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS

Start-up Voltage VMIN VEN = 1.2V, RLOAD = 50Ω 2.8 3.0 V

Input Undervoltage Lockout VUVLO VEN = VBAT, RLOAD = 50Ω, DFN 0.68 0.70 0.76 V
versions only

Feedback Voltage VFB ADJ version only 784 800 816 mV

Output Voltage VOUT VBAT = 2.8V, ADJ version only 3.0 5.2 V

ILOAD = 50mA, 5V DFN Fixed version 4.9 5 5.1 V

ILOAD = 1mA or 50mA, 5.1V WLCSP 4.96 5.1 5.2 V

Fixed version

Feedback Pin Input Current VFB = 0.8V, ADJ version only 100 nA

Quiescent Current from VOUT IQ1 VBAT = VEN = 1.2V, No Load (Note 8) 20 45 μA
Shutdown Current from VBAT ISD VEN = 0V, VBAT = 1.2V, VO = 0 0.5 2 μA

Leakage Current at SW Pin VEN = 0V, VBAT = 4.7V, VO = 0 1 μA

N-Channel MOSFET ON-resistance 0.20 Ω

P-Channel MOSFET ON-resistance 0.35 Ω

N-Channel MOSFET Peak Current Limit IPK 1.1 1.3 1.5 A

Maximum Duty Cycle DMAX 85 87.5 %

PWM Switching Frequency FOSC DFN version 1.5 1.8 2.0 MHz

WLCSP version 1.7 1.8 2.2 MHz

EN Logic High 2.5V < VBAT < 4.7V 1.2 V

VBAT < 2.5V 0.48*VBAT V

EN Logic Low 2.5V < VBAT < 4.7V 0.35 V

VBAT < 2.5V 0.14*VBA V

T

Soft-Start-Up Time COUT = 4.7μF, L = 2.2μH 0.2 1 ms

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ISL9113

Electrical Specifications VBAT = 3.0V, VOUT = 5.0V, TA = +25°C (see “Typical Application Circuit” on page 7). Boldface limits apply
across the operating temperature range, -20°C to +85°C. (Continued)

MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS

FAULT Pin Leakage Current when High VFAULT = VOUT 100 nA

FAULT Pin Sink Current when Low VFAULT = 0.5V 10 mA

Load Regulation ΔVOUT/VOUT ILOAD = 0 to 100mA, DFN versions -1.5 +1.5 %

ILOAD = 0 to 100mA, WLCSP versions ±1.5 %

Line Regulation VBAT = 3.0V to 3.6V, ILOAD = 1mA -1.0 +1.0 %

Output Overvoltage Protection Threshold ADJ version only 5.9 V

Thermal Shutdown TSD 150 oC

Thermal Shutdown Hysteresis 25 oC

NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. IQ1 is measured at VOUT and multiplied by VOUT/VBAT; thus, the equivalent input quiescent current is calculated.

the inductor current ramps down until the next clock. At this
Typical Application Circuit point, following a short dead time, the N-channel MOSFET is
2.2µH again turned ON, repeating as previously described.

Skip Mode Operation

8 VOUT =
VBAT = SW 5.0V/500mA The boost converter is capable of operating in two different
0.8V TO 4.7V VOUT 2
7 VBAT
modes. When the inductor current is sensed to cross zero for
4.7µF
523k eight consecutive times, the converter enters skip mode. In skip
4.7µF
5 EN
FB 4 mode, each pulse cycle is still synchronized by the PWM clock.
The N-channel MOSFET is turned ON at the rising edge of the
100k
clock and turned OFF when the inductor peak current reaches
GND 1 typically 25% of the current limit. Then, the P-channel MOSFET is
ISL9113ERAZ
turned ON, and it stays ON until its current goes to zero.
FIGURE 3. POWER SUPPLY SOLUTION FOR VOUT = 5V Subsequently, both N-channel and P-channel MOSFETs are
turned OFF until the next clock cycle starts, at which time the
N-channel MOSFET is turned ON again. When VOUT is 1.5% higher
Detailed Description than the nominal output voltage, the N-channel MOSFET is
immediately turned OFF and the P-channel MOSFET is turned ON
Current Mode PWM Operation until the inductor current goes to zero. The N-channel MOSFET
The control scheme of the device is based on the peak current resumes operation when VFB falls back to its nominal value,
mode control and the control loop is compensated internally. The repeating the previous operation. The converter returns to
peak current of the N-channel MOSFET switch is sensed to limit 1.8MHz PWM mode operation when VFB drops 1.5% below its
the maximum current flowing through the switch and the nominal voltage.
inductor. The typical current limit is set to 1.3A. Given the skip mode algorithm incorporated in the ISL9113, the
The control circuit includes a ramp generator, slope average value of the output voltage is approximately 0.75%
compensator, error amplifier and a PWM comparator (see “Block higher than the nominal output voltage under PWM operation.
Diagrams” on pages 2 and 3). The ramp signal is derived from This positive offset improves the load transient response when
the inductor current. This ramp signal is then compared to the switching from skip mode to PWM mode operation. The ripple on
error amplifier output to generate the PWM gating signals for the output voltage is typically 1.5%*VOUT (nominal) when input
driving both N-channel and P-channel MOSFETs. The PWM voltage is sufficiently lower than output voltage, and it increases
operation is initialized by the clock from the internal oscillator as the input voltage approaches the output voltage.
(typical 1.8MHz). The N-channel MOSFET is turned ON at the
beginning of a PWM cycle, the P-channel MOSFET remains OFF Synchronous Rectifier
and the current starts ramping up. When the sum of the ramp The ISL9113 integrates one N-channel MOSFET and one
and the slope compensator output reaches the error amplifier P-channel MOSFET to realize a synchronous boost converter.
output voltage, the PWM comparator outputs a signal to turn OFF Because the commonly used discrete Schottky rectifier is
the N-channel MOSFET. Here, both MOSFETs remain OFF during replaced with the low rDS(ON) P-channel MOSFET, the power
the dead-time interval. Next, the P-channel MOSFET is turned ON conversion efficiency reaches a value above 90%. Since a typical
and remains ON until the end of this PWM cycle. During this time, step-up converter has a conduction path from the input to the

FN8313 Rev 3.00 Page 7 of 15

February 23, 2015
ISL9113

output via the body diode of the P-channel MOSFET, a special divider should be placed close to the FB pin to prevent noise
circuit (see “Block Diagrams” on pages 2 and 3) is used to pickup. Figures 4 and 5 show the recommended PCB layout.
reverse the polarity of the P-channel body diode when the device
In the 8 Ld DFN package, the heat generated in the device is
is shut down. Thus, this configuration completely disconnects the
mainly dissipated through the thermal pad. Maximizing the
load from the input during shutdown of the converter. The benefit
copper area connected to the thermal pad is preferable. It is
of this feature is that the battery will not be completely depleted
recommended to add at least 4 vias within the pad to the GND
during shutdown of the converter. No additional components are
plane for the best thermal relief.
needed to disconnect the battery from the output of the
converter.

Soft-Start
The soft start-up duration is the time between the device being
enabled and VOUT rising to within 3% of target voltage. When the
device is enabled, the start-up cycle starts with a linear phase.
During the linear phase, the rectifying switch is turned ON in a
current limited configuration, delivering about 350mA, until the
output capacitor is charged to approximately 90% of the input
voltage. At this point, PWM operation begins in boost mode. If
the output voltage is below 2.3V, PWM switching is done at a
fixed duty-cycle of 75% until the output voltage reaches 2.3V.
When the output voltage exceeds 2.3V, the closed-loop current
mode PWM loop overrides the duty cycle until the output voltage
is regulated. Peak inductor current is ramped to the final value
(typically 1.3A) during the soft-start period to limit inrush current
from the input source. Fault monitoring begins approximately
2ms after the device is enabled.

Over-temperature Protection (OTP) FIGURE 4. RECOMMENDED PCB LAYOUT (DFN VERSION)

The device offers over-temperature protection. A temperature

sensor circuit is integrated and monitors the internal IC GND VBAT
temperature. Once the temperature exceeds the preset threshold
(typically +150°C), the IC shuts down immediately. The OTP has
a typical hysteresis of +25°C. When the device temperature
decreases by this, the device starts operating.

Fault Monitoring and Reporting

Fault monitoring starts 2ms after start-up. Table 1 shows the
response to different detected faults. Any fault condition shown VOUT
in Table 1 causes the FAULT pin to be taken LOW. The FAULT pin
will not release until VBAT and VOUT fully collapse or until the fault
condition is removed.

Printed Circuit Board Layout

Recommendations GND
The ISL9113 is a high frequency switching boost converter.
Accordingly, the converter has fast voltage change and high
FIGURE 5. RECOMMENDED PCB LAYOUT (WLCSP VERSION)
switching current that may cause EMI and stability issues if the
layout is not done properly. Therefore, careful layout is critical to
minimize the trace inductance and reduce the area of the power
Fixed and Adjustable Output Voltage
loop. ISL9113 offers options for fixed output voltage of 5V, 5.1V or an
adjustable output voltage.
Power components, such as input capacitor, inductor and output
capacitor, should be placed close to the device. Board traces that For the fixed output voltage version (ISL9113ER7Z,
carry high switching current should be routed wide and short. A ISL9113EI9Z-T), an internal voltage divider is used (see “Block
solid power ground plane is important for EMI suppression. Diagrams”, “ISL9113ER7Z” on page 2). For the adjustable output
voltage version (ISL9113ERAZ), the output voltage is programmed
The switching node (SW pin) of the converter and the traces by connecting two external voltage divider resistors between VOUT,
connected to this pin are very noisy. Noise sensitive traces, such FB and GND (see “Block Diagrams”, “ISL9113ERAZ” on page 3).
as the FB trace, should be kept away from SW node. The voltage

FN8313 Rev 3.00 Page 8 of 15

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ISL9113

TABLE 1. FAULT DETECTION AND RESPONSE

FAULT CONDITION DETECTION DETAILS ACTION

Low Battery Voltage VBAT < 0.7V Shut down until VEN or VBAT is cycled.

VOUT out of Regulation VOUT is 10% below the target output voltage Shut down only if VBAT and VOUT fall below 2.1V. Device
automatically restarts after 200ms.
FAULT signal switches ON and OFF when VOUT drops
out of regulation due to overload condition.

Short Circuit VOUT falls below VBAT Shut down immediately. Device automatically restarts
after 200ms.

Over-temperature Protection Die temperature is > +150°C Switching stops. Device automatically restarts when
temperature decreases to +125°C.

Output Overvoltage Protection (ADJ version only) VOUT > 5.9V Switching stops until EN pin is toggled or power is
cycled.

Output Voltage Setting Resistor Selection Capacitor Selection

For the ISL9113 adjustable output version, resistors R1 and R2,
INPUT CAPACITOR
shown in the Block Diagram “ISL9113ERAZ” on page 3, set the
desired output voltage values. The output voltage can be A minimum of a 4.7µF ceramic capacitor is recommended to
calculated using Equation 1: provide stable operation under typical operating conditions. For
 R 1 input voltage less than 1.0V application, an additional 4.7µF
V OUT = V FB   1 + ------- (EQ. 1) ceramic capacitor is recommended for better noise filtering and
 R 2
EMI suppression. The input capacitor should be placed close to
where VFB is the internal FB reference voltage (0.8V typical). The the input pin, GND pin and the non-switching terminal of the
current flowing through the divider resistors is calculated as inductor.
VOUT /(R1 + R2). Large resistance is recommended to minimize
OUTPUT CAPACITOR
current into the divider and thus improve the total efficiency of
the converter. R1 and R2 should be placed close to the FB pin of For the output capacitor, a ceramic capacitor with small ESR is
the device to prevent noise pickup. recommended to minimize output voltage ripple. A typical 4.7µF
should be used to provide stable operation at different typical
Inductor Selection operating conditions. The output capacitor should be placed
close to the output pin and GND pin of the device. Table 3 shows
An inductor with core material suitable for high frequency
the recommended capacitors.
applications (e.g., ferrite) is desirable to minimize core loss and
improve efficiency. The inductor should have a low ESR to reduce TABLE 3. CAPACITOR VENDOR INFORMATION
copper loss. Moreover, the inductor saturation current should be
MANUFACTURER SERIES WEBSITE
higher than the maximum peak current of the device; i.e., 1.5A.
AVX X5R www.avx.com
The device is designed to operate with an inductor value of 2.2µH
to provide stable operation across the range of load, input and Murata X5R www.murata.com
output voltages. Stable mode switching between PWM and skip
Taiyo Yuden X5R www.t-yuden.com
mode operation is guaranteed at this inductor value. Table 2
shows recommended inductors. TDK X5R www.tdk.com

TABLE 2. INDUCTOR VENDOR INFORMATION

MANUFACTURER PART NUMBER DIMENSIONS- W x L x H (mm)

Murata LQH32PN2R2NN0L 3.2 x 2.5 x 1.7(max)

Toko 1239AS-H-2R2M 2.5 x 2.0 x 1.2(max)

1286AS-H-2R2M 2.0 x 1.6 x 1.2(max)

TDK TFM201610A-2R2M 2.0 x 1.6 x 1.0(max)

Cyntec PSE25201B-2R2MS 2.0 x 1.6 x 1.2(max)

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ISL9113

Typical Characteristics
100 1.2
VBAT = 3.6V
95
VBAT = 4.2V VBAT = 3.0V
1.0
90 VOUT = 5.0V

85 0.8
EFFICIENCY (%)

VOUT = 4.0V
80

IOUT (A)
75 0.6
VBAT = 2.3V
70
0.4
65
VBAT = 1.2V
60 0.2
55
VOUT = 5.1V
50 0
0.0001 0.001 0.01 0.1 1 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8
VBAT (V)
LOAD CURRENT (A)
FIGURE 6. FIXED 5.1V EFFICIENCY (ISL9113EI9Z) FIGURE 7. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
(ISL9113ERAZ)

L = 2.2µH, COUT = 4.7μF VIN = 3.0V, VOUT = 5.0V, ILOAD = 20mA

5.16

5.14

ILOAD = 1mA (PFM) VOUT WITH 5V OFFSET (200mV/DIV)

5.12

5.10
VOUT (V)

ILOAD = 100mA (PWM)

5.08 INDUCTOR CURRENT(500mA/DIV)

5.06

5.04
SW (5V/DIV)

5.02
0 1 2 3 4 5
VBAT (V) TIME 10µs/DIV
FIGURE 8. LINE REGULATION, VOUT = 5V (ISL9113ER7Z) FIGURE 9. PULSE SKIP MODE WAVEFORM

L = 2.2µH, COUT = 4.7μF VBAT = 3.0V, VOUT = 5.0V, ILOAD = 250mA VBAT = 3.0V, VOUT = 5.0V, ILOAD = 250mA

EN
VOUT WITH 5.0V OFFSET (50mV/DIV)

VOUT (2V/DIV)
INDUCTOR CURRENT(500mA/DIV)

INDUCTOR CURRENT(500mA/DIV)

SW(5V/DIV)
SW (2V/DIV) TIME 1µs/DIV TIME 40ms/DIV
FIGURE 10. PWM WAVEFORM FIGURE 11. START-UP AFTER ENABLE (ILOAD = 250mA)

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ISL9113

Typical Characteristics (Continued)

VBAT = 3.0V, VOUT = 5.0V, ILOAD = 50mA VBAT = 3.6V, VOUT = 5.0V

VOUT (100mV/DIV)
EN (5V/DIV)

VOUT (2V/DIV)

INDUCTOR CURRENT(500mA/DIV)

ILOAD AT 0.66Ω
INDUCTOR CURRENT(500mA/DIV)
(200mV/DIV)

SW(5V/DIV) TIME 400µs/DIV

TIME 40ms/DIV
FIGURE 12. START-UP AFTER ENABLE (ILOAD = 50mA) FIGURE 13. LOAD TRANSIENT RESPONSE (100mA TO 500mA)

5.20
VBAT = 3.6V, VOUT = 5.0V

5.15
VOUT (200mV/DIV)
VOUT (V)

5.10
TBD

4.2V
3.0V 3.6V
INDUCTOR CURRENT(500mA/DIV) 5.05

ILOAD AT 0.66Ω
(200mV/DIV) 5.00
0 0.2 0.4 0.6 0.8 1.0
TIME 400µs/DIV ILOAD (A)

FIGURE 14. LOAD TRANSIENT RESPONSE (20mA TO 250mA) FIGURE 15. LOAD REGULATION (ISL9113ER7Z)

FN8313 Rev 3.00 Page 11 of 15

February 23, 2015
ISL9113

Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.

DATE REVISION CHANGE

February 23, 2015 FN8313.3 Updated Datasheet with Intersil new standards.
On page 6, under the“Absolute Maximum Ratings” section added “FB” to the first line.
Replaced Figure 9 on page 10.
Updated the About Intersil verbiage.

February 18, 2013 FN8313.2 Page 1:

Added 5.1V or Adjustable Output options to “Features”
Removed "Coming Soon" from WLCSP package references
Updated Figure 2. Changed y axis scale

Page 5:
Added information for WLCSP package option.

Page 6:
Removed Machine Model from “ESD Ratings”.
Added “Thermal Information” for WLCSP.

“Electrical Specifications” on page 6:

“Input Undervoltage Lockout”, aded "DFN versions only" to test conditions.
Changed parameter name from “Output Voltage Accuracy” to “Output Voltage”. Added "5V DFN Fixed version" to test
conditions where ILOAD = 50mA. Changed MIN/MAX from -100/+100 mV to 4.9/5.1 V. Added TYP. Added lines for ADJ
version only and WLCSP Fixed version.
Added "ADJ version only" to test conditions for “Feedback Voltage”.
Added test conditions for “Feedback Pin Input Current”.
Added WLCSP specs for “PWM Switching Frequency”.

“Electrical Specifications” on page 7:

Added "DFN versions" to test conditions for “Load Regulation” where ILOAD = 0 to 100mA. Added line for WLCSP
versions.
Added test conditions for “Output Overvoltage Protection Threshold”.

Page 8:
Added Figure 5 “RECOMMENDED PCB LAYOUT (WLCSP VERSION)”.
Changed “Fixed and Adjustable Output Voltage” from:
“ISL9113 offers options for fixed output voltage of 5V or an adjustable output voltage. For fixed output voltage version
(ISL9113ER7Z)..”
to:
“ISL9113 offers options for fixed output voltage of 5V, 5.1V, or an adjustable output voltage. For fixed output voltage
version (ISL9113ER7Z, ISL9113EI9Z-T)..”

Revised Table 2. Added dimensions. Revised Manufacturers and Part Numbers.

Added new efficiency plot, Figure 6.

Added “W3x2.6” on page 15.

January 16, 2013 FN8313.1 Updated Related Literature on page 1.

Changed ESD Ratings in “Absolute Maximum Ratings” on page 6 as follows:
HBM from 2.5kV to 3kV
MM from 250V to 300V

July 12, 2012 FN8313.0 Initial Release.

FN8313 Rev 3.00 Page 12 of 15

February 23, 2015
ISL9113

About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support

© Copyright Intersil Americas LLC 2012-2015. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN8313 Rev 3.00 Page 13 of 15

February 23, 2015
ISL9113

Package Outline Drawing

L8.2x2D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD
Rev 0, 3/11

2.00 6
A
PIN #1
6 B INDEX AREA
PIN 1
INDEX AREA
8 1
6x 0.50

2.00
1.55±0.10

(4X) 0.15
0.10M C A B 0.22 ( 8x0.30 )
TOP VIEW 4
0.90±0.10
0±0.10
0±0.10
BOTTOM VIEW

SEE DETAIL "X"

C 0 . 2 REF
0.10 C
C
0.90±0.10
BASE PLANE
0 . 00 MIN.
SEATING PLANE 0 . 05 MAX.
SIDE VIEW 0.08 C DETAIL "X"

PACKAGE ( 8x0.20 )
OUTLINE ( 8x0.30 ) NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
( 6x0.50 )
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
1.55 2.00
3. Unless otherwise specified, tolerance: Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

( 8x0.22 ) 5. Tiebar shown (if present) is a non-functional feature.

0.90
2.00 6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
TYPICAL RECOMMENDED LAND PATTERN either a mold or mark feature.

FN8313 Rev 3.00 Page 14 of 15

February 23, 2015
ISL9113

Package Outline Drawing

W3x2.6
3X2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLSCP 0.4MM PITCH)
Rev 3, 1/13

X
1.360±0.03
Y
0.280
0.200
0.800

2
0.800±0.03

(4X) 0.10 1
0.400
PIN 1 0.200
(A1 CORNER) C B A
TOP VIEW
6X 0.265±0.035

BOTTOM VIEW

PACKAGE
OUTLINE

4
0.240
0.10 ZXY
SEATING PLANE 2
0.400 0.05 Z
3 0.265±0.035
Z

0.200±0.030

0.05 Z
0.290

0.500±0.050
6 NSMD
TYPICAL RECOMMENDED LAND PATTERN SIDE VIEW

NOTES:
1. Dimensions and tolerance per ASME Y 14.5M - 1994.

2. Dimension is measured at the maximum bump diameter

parallel to primary datum Z .

3. Primary datum Z and seating plane are defined by the spherical

crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.

5. All dimensions are in millimeters.

6. NSMD refers to non-solder mask defined pad design per Intersil
Tech Brief www.intersil.com/data/tb/tb451.pdf
7. Ball height and post saw device size can vary by ±10µm
depending on final selection of assembly vendor.

FN8313 Rev 3.00 Page 15 of 15

February 23, 2015