7314 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO.

9, SEPTEMBER 2018

Measurement Methodology for Accurate Modeling of

SiC MOSFET Switching Behavior Over Wide
Voltage and Current Ranges
Hiroyuki Sakairi , Tatsuya Yanagi , Member, IEEE, Hirotaka Otake , Naotaka Kuroda, Hiroaki Tanigawa ,
and Ken Nakahara , Member, IEEE

(Highlighted Paper)

Abstract—This paper presents two novel measurement methods I. INTRODUCTION

to characterize silicon carbide (SiC) MOSFET devices. The re-
IDE-BAND-GAP semiconductors such as silicon car-
sulting data are utilized to significantly improve the extraction of
a custom device model that can now accurately reproduce device
switching behavior. First, we consider the Id−Vds output character-
W bide (SiC) and gallium nitride (GaN) are promising
candidate materials for power devices because they show ex-
istics of power devices such as SiC transistors. These are typically cellent performance in low on-resistance, high-frequency, and
measured using traditional curve tracers, but the characteriza-
tion of the high-voltage and high-current (HVHC) region is very
high-speed switching, as well as in operation at high tempera-
challenging because of device power compliance and self-heating. tures beyond the operating range of Si devices [1], [2]. Espe-
In this paper, we introduce a measurement technique that over- cially, the high-frequency and high-speed operation capability
comes self-heating and derives the HVHC region from switching of SiC and GaN devices expands the possibility of miniaturiz-
waveforms. The switching transient characteristics of devices are ing power electronics systems [3]. However, these high-speed
used to determine drain current (Id ) as a function of drain–source
voltage (Vds ) in the HVHC range. Second, we consider another operations increase the time derivatives of voltage (dv/dt) and
challenging characterization area: measurement of nonlinear ca- current (di/dt) and deteriorate the conducted and/or radiated
pacitances when device is turned on. These capacitance character- emissions [4]. This makes it difficult to ensure electromagnetic
istics of on-state devices are important for correcting disagreements compatibility (EMC). Experimental approaches for improving
between simulations and measurements in turn-off switching tran- EMC require multiple rounds of testing, which inevitably de-
sient waveforms and cannot be measured using a conventional
capacitance-voltage meter. We introduce S-parameter measure- lays product launch. Thus, the front-loading design should be
ments as an effective method to obtain the capacitance character- established for achieving EMC by maximizing the features of
istics of both off-state devices and on-state devices. These novel power devices built using the new materials.
measurement techniques have been applied to the modeling of a To this end, it is crucial to establish a simulation environment
SiC device. The extracted device model, a modified version of the that accurately predicts the electromagnetic (EM) noise in the
popular Angelov−GaN high-electron-mobility transistor model,
shows significant improvement in terms of the accuracy of switch- investigated systems. This means that the simulation has to re-
ing waveforms of devices over a wide range of operating conditions. produce the transient waveforms of power device switching as
accurately as possible, because the switching process generates
Index Terms—Circuit simulation, device modeling, double pulse high-frequency electric signal components, which mainly gen-
tester, MOSFET, silicon carbide (SiC), S-parameter, switching erate EM noise. Accordingly, the quality of the switching device
behavior. model used in the simulation significantly influences simulation
quality.
The power device modeling methods previously reported,
however, include insufficient experimental data on the range
Manuscript received May 11, 2017; revised August 25, 2017; accepted Oc- of drain current (Id ) and drain–source voltage (Vds ). Measured
tober 3, 2017. Date of publication November 1, 2017; date of current version data of several tens of amperes for Id and ∼20 V for Vds are
June 22, 2018. Recommended for publication by Associate Editor S. S. Ang.
(Corresponding author: Hiroyuki Sakairi.) conventionally used for extracting the parameters of a device
H. Sakairi, T. Yanagi, H. Otake, N. Kuroda, and K. Nakahara are with the De- model. However, these values are far less than the Id and the
partment of Research and Development, Rohm Co., Ltd., Kyoto 615-8585, Vds, values used commonly in the power applications in which
Japan (e-mail: hiroyuki.sakairi@dsn.rohm.co.jp; tatsuya.yanagi@dsn.rohm.
co.jp; hirotaka.otake@dsn.rohm.co.jp; naotaka.kuroda@dsn.rohm.co.jp; ken. SiC and GaN are expected to be applied [3], [5]. Consequently,
nakahara@dsn.rohm.co.jp). it is necessary to measure the Id−Vds characteristics in higher
H. Tanigawa is with the EEsof EDA, Keysight Technologies Japan G.K., current and voltage regions than usual to develop high-quality
Tokyo 192-8550, Japan (e-mail: hiroaki_tanigawa@keysight.com).
Color versions of one or more of the figures in this paper are available online power device simulation models.
at http://ieeexplore.ieee.org. Another problem is measuring the capacitance-voltage
Digital Object Identifier 10.1109/TPEL.2017.2764632 (C–V) characteristics of power devices. The commonly used

0885-8993 © 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution
requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
SAKAIRI et al.: MEASUREMENT METHODOLOGY FOR ACCURATE MODELING OF SIC MOSFET SWITCHING BEHAVIOR OVER WIDE VOLTAGE 7315

C–V meter is capable of measuring device capacitance in the

off-state. However, the on-state C–V curve of a MOSFET heav-
ily affects its switching transient behavior, especially in the
turning-off transition, but this type of measurement has not yet
been established.
The last issue we discuss here is determining how to include
the parasitic impedance of a measurement system into switching
simulation because the system itself has non-negligible effects
on switching waveforms. One approach is to measure parasitic
impedances, for which circuit simulation is performed [6]; an-
other is to model the system by calculating the S-parameters
[7], [8]. We do not choose the first option because it requires Fig. 1. Equivalent circuit of the original Angelov model that was adapted to
measurements, thus conflicting with the main research focus of add a pn-diode as the body diode of a SiC MOSFET.
front-loading design.
In this study, we propose experimental procedures for ex-
the gradient of the drain current depended on Vgs . Therefore, we
tracting an accurate device model. A commercially available
added a gate bias-dependent term to the original Angelov−GaN
SiC MOSFET is examined as the research object. The charac-
HEMT model equation [9] to better represent the actual Id−Vds
terization process is as follows:
characteristics of the SiC MOSFET in the HVHC range.
1) static Id−Vds characteristics of the SiC device are obtained
The drain current equations are given as follows:
in a high-voltage and high-current (HVHC) range by per-
forming switching measurements;
2) the C–V curves of the SiC device with a forward bias Ids = 0.5 × (Idsp − Idsn ) (1)
applied to its gate are acquired by S-parameter measure- Idsp = A × g1 (Vgs ) × (1 + f1 (Vgs , Vds )) × (1 + g3 (Vgs )
ments; and
3) EM simulation is performed to determine the S-parameter × f2 (Vgs , Vds ) + B × g4 (Vds )) (2)
describing the measurement system and the device pack- Idsn = A × g1 (Vgd ) × (1 + f1 (Vgd , Vds )) × (1 + g3 (Vgd )
age, and this result can be used directly in an S-parameter-
based circuit simulation. ×f2 (Vgd , Vds )) (3)
The above modeling procedure is applied to a modified   
g1 (Vi ) = 1 + tanh 0.5 × eg 2 (V i ) − e−g 2 (V i ) (4)
version of the Angelov−GaN high-electron-mobility transis-
tor (HEMT) model, which serves as an example of a state of g2 (Vi ) = C1 × (Vi − f3 (Vdg , Vds ) + C2
the art model capable of incorporating key effects. However, the 
procedure can be applied to any compact model. × (Vi − f3 (Vdg , Vds ))2 + C3 × (Vi − f3 (Vdg , Vds ))3 (5)
In each characterization step, a subset of related model param-
eters of the modified Angelov−GaN HEMT was extracted by g3 (Vi ) = G1 + G2 × g1 (Vi ) (6)
comparing measured and simulated data. Finally, the measured × (V ds − K )
and the simulated switching waveforms of gate–source voltage g4 (Vds ) = eJ (7)
(Vgs ), Vds , and Id were compared, and very good agreement was f1 (Vi , Vds ) = tanh ((E + F × g1 (Vi )) × Vds ) (8)
found over a wide operation range.
f2 (Vi , Vds ) = tanh ((H1 × tanh (1 + H2 × Vi )) × Vds ) (9)
II. SELECTED DEVICE AND MODEL f3 (Vdg , Vds ) = D − L + L × tanh (F × Vds ) − M
The examined device was a SiC MOSFET (SCT2080KE × (Vdg − K)2 . (10)
made by ROHM Co., Ltd.; Rated voltage = 1200 V;
Rated current = 40 A). The Angelov−GaN HEMT model was
The term added for the current equation is (9). H1 and
employed as the base model for the SiC MOSFET model used
H2 are channel length modulation parameters, and they are
in this work [9]. Fig. 1 shows an equivalent circuit schematic
used for fitting the SiC MOSFET model to measurements.
of the device model used. The original Angelov−GaN HEMT
H2 is an added parameter for describing the dependence of
topology was modified by adding a pn-diode model between the
output conductance on Vgs in the large Vgs × Vds region.
source and the drain. The current and charge model equations
A, B, C1 , C2 , C3 , D, E, F, G1 , G2 , H1 , H2 , J, K, L, and M
were modified to better represent the I–V and the C–V character-
are fitting parameters in the SiC MOSFET model, and Vi is Vgs
istics of the SiC MOSFET. The modified parts of the equations
or gate–drain voltage (Vgd = −Vdg ).
are explained in this section.

A. Drain Current Equations B. Charge Equations

As shown in Fig. 7 in Chapter III, we found that the drain We modified the charge equations of the SiC MOSFET model.
current of the SiC MOSFET at each Vgs was not saturated in the The parasitic capacitances of the SiC MOSFET were modeled
measured HVHC range (the so-called saturation region), and using the following mathematical scheme.
7316 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 9, SEPTEMBER 2018

First, the charge between the gate and the source Qgs is ex-
pressed as follows:
Qgs = (Cgs0 + Cgs1 × f32 (Vgs , Vds )) + (Cgs0 + (Cgs1
× f31 (Vgs , Vds ) + Cgs2 × f33 (Vgs , Vds )) × f32 (Vgs , Vds ))
(11)
f3i (Vgs , Vds ) = 1 + tanh (Li + Ni × Vgs + Pi × Vds )
(i = 1 ∼ 6) (12)
C gs0 is a gate–source pinch-off capacitance, and C gs1 and
Cgs2 are gate–source capacitance parameters. Cgs0, Cgs1 , Cgs2 , Fig. 2. Schematic diagram of clamped inductive load circuit used to acquire
Li , Ni , Pi are fitting parameters of the SiC MOSFET model. switching behavior of SiC MOSFET. The direction of the arrows shows the
high-side of the voltage and the positive direction of the flowing current.
As for Qgs , capacitances with two types of dependence on the
gate–source voltage can be expressed by using f31 to express a
adding a pn-diode model between its drain and source electrode
positive bias dependence on the gate–source voltage and f33 to
to reproduce the Cds−Vds capacitance characteristics, as shown
express a negative bias dependence.
in Fig. 1. In this work, the I–V characteristics of the body diode
Second, the charge between the gate and the drain Qgd is
were not used in the inductive load switching circuit that we
expressed as follows:
used for model validation because the high-side device in the
When Vds is greater than −Fcp
switching circuit is a Schottky barrier diode and the low-side de-
Qgd = Cgd1 + g5 (Vds ) × f34 (Vgs , Vds ) + Cgd2 × g5 (Vds ) vice does not use the reverse current characteristics. Therefore,
we fitted the reverse I–V characteristics of the SiC MOSFET
× f35 (Vgs , Vds ) + Cgd3 + Cgd4 × f36 (Vgs , Vds ) (13)
very roughly. More accurate modeling of the reverse Id−Vds
 −M m characteristics could be a topic for a future investigation.
Vds
g5 (Vds ) = Cgd0 × 1 + . (14) The most important part in this study was establishing a mea-
Vj
surement procedure to obtain accurate experimental data, so
When Vds is smaller than −Fcp that the model can predict device behavior in a circuit. The de-
Qgd = Cgd1 + g6 (Vds ) × f34 (Vgs , Vds ) + Cgd2 × g6 (Vds ) tails of the developed measuring techniques are described in the
following sections.
× f35 (Vgs , Vds ) + Cgd3 + Cgd4 × f36 (Vgs , Vds ) (15)
Cgd0 III. ID−VDS CHARACTERISTICS MEASUREMENT
g6 (Vds ) = Mm
(1 − Fc ) A. Principle of Measuring Static Id−Vds Characteristics Based
    on Switching Behavior
Mm
× 1+ × (−Vds − Fc × Vj ) .
Vj (1 − Fc ) Previous static Id−Vds characteristic measurements, as de-
(16) scribed in the introduction, did not cover the voltage and current
areas where SiC MOSFETs are expected to be applied. Self-
Here Fcp is defined as follows: heating of the device under test (DUT) cannot be avoided when
Fcp = Fc × Vj (17) using the conventional methodology. Therefore, we developed
a new method to measure the Id−Vds characteristics by utilizing
where Fc is a forward bias junction parameter of Cgd , and Vj is switching transient behavior measurements. A similar method
the junction potential of Cgd0 . has already been proposed elsewhere [9], but we improved it to
Where Cgd1 is a gate–drain pinch-off capacitance, Cgd0 is acquire the Id−Vds characteristics over wider voltage and current
a gate–drain capacitance parameter, M m is a grading coeffi- regions than those in the reference. The main differences from
cient for Cgd0 , and Cgd2 is a gate–drain capacitance parameter. the previous study [10] pertain to the method of measuring Ig
Cdg0, Cdg1 , Cdg2 , Cdg3 , Cdg4, Vj , M m, and Fc are fitting parame- and the gate plateau voltage used to derive Vgs .
ters of the SiC MOSFET model. Qgd consists of two numerical A clamped inductive load switching circuit (see Fig. 2) al-
expressions with junction capacitance, which results in more lows us for the characterization of the switching transient wave-
accurate drain voltage dependence. The f36 function provides forms of the SiC MOSFET. Three SiC Schottky barrier diodes
a good fit of the simulation data to the experimental data in the (SCS240KE2 made by ROHM Co., Ltd.) were connected in par-
low drain voltage region. allel and used as the high-side device. E, Cf , L, and Rg denote a
power source (600 V), film capacitor (160 μF), load inductance
C. Body-Diode Model
(500 μH), and gate resistance (240 Ω), respectively.
The SiC MOSFET has a body diode in its device structure, The switching data acquired with Id = 20 A are plotted as a
which is not considered in the original Angelov−GaN HEMT trajectory curve in the Id−Vds plane (pale orange line) in Fig. 3.
model because GaN HEMTs have dissimilar structures. There- This figure includes the red lines denoting the Id−Vds character-
fore, we adapted this model to create the SiC device model by istics measured using a curve tracer (CT).
SAKAIRI et al.: MEASUREMENT METHODOLOGY FOR ACCURATE MODELING OF SIC MOSFET SWITCHING BEHAVIOR OVER WIDE VOLTAGE 7317

Fig. 3. Id−V ds plane including SW of SiC MOSFET (solid pale yellow line
“SW”), and CT measurement results (red solid lines “CT”). A, B, and C denote
the discriminative switching points detailed in the main text.

First, Fig. 3 shows that the CT data do not cover the actual
operating area at all. The Id−Vds characteristics region delin-
eated by the switching trajectory (SW) in this figure is the least
data necessary to predict the switching behavior of this power
device.
Second, the SW line indicates the method of measuring Fig. 4. Experimental switching waveforms of SiC MOSFET in inductive load
the Id−Vds characteristics in real operating ranges by obtain- switching using circuit shown in Fig. 2.
ing switching measurements. When the DUT was switched on,
the track shifted from A (off-state) through B to C (on-state). Id
cannot increase beyond the load current determined by the high-
side closed loop composed of an inductor and diodes. Therefore,
at this moment, the direction of the Id−Vds trajectory must be
changed. Point B in Fig. 3 denotes the moment at which Vgs
reaches the so-called gate plateau voltage (Vp ). This means that
point B in Fig. 3 identifies the Id−Vds characteristics specified by
Vgs = Vp in a high-Vds region. Our measurement method, which
allows us for the determination of Id−Vds over wider voltage Fig. 5. Equivalent gate-driving circuit; R g,in denotes internal gate resistance
of SiC MOSFET die, and V GD is output voltage of gate driver.
and current regions without self-heating of the DUT, is based
on this experimental observation, and details of the associated
procedures are given in the following two sections.
Fig. 4 shows the switching waveforms of a SiC MOSFET Vds = 600 V and Id = 20 A. By contrast, when using the con-
in the turn-on transient, as measured using the circuit dis- ventional method, it can be as much as 1.2 J when the CT pulse
played in Fig. 2. The operating conditions are as follows: width is 100 μs, which is the general setup for the CT mea-
E = 600 V, Rg = 240 Ω, and L = 500 μH. The symbols A, B, surements. This finding validates that our method is appropriate
and C in the figure denote the respective operation points, as in for obtaining the true static Id−Vds characteristics of a DUT
Fig. 3. The plateau region must be long to improve the accuracy at room temperature. Therefore, we used the switching behav-
of the transient response measurement. Thus, gate resistance ior data to acquire the static Id−Vds characteristics over a wide
was set to a large value of 240 Ω. Id−Vds range.
Id remains zero from the beginning of switching to the op-
eration point A, when the time zone Vgs does not exceed the
B. Adapting Vgs and RT Static Id −Vds Curves
threshold voltage (Vth ) of the DUT. In the operating region
from A to B, Id increases while Vds remains constant. When Id We should note, however, that the Vgs measured using our
reaches the load current, Vds starts to decrease while Id remains method is not the same as that captured using the CT. The CT
constant and Vgs is pinned to Vp [11], [12]. As explained above, measures Id at Ig = 0 A, because the measurement is performed
this data point provides the static Id−Vds characteristics speci- after adequate time elapses for Vgs to become constant. Thus,
fied by point B. If this process is repeated with different E and the conventionally measured Vgs is always equal to the voltage
Id , the obtained dataset including Vgs , Id , and Vds allows us to applied to the gate oxide layer of a MOSFET (Vgo ), which
determine the Id−Vds characteristics in the HVHC region. determines the Id−Vds curves. As shown in Fig. 4, however, Ig
In addition, device self-heating is negligible when using is not 0 A with this method, and Vgo = Vgs . Accordingly, the Vgs
this method. The energy equivalent to the heat generated dur- measured by this method must be adapted to obtain the static
ing one switching process is calculated to be 6.6 mJ when Id−Vds curves.
7318 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 9, SEPTEMBER 2018

Fig. 6. RT Id−V go characteristics obtained by multitudinous switching mea- Fig. 7. Id−V ds characteristics acquired from switching waveform data in
surements. HVHC region.

The equivalent gate-driving circuit is shown in Fig. 5. As

indicated in the figure, the output voltage of the gate driver (VGD )
decreases due to Rg and the internal gate resistance (Rg,in ) when
Ig flows in the manner shown in this figure. Thus, Vgs differs
from Vgo .
As described in detail in Section A, we collect Id and Vgs at
various E to acquire the Id−Vds characteristics, but it is very
difficult to specify Id , Ig , and Vgo from the measured data due
to non-negligible jitter (see Fig. 4). Thus, the mean value over
the plateau region is used to obtain the Id−Vds characteristics.
The measured Vp and Ig data in the plateau region of a switch-
ing waveform are averaged (Vp,ave and Ig,ave ) to eliminate jitter
in the data. This is validated by the facts that Ig is constant in
the plateau region because Ig can be simply calculated by Fig. 8. Modeling flow chart for the parameter extraction.

VGD − Vgs
Ig = (18) The function used is a polynomial expression as follows:
Rg

n

and VGD and Rg are constant with Vgs being fixed at Vp . y= ai X i . (20)
Accordingly, Vgo is computed as i=0

We chose a value of n between 3 and 6 to obtain the best fit.

Vgo = Vp,ave − Rg,in Ig,ave . (19) These fitted curves provide the dataset of Id and Vds at a specific
Vgo , and finally the static Id−Vgs characteristics are shown in
This Vgo corresponds to the Vgs conventionally obtained by Fig. 7, wherein Vgs is used as Vgo to place the curves in the
the CT. conventional context. In this figure, the plotted points are the
Furthermore, we should consider that the SiC MOSFET has measured data.
positive Id−Vds curves, even in the saturation region, owing to
its short channel effect [11], [13]. Consequently, Vp depends on
Vds even at the same Id ; therefore, Vp must be measured under C. Parameter Extraction Using Id−Vds Characteristics With
different Vds and Id . Accordingly, in this study, the switching HVHC Region Data
characteristics are measured at E = 30, 100, 200, 400, and 600 Using measured Id−Vds data from HVHC region, parameter
V, and the equation (19) provides Vgo , which is regarded as extraction was performed with a commercially available param-
Vgs in the conventional context. The measured Id values are eter extraction tool (IC-CAP; Keysight Technologies, Inc.). IC-
plotted as a function of Vgo at each Vds (= E), leading to the CAP includes the original and modified Angelov–GaN model.
Id−Vgo characteristics. Fig. 6 shows the Id−Vgo characteristics The measured I–V and C–V data were fed into IC-CAP, and the
at Vds = 100, 200, 400, and 600 V, as examples. simulated data were fitted to the measured data for a parameter
In the switching measurements, Vds and Id can be specified extraction. The fitting procedure was performed with the non-
intentionally, whereas Vgo cannot be. The Id and Vds values at linear least-squares-fit algorithm in IC-CAP until the root mean
a specific Vgo , however, are necessary to draw an Id−Vds curve, squared (RMS) error was less than 5% and 10% for the I–V and
and, thus, a number of measured Id−Vgo curves are fitted by C–V curves, respectively. Fig. 8 presents a flow chart for the
polynomial approximation by using the least squares method. parameter extraction.
SAKAIRI et al.: MEASUREMENT METHODOLOGY FOR ACCURATE MODELING OF SIC MOSFET SWITCHING BEHAVIOR OVER WIDE VOLTAGE 7319

Fig. 9. (a) Fitted results of Id−V ds characteristics in the CT measurement

region. (b) Fitted results of Id−V ds characteristics in the HVHC region. The
red lines in (a) and the circles, triangles, and crosses in (b) are measured data.
The blue dot and solid lines show the Id−V ds curves fitted by models A and B,
respectively.

In the parameter extraction for I–V characteristics, first, the

Id−Vds characteristics in the CT measurement region were
roughly fitted. Second, the Id−Vds characteristics in the HVHC
region were accurately fitted. Finally, the Id−Vds characteristics
in the CT measurement region were fitted once again with in-
creased accuracy; however, in this step, we considered only the
accuracy of the linear region (Ron ) of the Id−Vds curves.
The parameter extraction results are shown in Fig. 9. Fig. 9(a)
and (b) shows the fitted results of Id−Vds characteristics in the Fig. 10. (a) C iss , C oss , and C rss of off-state SiC MOSFET as a function of
CT measurement region and the HVHC region, respectively. We V ds . V gs = 0 V. (b) C gs of off-state SiC MOSFET as a function of V gs . V ds =
compared the two types of device models. One was fitted with 0 V. (c) C gd of off-state SiC MOSFET as a function of V gd . V ds = 0 V. The
broken red lines represent experimental data, and the solid blue lines represent
model A using only the I–V data from CT measurements, which the simulated data after extracting the parameters for the applied device model.
is plotted with dotted blue lines in Fig. 9. The other was fitted
with model B using datasets from both the CT measurements
and the HVHC switching measurements, which is plotted with IV. C–V CHARACTERISTICS MEASUREMENT
solid blue lines in Fig. 9. In Fig. 9(a), models A and B both
agree well with the experimental curve obtained with the CT. A. Off-State C–V Measurement
Conversely, in Fig. 9(b), although model A does not agree with A C–V meter is used to measure the input capacitance
the experimental data, model B agrees well with it. In this case, (Ciss ), output capacitance (Coss ), and reverse transfer capaci-
because the slope of Id−Vds characteristics in the HVHC region tance (Crss ) of the SiC MOSFET in the off-state (Vgs = 0 V)
is important for the modeling, a few points from the HVHC at Vds = 0 to 1200 V. The red broken lines in Fig. 10(a) repre-
region were used to fit the simulated curve to the experimental sent the experimental data of Ciss , Coss , and Crss, as a func-
data. tion of Vds . The gate bias dependence of Cgs and Cgd was
7320 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 9, SEPTEMBER 2018

also of the on-state devices. S-parameter data were also used for
the confirmation of the frequency dependence of the parasitic
capacitances. As explained in Section VI, Ciss of the on-state
device is necessary to reproduce its switching waveforms accu-
rately [14]. However, capacitances of the on-state device cannot
be measured by C–V meters because it is difficult to measure
the alternating current that induces the parasitic capacitance of
the device when the drain current flows. Thus, we employed
S-parameter measurement to obtain the gate–drain capacitance
Cgd , gate–source capacitance Cgs of the on-state device.
This method is often used for determining the small-signal
equivalent circuit parameters of microwave devices [15], [16].
The resulting on-state capacitances Cgd and Cgs derived
from the S-parameters are plotted with a red broken line in
Fig. 12. In the figure, Vds = 3 V and Vgs = 3 to 6 V. The sim-
Fig. 11. Evaluation board for measuring S-parameters of SiC MOSFET.
ulated curves (pale blue solid lines) of the gate–drain capaci-
tance model Cgd = Crss and gate–source capacitance model Cgs
also measured over the range Vgs = −5 to 18 V, as shown in are also plotted in Fig. 12(a) and (b). These calculated capaci-
Fig. 10(b) and (c). The parameters in the polynomial model tances are extracted solely from the off-state C–V measurements
were optimized to reproduce these C–V characteristics. First, shown in Fig. 10. Because S-parameters are measured in the fre-
the Vds dependence of Crss shown in Fig. 10(a) was fitted with quency domain, the calculated Cgd and Cgs were also plotted in
g5 (Vds ) and f36 (Vgs , Vds ) in (13) and the Cgd−Vgd characteris- the frequency domain, as shown in Fig. 12. In this study, the
tic in Fig. 10(c) was fitted with f34 (Vgs , Vds ) and f35 (Vgs , Vds ) S-parameters were measured only under limited bias conditions
in (13). Second, the Coss was fitted with the capacitance pa- because of the bias tee current limit of 2 A (PSPL5544; TEK-
rameters of the conventional pn-diode, which was added as a TRONIX). However, in the turned-on state, the drain voltage of
body diode, as shown in Fig. 1. Finally, the Ciss and Cgs−Vgs the device maintains on-voltage (near 0 V), so the S-parameter
characteristics were fitted with (11). The simulated C–V curves data at Vds = 0 to 3 V are adequate to calculate the Cgd and
are also shown in Fig. 10 as pale blue solid lines. This fig- Cgs of the on-state from the S-parameters. In addition, the mea-
ure shows that the simulated capacitances agree well with the sured Cgd data at Vgs > 6 V is almost overlapped on the data at
experimental data examined over the entire range of Vds , Vgs , Vgs = 6 V, so the date at Vgs = 3 to 6 V are adequate. Therefore,
and Vgd . we show Cgs and Cgd data at Vgs = 3 to 6 V in Fig. 12.
From Fig. 12, although the simulated curves of the Cgs agree
well with the measured curves at frequencies under 10 MHz, the
B. S-Parameter Measurement simulated Cgd curve is less than the measured data by an order
S-parameters of the SiC MOSFET were measured by mount- of magnitude. Fig. 12(c) shows the Cgd model adapted to match
ing it on a board dedicated to high-frequency response evalua- the on-state capacitance features. Comparing Fig. 12(a) and
tion. The evaluation board comprised an insulating layer made (c) clearly demonstrates that using only off-state measurements
of dielectric material (Megtron4), Copper (Cu) microstrip lines insufficiently reproduces the on-state capacitance characteris-
(characteristic impedance Z0 = 50 Ω) on the surface, and a Cu tics. By contrast, the S-parameter measurements explained here
ground plane on the backside. SMA connectors were adopted constitute a good method to reproduce the on-state capacitance
as the input and the output terminals. The configuration of the features of a switching device.
board is shown in Fig. 11, and the S-parameters were measured The vertical lines in the experimental data in Fig. 12 are
using a packaged discrete device mounted on the evaluation likely to be caused by resonance between device capacitance
board, also shown in the figure. and inductance of the wiring in the test fixture. We believe they
The measurement frequency ranged from 50 kHz to 3 GHz, have nothing to do with the characteristics of the device and
and a vector network analyzer was used for measuring the S- neglected them.
parameters. Vgs was 0 to +18 V, and Vds was 0 to +3 V, and they
were biased for generating various on-states of the device. Id =
0 to 8 A appeared under the measurement conditions employed. V. MODELING TEST FIXTURE
The phase shift in the microstrip line was corrected by auto-port- The test fixture drawn in Fig. 13(a) shows parts of the switch-
extension through the network analyzer. The S-parameters of ing measurement circuit depicted in Fig. 2. The parasitic com-
the package were obtained by using an EM simulator (EMPro; ponents in the circuit modify the switching waveforms. Thus,
Keysight Technologies, Inc.), and the S-parameters of the bare the simulation to predict the switching waveforms must appro-
die were finally obtained by de-embedding the S-parameters of priately include the parasitic components of the measurement
the package from the measurement results. system. The parasitic components are usually measured using
We utilized the S-parameter data of the bare die to acquire an LCR meter or calculated using an EM simulator, and ex-
the parasitic capacitances not only of the off-state devices, but pressed as lumped-parameter elements. However, construction
SAKAIRI et al.: MEASUREMENT METHODOLOGY FOR ACCURATE MODELING OF SIC MOSFET SWITCHING BEHAVIOR OVER WIDE VOLTAGE 7321

Fig. 13. (a) CAD model of the switching measurement circuit shown in Fig. 2.
(b) Schematic for the clamped-inductive-load-switching circuit simulated via
ADS.

describe the S-parameters of the test fixture. The SiC MOSFET

model comprise a bare die model and an equivalent circuit for
the package.
After circuit simulation in the frequency domain was com-
pleted, S-parameters were converted to the time domain via
a convolution integral method included with ADS. Thus, the
S-parameters were analyzed as a circuit component, and para-
sitic components of the test fixture were considered in the sim-
ulation of the clamped inductive load switching circuit shown
in Fig. 2.
Finally, to simulate the switching behavior of the SiC MOS-
FET, we combined all models in ADS: the intrinsic device model
extracted above, test fixture model, and SPICE models of the
Fig. 12. C gd and C gs as a function of input signal frequency. The red broken
lines are the experimental curves, and the blue solid lines are the simulated passive circuit components.
ones. V ds = 3 V. (a) Model expression of C gd in Fig. 10 is used to draw the
simulation curves. (b) Model expression of C gs in Fig. 10 is used to draw the
simulation curves. (c) Model of C gd optimized to fit the on-state experimental VI. MODEL VALIDATION
data is used to draw the simulation curves.
A. Measurement Versus Simulation
of the lumped-parameter equivalent circuit by considering all In this section, we validate SiC MOSFET model made by
parasitic components in the measurement system is tedious and this characterization technique. The validation was carried out
time consuming. clumped inductive load switching circuit in Fig. 2.
Therefore, we modeled the entire test fixture, as shown in Figs. 14–16 show the experimental results obtained under the
Fig. 13(a), calculated its S-parameters with EMPro (Finite El- operating conditions of Vds = 600 V, Id = 20 A, Rg = 5.6 Ω,
ement Method), and imported these S-parameters into the cir- and L = 500 μH, as well as their simulated counterparts. The
cuit simulator (ADS; Keysight Technologies, Inc.). A circuit measurement circuit is a double pulse tester, as shown in Fig. 3.
schematic for the simulation is shown in Fig. 13(b). The box The switching waveform was obtained using an oscilloscope
of blue squares in the figure show the circuit components that (DL7480; YOKOGAWA). Vgs , Vds , and Id were measured using
7322 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 9, SEPTEMBER 2018

Fig. 14. Switching transient experimental and simulated waveforms of V gs , V ds , and Id . The device model optimized using the Id−V ds and off-state C–V properties
were employed to obtain the simulation results. (a) Turn-on waveforms. (b) Turn-off waveforms.

Fig. 15. Switching transient experimental and simulated waveforms of V gs , V ds , and Id . The device model optimized using the Id−V ds characteristics shown in
Fig. 9 and the off-state C–V properties were employed to obtain the simulation results. (a) Turn-on waveforms. (b) Turn-off waveforms.

Fig. 16. Switching transient experimental and simulated waveforms of V gs , V ds , and Id . The device model optimized using the Id−V ds characteristics shown
in Fig. 9 and the off- and on-state C–V properties shown in Figs. 10 and 12 was employed to obtain the simulation results. (a) Turn-on waveforms. (b) Turn-off
waveforms.

differential probes (701921 and 700924; YOKOGAWA) and a Furthermore, in this section, we describe the development of
current probe (model 2877; Pearson) connected to the test fixture our device model step-by-step. First, we summarize the results
in Fig. 13. in the simplest simulation configuration in Fig. 14. In the figures,
In Figs. 14–16, (a) shows turn-on waveforms, and (b) shows the employed device model (model A) is optimized using the
the turn-off counterparts. The broken lines denote the experi- off-state capacitance properties shown in Fig. 10 and the Id−Vds
mental data, and the solid lines show the simulated waveforms. properties obtained using the CT shown as dotted blue lines in
SAKAIRI et al.: MEASUREMENT METHODOLOGY FOR ACCURATE MODELING OF SIC MOSFET SWITCHING BEHAVIOR OVER WIDE VOLTAGE 7323

Fig. 9, ignoring the data shown in Figs. 9(b) and 12(c). This
means that the device model used in Fig. 14 do not follow the
on-state capacitance characteristics and the Id−Vds curves in the
HVHC range. Consequently, this device model does not present
the time lags and the rise and fall times; in addition, it does not
show sufficiently the ringing of the waveforms.
Next, we use the device model (model B), which reproduces
the static Id−Vds characteristics shown as blue solid lines in
Fig. 9, but follows only the off-state C–V characteristics in
Fig. 10. The results are shown in Fig. 15. This model success-
fully improves the turn-on time lags, Vds decreasing gradient,
and Id increasing and decreasing gradients in comparison with
the first device model described above. However, the turn-off
time lags of the waveforms of Id and Vds , which are about 40 ns,
remain. Because the turn-off time depends on the discharge time
of Ciss and the MOSFET is active (in the on-state) before the
turn-off period, the turn-off time depends on the Ciss of device
when it is on-state. Thus, we hypothesize that this mismatch is
caused by the insufficient modeling of the on-state Ciss charac-
teristics. Ciss is expressed as follows:

Ciss = Cgs + Cgd . (21)

We considered that the Cgd and/or Cgs of the on-state de-

vice might be different from the Cgd and/or Cgs of the off-state
device measured by the C–V meter [14]. Unfortunately, be-
cause we cannot measure the capacitance of the on-state of the
device by using a conventional C–V meter, we measured the
S-parameters of the SiC MOSFET and derived the Cgd of
the on-state device from the S-parameters by using a π–
equivalent circuit topology. From this analysis, as for Cgs , we
confirm that the modeled on-state Cgs was matched to the mea-
sured on-state Cgs , as shown in Fig. 12(b). Conversely, we found
that the modeled Cgd did not match the measurement data, as
shown in Fig. 12(a). Herein, two methods are available to match
the modeled Cgd to the measured Cgd . While one method is
changing the model parameters, the other is changing the model
equations. Because the simulated off-state capacitances were
already matched very well to the measured ones, as shown in
Fig. 10, we modified the Cgd model equation without changing
any model parameters. However, because the Qgd equations (13)
and (15) were already rather complex, we modified an existing
variable in the Qgd equations (13) and (15). In concrete terms,
we changed Vds to Vds − Vgs = Vdg in (14) and (16). Because
Vdg = Vds in the off-state (Vgs = 0 V), the off-state parameters
did not need to be changed.
Finally, we use the device model C that considers the on-state
capacitance shown in Fig. 12(c), and the results are summarized
in Fig. 16. The turn-off time lags in the waveforms of Id and Vds
disappear. This shows that the on-state capacitance properties
of the device significantly affect the way in which the device Fig. 17. RMS errors defined by (22) are shown as functions of V ds , Id , and R g
transitions from the on-state to the off-state. Furthermore, the in subpanels (a), (b), and (c), respectively. The common experimental settings
for each case are described at the top right corners of the graph panels. The
change of g5 (Vds ) to g5 (Vdg ) was sufficient to run out the turn- solid lines denote the RMS errors obtained using the proposed device model,
off time lags and match the simulated capacitance-frequency whereas the broken lines denote the results obtained using the conventional
curves to the measured ones under 10 MHz in Fig. 12(b) SPICE device model. (a) RMS errors as a function of V ds . (b) RMS errors as a
function of Id . (c) RMS errors as a function of R g .
and (c).
7324 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 9, SEPTEMBER 2018

B. Comparison With Conventional SPICE Model nents of the package and to develop a computational model of
the test fixture.
To further demonstrate the advances facilitated by the pro-
posed measurement and modeling techniques, we compare the To demonstrate the validity and usefulness of the newly ob-
tained measured data, we deployed a custom version of the
new model with the conventional SPICE model, that is, the
Angelov–GaN RF model, modified to account for power SiC
equation-based model published on the ROHM website [17].
Fig. 14 shows only the switching waveforms when the de- device behavior. The model can be extracted by using these new
measurement techniques.
vice operates at Vds = 600 V, Id = 20 A, and Rg = 5.6 Ω, but
The new model can predict switching waveforms of the SiC
the model can also predict the switching behavior in other volt-
age and current ranges. Here we verify that our model can MOSFET device under wider voltage and current operation
conditions, and it is significantly more accurate than the existing
reproduce measurement waveforms in the operating ranges of
Vds = 200 to 600 V, Id = 10 to 40 A, and Rg = 0 to 20 Ω. SPICE models across different bias conditions. In conclusion,
In addition, we use the relative RMS error to validate quanti- because this novel measurement and modeling technology can
tatively the capability and general versatility of the model. predict switching waveforms accurately, we believe the solution
The RMS error used herein is given as follows: is valuable for simulating power electronic circuit performance,
including estimating precisely their power conversion efficiency
 and EM noise.
N 2
i=1 |mi − si |
Relative RMS Error =  N 2
× 100 [%] (22)
i=1 |mi |
ACKNOWLEDGMENT
The authors are deeply grateful to Dr. Roberto Tinti and
where i, mi , si , and N denote the number of data, measured Dr. David Root of Keysight Technologies, Inc., for their valuable
and simulated values (Id , Vds , and Vgs ) at the i-th data point, comments and discussion.
and total number of data points, respectively. The time domain
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Hiroyuki Sakairi was born in Tochigi, Japan, in

1982. He received the B.S degree in applied physics
from Tokyo University of Science, Tokyo, Japan,
in 2007, and the M.Eng. degree in material science
from Nara Institute of Science and Technology, Nara,
Japan, in 2009.
He joined ROHM Co., Ltd., Kyoto, Japan, in 2009. Hiroaki Tanigawa received the B.S. degree in
From 2009 to 2012, he was engaged in development electronics engineering from Fukuoka University,
of SiC power devices, and since 2013, he has been Fukuoka, Japan, in 1997.
working in the development of system applications In 2001, he joined Keysight Technologies Japan
of power devices and modeling power devices. G.K. (formerly Agilent Technologies Japan), Tokyo,
Japan, where he had a role as a semiconductor device
modeling. He is currently a Global Services and Sup-
Tatsuya Yanagi (M’14) was born in Osaka, Japan, in port Engineer for EEsof EDA Organization, Keysight
1985. He received the B.Eng. degree in electrical and Technologies Japan G.K. His current research inter-
electronic engineering and M.Eng. degree in electri- ests include electrical characterization/modeling of
cal engineering from Kyoto University, Kyoto, Japan, III-Nitride devices and power semiconductor devices.
in 2010 and 2012, respectively.
He joined ROHM Co., Ltd., Kyoto, Japan, in 2012.
His research interest includes the behavior of power
devices, Si, SiC and GaN power devices, in power
converter circuits.

Hirotaka Otake was born in Chiba, Japan, in 1981. Ken Nakahara (M’12) was born in Hyogo, Japan, in
He received the B.Eng. and M.Eng. degrees in ap- 1972. He received the B.S. degree in physics from
plied physics from Waseda University, Tokyo, Japan, Kyoto University, Kyoto, Japan, in 1995, and the
in 2004 and 2006, respectively. Ph.D. degree in chemical from Tohoku University,
He joined ROHM Co., Ltd., Kyoto, Japan, in 2006. Sendai, Japan, in 2010.
From 2006 to 2011, he was engaged in the develop- He is the Division Manager of the Research and
ment of GaN power devices, and since 2011, has been Development Division, ROHM Co., Ltd., Kyoto. His
engaged in the development of power modules and current research interests include power devices and
circuits using SiC devices. their applications.