Gate Charge Control of High-Voltage

Silicon-Carbide (SiC) MOSFET

in Power Converter Applications
S. Musumeci
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Abstract— Switching devices such as Silicon Carbide size and costs in an extended range of converter
(SiC) MOSFET present significant performance applications such as industrial motor control, induction
improvement in high frequency switching power converter heating, industrial power supplies and renewable energy
applications. This paper presents a gate charge profile
conversion [2]. In order to investigate the performance of
investigation of a Silicon Carbide MOSFET and gate driver
circuit solutions to optimize both switching speed, power SiC MOSFET in high switching frequency applications it
losses and EMI requirements. Main technology issues of is crucial the proper knowledge of driving technique to
Silicon carbide MOSFET are presented in order to optimize switch performance choosing a suitable power
understand the correlation between the technology solutions MOSFET driver. The switching performance are
and the switching performances. Driver circuit influenced by the rate of charge of the MOSFET intrinsic
requirements are highlighted and discussed. A Miller
capacitance. Through the gate charge investigation it is
plateau identification method is presented. An
independently circuit control principle of drain current and achievable the control of the main parameters involved in
drain-source voltage is presented and discussed. The switching operations. The correct design of gate drive
circuital technique allows a positive impact on the reduction circuit through the management of gate charge leads to a
of power losses and electromagnetic interferences level. proper control of both drain-source current and voltage
behavior. The optimum design of switching driver circuit
Index Terms-- SiC MOSFET, Gate Charge, Driver must hold together the control of both the rate of current
Circuit, power converter.
rise, to reduce the electromagnetic interference (EMI) and
I. INTRODUCTION the control of the rate of voltage rise to avoid voltage
peaks, on the other hand it is necessary to reduce the
Silicon-carbide (SiC) MOSFETs have been introduced power losses in order to optimize the efficiency. Circuit
in the power electronics applications during the last years.
techniques are often used to actively controlling the dv/dt
Due to superior material characteristics, silicon carbide and di/dt insulated gate devices through the management
leads to high breakdown electric field strength resulting of gate charge injecting a suitable gate current in order to
in high voltage-blocking capability with a lower on-
handle electromagnetic interference (EMI) and reducing
resistance compared with standard Si, while its large voltage peak without using passive lossy snubber circuit
band-gap energy leads to higher temperature operation [3]. Driver circuit standard solution is done by two
capability, higher radiation hardness, and relatively
simply gate resistance in order to turn on and turn off
higher thermal conductivity. SiC MOSFET according to
separately the device. Enhanced driving circuit technique
best performance in operating conditions, compared to is necessary to improve performance and reliability in
traditional Silicon (Si) based MOSFET built with silicon power converter applications. In the paper gate charge
technology, makes it well-suited device for power
control of Silicon Carbide MOSFET is investigated in
electronics switching circuits in medium power range order to give design guidelines that improve the
applications [1]. In switching conditions SiC MOSFET switching performance of the device in converter
reduces conduction losses and allows an extremely low
applications. 1200V, 20A SiC MOSFET is investigated
power switching losses that leading to reduction of in several driving conditions and gate charge correlation
cooling requirements and heatsink volumes. Moreover with dynamic behavior of the output voltage and current
switching performance improving of silicon carbide
are shown.
devices allows to obtain high operating frequencies with
consequently reduction of bulky inductive components in II. SIC MOSFET TECHNOLOGY OVERVIEW
power converter circuit. Furthermore according to the
Based on the advanced and innovative properties of
increase of junction temperature up to 200°C an extended
wide bandgap materials, SiC MOSFETs, compared with
reliability is obtainable.
silicon (Si) MOSFETs, achieve large reductions in energy
Consequently of dynamic characteristics SiC
consumption which results in lower leakage currents and
MOSFETs can improve overall converter system
higher operating temperatures. SiC components have
efficiency with consistent reduction on the whole system

978-1-4799-8704-7/15/$31.00 ©2015 IEEE 709

higher advantages as follows: 4V B2
xWider energy bandgaps, that leads to much lower R DS _ on (1)
leakage currents and higher operating HP n E C3
temperatures. where VB is the breakdown voltage and Ec is the critical
xHigher critical electric fields, thus the devices electrical field. Based on the equation (1) RDS_on is
can have higher doping concentrations with reversely proportional to Ec, hence higher Ec leads to a
thinner blocking layers, and consequential much lower RDS_on. Moreover SiC MOSFET's have
lower on-resistance. positive temperature coefficient that allows easy
xHigher electron saturation velocity, resulting in paralleling to obtain higher operating currents. Only the
high costs for SiC devices are a significant limit at the
higher operating frequencies compared to
moment.
similar silicon-based devices.
x Better thermal conductivity compared with Si TABLE I
devices which improves heat spreading and COMPARISON OF SI AND SIC MATERIAL PROPERTIES
Property Si 6H-SiC 4H-SiC
allows operation at higher power densities.
Bandgap eV (at 300
The main features of silicon carbide MOSFET and 1.12 3.0 3.2
K)
benefits on applications are described in the following: Critical electric field
2.5×105 2.5×105 2.2×105
x Industry's highest temperature rating of 200 °C Ec [V/cm]
Thermal conductivity
with a benefit of improved thermal design. Ȝ (W/cmK at 300K)
1.5 3-4 3-4
x Low on-state resistance over the full Saturated electron
temperature range to 200 °C with drift velocity, vsat 1×107 2×107 2×107
[cm/s]
consequently reduction of cooling Electron Mobility, P n
requirements. 1350 500 950
(cm2 / V×s)
x Switching losses reduction and enhanced Hole Mobility, P p
480 80 120
switching frequency allowing smaller size of (cm2 / V×s)
Dielectric constant Hr 11.9 10 10
passive components and compact design.
x Fast and robust intrinsic diode. No external III. STATIC AND DYNAMIC CHARACTERISTICS OF
diode is necessary. SIC MOSFET
The structure of a vertical SiC MOSFET and the
The SiC MOSFET tested is a 20A, 1200V device with
similar technology solution in Si device are shown in Fig.
1 a) and b) respectively, where it is possible to note the RDSon=169m: measured at 25°C from
very thin drift layer thickness of SiC devices compared STMicroelectronics (SCT20N120) in HiP247 package.
with an equivalent Si MOSFET. Moreover the carrier A. Static Characteristics
concentration in the drift layer region of SiC structure is The internal gate resistance is a critical parameter in
very high which result in drastic reduction of on-state the design of gate driver circuit. The intrinsic resistance
resistance. Silicon carbide chemical structure is realized of the gate (RG_Intrinsic) depends on the resistance of the
in several polytypes. 4H-SiC is the most utilized for material used to build the contact and the size of the chip;
power devices because its properties are superior to those to parity of the other parameters the intrinsic resistance is
of other polytypes of silicon carbide such as 3C-SiC, 6H- inversely proportional to the size of the chip and thus
SiC [4]. The key materials properties are listed for the decreasing the chip size there is an increase of the
main wide bandgap semiconductors SiC compared with resistance. By a measurement with LCR meter the
Si in Table I. intrinsic gate resistance value is achieved.
RG_Intrinsic=7.76: at 1MHz and junction temperature
Tj=25°C. The experimental measurements of the
capacitance curves through LCR meter versus drain-
source voltage are reported in Fig. 2. Measurement
conditions: (VDD=1000V, VGS=0V, f =1MHz, Tj=25°C).
B. Dynamic Characteristics
The SiC devices show an intrinsic capacitance lower if
compared with the components in the standard silicon
technology, which means that the silicon carbide devices
have best switching speed than Si MOSFET. In a half-
Fig. 1 SiC MOSFET structure a) compared with b) Si MOSFET
structure. bridge configuration this high switching speed can create
On-resistance (RDS_on) is a critical parameter for resonance with parasitic elements of the circuit (damped
MOSFET devices because it is directly correlated to the oscillations) and forced commutations are possible
power losses during the conduction time. Ron can be because the potential of the channel is modulated by the
calculated from equation (1) current that flows through the gate.

710
Fig. 2. Experimental curves of input and output capacitances versus
drain-source voltage.
Fig. 3. SiC MOSFET drain current and drain source voltage turn off
switching waveforms. ID=5A/div, VDS=200V/div, Pon=5kW/div,
Another phenomenon that can take place are self- t=20ns/div.
sustaining oscillations to the turn-off of the transistors in
the half-bridge low side. This problem can destabilize the
circuit and even destroy the devices under certain
conditions. This trouble conditions may be overcome by
turning off the device with a negative voltage VGS_off (e.g.
-5V).
Although the drift region of the SiC MOSFET shows a
lower resistance than the silicon devices, the lowest
carrier mobility in the SiC leads to a higher channel
resistance. For this reason the increase of the gate voltage
causes an increase of the resistance in on state, which
goes progressively to saturate with the increase of VGS up
to the overcoming of 20V. Usually for the Si MOSFETs
and IGBTs are used VGS equal to 10V and 15V
respectively; to these voltage values SiC MOSFETs do
not show low resistance and therefore it is advisable to Fig. 4. Energy losses during turn-on and turn-off transients versus gate
apply voltages equal to or above 20V thus reducing the resistance variations at 150°C, VDD=800V, ID=5A.
resistance in on state. Experimental tests are carried out
in order to evaluate switching performances and power Switching transient power losses are approximately
losses of SiC MOSFET. An experimental set-up is given by (3):
arranged in order to supply a double pulse with adequate
t sw _ on ˜ V DS ˜ I D ˜ f s
gate current level. In Fig. 3 turn off switching waveforms PSW 
are reported. The experimental tests are carried out with a 2
(3)
VDD= 800V and ID=10A, RG_on=RG_off=RG=10:, T=25°C. t sw _ off ˜ V DS ˜ I D ˜ f s
As freewheeling diode is used a same type SiC MOSFET 
connected in parallel to inductive load. The power losses 2
are a crucial point for MOSFET devices applications. The where tsw_on /tsw_off is the time it takes to turn the MOSFET
power dissipated in a MOSFET mainly depends on the on / off. Notice that, VDS_ is the drain source voltage
follow parameters: gate resistance RG, on-state resistance when the MOSFET is off [5]. Also the drain-source
RDS_on, switching frequency fs and operating temperature parasitic capacitance (Coss) charging/discharging during
T. The characterization of energy losses SiC MOSFET at transients operation produces losses as shown in equation
150 °C versus gate resistance is reported in the Fig. 4. (4). The effect on power losses of input capacitance and
The power losses are the sum of different contributions: reverse transfer capacitance compared to the output
capacitance is negligible.
power losses during conduction time (Pcond), power losses
2
during turn-on transient and during turn-off transient PCoss V DS ˜ C oss ˜ f s (4)
(Psw), power losses on the output capacitance Coss (PCoss) At the output power must sum the power dissipated in
and finally losses in the gate circuit PG. Pcond is strictly the gate circuit, given by the following expression (5).
related to on-state resistance RDS_on and the drain current RG _ Intrinsic
level in on-state ID as shown in (2): PG VGS ˜ QG ˜ f s ˜ (5)
RG _ Intrinsic  RG
2
Pcond ID ˜ R DS _ on (2)
were RG is the gate resistance connected to the driver

711
circuit, RG_Intrisic is the internal gate resistance of the dI D g m ˜ I G g m ˜ I G
devices. These type of power losses typically negligible # | (9)
dt CGS C iss
become significant with increasing switching frequency
In the second step of gate charging process (t2), also
above 100kHz.
called “Miller plateau”, the drain current remains
The energy losses increase with temperature while the
constant at ID_C and also gate voltage is constant thus the
power losses are higher with increasing switching
time derivative of VGS is equal to zero. Therefore the gate
frequency. The reduction of power losses is obtained by
current and output voltage slope are related by:
lowering the gate resistance in order to increase the
dV DG dV DS
switching transient or in other way it may act by reducing I G C GD CGD (10)
the switching frequency at the cost of the increase of the dt dt
size of the passive components. On the other hand the From equation (10) it can be noticed as the slope of
reduction of the gate resistance increases the rate of rise VDS depends on CGD and since it increases with
of drain current during the transient and this enhances the decreasing of voltage VDS (as shown in Fig. 5 b), the slope
content of electromagnetic interference. have to decrease. During time t3 drain-source voltage VDS
Hence a trade-off is necessary that holds together all remains at a small value equal to conduction voltage. VGS
these requirements. Moreover it is possible to optimize continues to increase proportionally to the charging
the performance of the device by acting on the current current and the equation related to IG and gate voltage
supplied to the gate through the control of the profile of variation is again (7). The description given suggests that
gate charge. the study of the gate-charge gives crucial information on
the behavior of switching transients.
IV. GATE CHARGE INVESTIGATION
The MOSFET analysis behavior during the switching
transient is strongly influenced by the capacitances
present in the structure of the device. The gate current
during the switching has the typical behavior of the
current in an RC circuit. In order to better understand the
phenomena that occur during switching, it is preferred to
refer to the curve "gate charge", obtained by using for the
driving of the MOSFET a current generator.
A schematic of gate charge measurement setup is
shown in Fig. 5 a). A constant current source of IG is
applied to the gate and charging the gate capacitances.
The gate current IG is related to charge quantity as
shown in (6):
dQG t  Fig. 5. a) schematic of gate charge measurement set-up. b) qualitative
IG (6) gate charge waveforms.
dt
A gate charge curve with drain voltage and current
In actual operating conditions to the gate is supplied a
behavior is shown in Fig. 5 b). Supplying a constant gate voltage VGG, through a resistor RG, thus the variation of
current IG the gate voltage VGS begins to increase. Since the current IG is not constant as in gate charge curve. The
VGS is below threshold voltage VTH there is no current
gate voltage grows exponentially with time constant W
flowing between the drain and the source. After VGS rises
given by the group RC related to input inner capacitances
beyond the threshold voltage the current ID start to flow
of device and gate resistance. The current IG, calculated at
up to reach its maximum value ID_C while VDS is set at
the beginning of the area Miller has the following
VDD from freewheeling diode, as long as the current ID
expression:
does not reach the final value established by the external
circuit. Since VDS is fixed (during time t1) we have (7):
VGG  VMiller 
IG (11)
dVGS RG
I G C GS (7) with:
dt
In this step CGS and CGD have constant value. The gate I
V Miller VTH  D (12)
voltage start from VTH and reaches the value given in (8): gm
I Equation (11) can be replaced in (9) to obtain the current
VGS VTH  D (8) ID slope:
gm
dI D g m ˜ I G g m ˜ VGG  V Miller 
where gm is the MOSFET transconductance. # | (13)
The change in the slope of the current ID, is due to gate dt C GS RG ˜ C iss
charge during this phase, and is defined, with good The curves relating to the actual situation and the test
approximation, by the relation: circuit comprising the parasitic inductances are illustrated

712
in Fig. 6, where it is possible to note how the peak current VDD assigned. Typical waveform of the gate charge of the
through the capacitance CGD is reflected also above the SiC MOSFET tested is shown in Fig. 7. In the same
gate voltage. The same considerations can be drawn for figure the switching waveforms of drain-source voltage
turn-off switching transient. and drain current are also reported at following
measurement conditions: VDD=800V, VGG=20V,
ID_C=10A. To obtain the charge from the time read on the
oscilloscope is necessary to multiply by the value of the
constant gate current (IG=1.6mA). In Table II the gate
charge quantity and the time related are reported. The
knowledge of gate charge quantity allows to design the
driver circuit and modulate the IG current in order to
control both drain current and voltage slope to reach an
optimization of switching transients [6].
In Fig. 8 a simple driver circuit is shown with the turn-
on waveforms, considering the turn-on transient the
Fig. 6. Turn on Typical waveforms at of a MOSFET and effect of stray knowledge of gate charge allows to calculate the gate
inductances in a inductive load switching circuit. resistance required by the equation (15) related to driver
From the equation (13), taking into account the circuit shown in Fig.9:
parasitic inductances, the time derivative of the drain RG _ on

VGG  VTH  VCE _ sat ˜ 't (15)
current is changed as follows: QG
Vice versa by using the value of the gate resistance can
dI D V  VMiller  find the time required for the device turn-on.
| GG (14)
dt § R ˜C · From Fig. 3, taking into account the charge ignition
¨ L s  G iss ¸
¨ g m ¸¹ time that is approximately 40n seconds, from equation
©
(15), and handling Table II data is obtained a gate
The expression, thus found, shows all the parameters
resistance of 10: (from experimental characterization
involved in the definition of the drain current slope.
VTH = 3V and VCE_sat depicted in Fig. 9 is fixed to 0.5V).
These parameters can be thus divided:
xinternal parameters of the device: Ciss, VTH and gm.
xdriver circuit parameters: VSS, RG and Ls.
The internal parameters of the device are fixed. Only
driver parameters can be chosen to control the slope of
the drain current. The lay-out optimization is crucial to
minimize the contribution uncontrollable of parasitic
inductance Ls. The control strategy of the dID/dt is
implemented through the choice of the resistance RG,
setting the driver circuit gate voltage, VGG. The above
considerations are very significant in order to optimize
the performance of MOSFET device. Moreover switching
transients generate conducted EMI with amplitudes
directly related to the time variation of the drain current.
Through the resistance RG it is possible to control the
switching speed during both turn-on and turn-off Fig. 7. Gate charge waveforms. VDS=200V/div, VGS=5V/div,
switching transients, as well as the current peak due to the ID=5A/div, t=5—s/div.
freewheeling diode, consequently the device power loss
and the EMI can be managed by a suitable choice of gate TABLE II
GATE CHARGE VALUES AT VDD=800V, VGG=20V, ID_C=10A
resistance.
QG [nC] t[Ps]

V. DRIVER CIRCUIT DESIGN ISSUES QGS 7.12 t1 4.45

The control of the gate charge is carried out through QGD 22.8 t2 14.25
the injection of current in adequate quantity to control the
rate of rise/fall of the output current and/or voltage QG  't 31
according to the application request for reducing power
losses and having lower electromagnetic interference. A. Miller Plateau Identification
The gate charge allows to know the amount of charge to In order to control the dID/dt and dVDS/dt both at turn-
be supplied to the gate to bring its voltage from 0 to VGG on and turn-off transient it is necessary to have
and to switch the device in correspondence with ID and information on the Miller plateau and in particular to

713
discriminate the start of this flat area to have the ability to From the driver conditions and the device parameters
act independently on the slope of drain-source voltage it is possible to design a RC network to identify the
and drain current. The method of detection the beginning starting point of Miller plateau [7]. Parametric simulation
of Miller plateau is based on time derivative of "gate- results performed with PSpice software are shown in the
charge" curve. Deriving theoretically gate voltage, the Fig 10. In Fig. 10 a) is shown a cycle of commutation of
curves of Fig. 9 b) are obtained. The same method can be a gate voltage and the high-pass filter output. RC network
used to turn-off. response is shown with three different cases of study. A
turn-on zoomed view is shown in Fig. 10 b) while the
turn-off zoomed view is reported in Fig. 10 c).
Simulations were conducted taking into account the time
constant to be obtained. In our case study a capacitance
was settled to 1nF and three simulations were conducted
with three different resistances 10, 50 and 100 Ohm. As
shown in Fig 10 b) the simulation with the lowest value
produces a voltage of a level sufficient to be
discriminated. The next value of resistance produces a
higher peak still better usable while the last value of
Fig. 8. MOSFET driver circuit and turn-on waveforms. resistance does not produce a useful signal. The
simulation results show the effectiveness of the technique
The real circuit, to carry out the process of the used.
derivative of the gate voltage, must be as simple as
possible and have very fast response times because the
phenomena has a duration of tens of nano seconds. The
reasons listed have led to the choice of an RC circuit, in
the configuration of the high pass filter (Fig. 9 a), which
makes a time derivative function approximated by
converting the variations of the slope of the gate in a
series of positive and negative pulses as shown in Fig. 9
c).

Fig. 10. Simulation results a) Gate voltage VGS, t=2Ps/div

VGS=20V/div. b) Zoomed view of turn-on, VGS=10V/div,
t=20ns/div. c) Zoomed view of turn-off, VGS=10V/div,
t=200ns/div.

B. Independent Drain Current and Voltage Slope

Control Technique.
The drain-source voltage and the drain current slope
can be controlled independently through auxiliary
generators that are controlled by the signals coming from
Fig. 9. a) RC high pass filter circuit schematic. b) Theoretical
derivative waveforms of gate voltage. c) Actual derivative pulse
sensing voltage obtained from the network RC. During
waveforms of RC network response. the first slope of the gate voltage turn-on transient the rate
Managing a RC network charge/discharge equation of charge supplied to the gate establishes the drain current
and knowing the relationship between gate current and slope. During the Miller plateau of the turn-on transient
Miller voltage is possible to know the derivative voltage the rate of charge supplied to the gate imposes the
peak (VRC0) with the following mathematical relation (16) collector-voltage slope. The principle of operation of a
gate charge controller circuit is depicted in Fig. 11where
§ D 1 ˜ Miller ·¸
V
¨ the conventional drive circuit supply a rate of charge
V RC 0 D ˜ R ˜ C ˜ ¨1  e RC
¸ (16)
¨ ¸ through the gate resistance RG_on obtaining the slow dv/dt
© ¹ shape. Faster fall dv/dt shapes of VDS are obtained
where D is: enabling additional current generator at two different
VGG current pulses of 500mA and 1A. With this technique, as
D (17) shown in the simulation results of Fig. 11, it is possible to
RG ˜ Ciss

714
accelerate the voltage-drain variation, and thus the Other problems to consider are electrical noise that,
switching speed without increasing the drain-current through the parasitic capacitances, may enables
slopes and EMI levels. The drain current slope does not inadvertently additional generators. To avoid this
change because it is imposed by the rate of charge problem is crucial the separation of turn-on and turn-off
established by RG_on in the first gate voltage slope. Same circuit path in order to enable separately the additional
effect is obtained with a current sink at turn-off transient, generators.
as shown in Fig. 12. The time shift of the drain current
fall, as well as of drain-source voltage rise, is due to the VI. CONCLUSION
Miller effect reduction caused of added current sink In this paper a 1200V, 20A SiC MOSFET was
action. characterized. From the characterization results it is clear
The voltage pulses obtained from the sensing circuit that MOSFET behavior during the switching transient is
cannot be used directly to operate the auxiliary circuits, strongly influenced by the capacitances present in the
but must be processed further to obtain signals of suitable structure of the device and its charging profile. The curve
amplitude and time duration. Between the RC network of the gate charge has been investigated to understand the
identification (sensing) of the Miller plateau and the relationship between the slope of the drain current and the
additional generator current must be interposed an drain-source voltage with the gate current supplied
enabling circuit which intervenes in suitable time and through the driving circuit. The main issues on drive
gives appropriate trigger signal. The same consideration circuit requirements have been explained taking into
must be done during the turn-off cycle to trigger the account power losses reduction and EMI requirement. A
auxiliary discharge circuit. The technique is much more Miller effect identification technique has been discussed
effective if the amplifiers are very fast, in order to in order to control independently drain current and drain-
synchronize the operation of the additional generators source voltage slope of a MOSFET device.
instantly wanted.
ACKNOWLEDGMENT
Author would like to thank Dr. F. Portoghese and Dr.
D. Cristaldi for their cooperation on experimental results.

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