Received: 6 June 2021 Revised: 22 December 2021 Accepted: 19 January 2022 IET Power Electronics

DOI: 10.1049/pel2.12253

ORIGINAL RESEARCH

A highly efficient power block with series connection of power

SiC MOSFETs-design, characterization and assessment in
MV converters

Chengmin Li1 Zhebie Lu1 Ankang Zhu1 Chushan Li2 Haoze Luo1
Wuhua Li1 Xiangning He1

1
College of Electrical Engineering, Zhejiang Abstract
University, Hangzhou, China
Implementation of the series connection of the SiC MOSFETs in medium voltage (MV)
2
Zhejiang University – University of Illinois at high power converters faces a series of challenges, including the electrical/thermal stress
Urbana-Champaign Institute, Zhejiang University,
Haining, China
imbalance, insulation coordination design, high dv/dt elimination and robustness under
variable operating conditions. This paper stresses these challenges and proposes a compre-
Correspondence hensive design of a 9.6 kV/200 A power block based on the series connection of SiC MOS-
Chushan Li, Zhejiang University – University of FETs. The power block has been verified under the continuous operation, which demon-
Illinois at Urbana-Champaign Institute, Zhejiang
strates the highly efficient and reliable operation under the variable switching current con-
University, Haining, China.
Email: chushan@intl.zju.edu.cn dition. Afterward, performance screening in a 5 kV/1 MW inverter is conducted to assess
the efficiency in MV converters. Compared with the advanced high voltage high power
Funding information devices, the proposed power block demonstrates fast switching speed and low switching
National Nature Science Foundations of China, loss, which indicates that the series connection of SiC MOSFETs is a promising technique
Grant/Award Numbers: 51877192, U1834205;
Zhejiang Provincial Natural Science Foundation of to expand the operation voltage/power of the SiC MOSFETs to the MV megawatt level.
China, Grant/Award Number: LZ22E070002 The proposed design can be expanded to other specifications as well.

1 INTRODUCTION as 1200 and 1700 V [5]. Such a tendency is driven by grow-

ing applications such as the electric vehicle and the IT indus-
The rapid growth of the medium voltage high power convert- try. In contrast, the application of high voltage SiC MOSFETs
ers in supercharging stations, renewable energy systems, data in the medium voltage range is still limited. Until so far, some
centres and transportation electrification has drawn a growing samples of 10 kV SiC MOSFET are supplied by companies
need for high-performance power converters [1–4]. In a wide [6, 7]. Several works report the evaluation of the high voltage
range of emerging applications, the volume/footprint is often SiC devices, including unipolar and bipolar SiC devices. Ref. [8]
highly constrained and hopefully, bringing economic benefits. gives a thorough assessment of the 10 kV/100 A SiC MOS-
Such requirement is not commonly demanded in bipolar silicon FET power modules and demonstrates superior performances
devices based medium voltage solutions, which is always limited of HV SiC MOSFETs. 15 kV SiC IGBTs are adopted in a MV
by the large switching loss of the power devices. As the emerging DC/DC converter in [9]. 10 kV SiC MOSFETs are adopted in
next-generation power devices, the applications of SiC MOS- MV AC to LV DC converter [1]. An MV 200 kW inverter based
FETs are growing rapidly. SiC MOSFET has high voltage, high on the series connection of the 10 kV SiC MOSFETs is pro-
temperature or high switching frequency operation capability, posed in [10]. The concept of a 40 kV/300 kVA quasi-two-level
making it attractive in high power medium voltage converters integrated power module is proposed in [11]. These researches
with appropriate design consideration [4]. demonstrate the potential that SiC MOSFETs can operate at
However, the commercial applications of SiC MOSFETs are high voltage. However, high voltage devices face a series of chal-
mainly concentrated in the relatively low voltage classes, such lenges in terms of reliability issues and cost [6, 12, 13].

This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the
original work is properly cited, the use is non-commercial and no modifications or adaptations are made.
© 2022 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.

IET Power Electron. 2022;15:605–620. wileyonlinelibrary.com/iet-pel 605

606 LI ET AL.

Generally, the application of high voltage SiC MOSFETs in converter. However, for a general case, previous work lacks a
medium voltage applications is relatively slow compared with thorough analysis on the dynamic performance of the series
that of the low voltage devices. When the blocking voltage connection of power devices (both active devices and the free-
increases, the on-state resistance of the device increases dramat- wheel diodes), including the switching loss/speed under various
ically. For SiC MOSFETs, the specific on-state resistance of SiC operation conditions, continuous running under variable load
MOSET is proportional to VBR 2.43 (VBR , breakdown voltage) currents and integration into the medium voltage high power
[14, 15], which reduces the efficiency of SiC MOSFETs in high converters.
blocking voltages. Another option is to use bipolar connection In the series connection of SiC MOSFETs, dealing with the
SiC devices such as SiC IGBT [16]. However, SiC IGBT faces extremely fast switching within a compact space is the crit-
challenges in the device fabrication technologies and is far away ical challenge. The paper proposes a comprehensive design
from commercially available [6]. approach of the critical elements related to the voltage balanc-
As a compromise, the series connection of low voltage ing, auxiliary power supply and insulation coordination design in
devices to achieve higher blocking voltages is viewed as another the series connection of SiC MOSFETs. These considerations
solution [17, 18]. Owing to the limitation of the theoretical on- are critical details that must be overcome in implementation.
state resistance of SiC MOSFET, the specific on-state resis- However, many of them are not sufficiently explored in pre-
tance of the series connection is smaller than single high voltage vious works. To promote the feasibility of the series connection
device under high blocking voltage condition [14, 15]. Besides, operation of SiC MOSFETs, a 9.6 kV/200 A SiC power block
due to the wide applications, low voltage devices have more based on the series connection of SiC MOSFETs is built and
suppliers and are more accessible compared with the high volt- tested at 330 kW leg output power. Further, the performance
age devices, and consequently, reducing cost. Therefore, it is an of the converter under a three-phase 1 MW, 5 kV DC condi-
attractive solution to realize the high blocking voltage based on tion is assessed under various operating conditions. Although
the series connection of low voltage devices. the demonstration in the paper is a specific 9.6 kV/200 A power
Compared with the widely applied series connection of Si module, the design method is overall general and can be adapted
IGBT devices, the obvious benefit of the series connection of to other specifications. It is verified that the designed power
SiC MOSFET is the lack of the turn-off tail current, which is block has very good performances compared with its coun-
viewed as the main source of the voltage imbalance among the terparts (Si IGBTs and high voltage SiC MOSFETs), which
Si devices [19]. However, it is also challenging to connect the is a promising selection for the next generation high power
SiC MOSFETs in series. The gate driving strategy and voltage converter.
imbalance are the main issues. And the fast-switching speed
makes the devices more sensitive to the parasitics in the cir-
2 DESIGN OF 9.6 KV/200 A SIC POWER
cuit. For example, [20, 21] find that the stray capacitance among
BLOCK
the devices and components is one of the causes of the volt-
age imbalance. The authors in [21–23] have been working on
To investigate the potential of the series connection of SiC
these topics and propose different solutions, mainly focusing
MOSFETs, the critical issues related to voltage balancing, insu-
on the active voltage balancing method to solve the challenge of
lation coordination, thermal dissipation, isolation, and gate driv-
the voltage sharing among the devices. Generally, the gate-
ing must be solved. However, the high speed and high volt-
source voltage and gate driving delay time are the two main
age switching bring a higher challenge to the solutions. In this
control freedoms in the feedback loop [24–26]. Considering the
section, a 9.6 kV/200 A SiC power block, which contains the
various efforts in exploring the series connection of SiC MOS-
control, driving, and cooling embodiments, is designed to solve
FETs, however, there is still a lack of the operation assessment
these issues.
of the active voltage balancing circuits in the high voltage high
power converters.
In most cases, due to its reliable and straightforward struc- 2.1 The architecture of the 9.6 kV/200 A
ture, the resistor-capacitor (RC) snubber is required to bal- module
ance the voltage during the switching transitions. Consequently,
the switching loss increases. To achieve systematic optimized The equivalent circuit is demonstrated in Figure 1. In general,
performance, the RC parameter should be comprehensively the interface of the power block is the same as the conven-
selected considering the voltage balancing effect and the extra tional half-bridge power module. The adopted SiC half-bridge
switching loss. In [27], the series connection of SiC MOS- power module is BSM180D12P2E002 from Rohm Semicon-
FETs in high-speed drive is demonstrated and compared with ductor with an anti-paralleled SiC Schottky diode, which is com-
Si IGBT based solutions. A prototype of the series connec- mercially available. To form a 9.6 kV module, each switch is
tion of eight 1.7 kV SiC MOSFETs is given in [28]. The composed of eight series-connected power devices with four
current source gate driver for the series connection of SiC half-bridge power modules. G1/2 is the driving signal of the
MOSFETs is reported in [29]. The series connection of the upper/lower leg. There exists a central controller to distribute
SiC MOSFETs with capacitor snubber under soft-switching the single input driving signal to the eight devices. For each
conditions has been reported in [30, 31], where the device power module, an independent gate driver is employed. To sat-
turns off at a relatively low current at 5 kV/400 V DC LLC isfy the isolation requirements, the gate driver and the central
LI ET AL. 607

waveform of the MOS1 and MOS2 is viewed as a result of the

small disturbance among the ideal balanced conditions.
Assume the voltage rising time when the device is turned off
is trv and the total bus voltage is assumed to be Vdc . The drain
voltage among the device can be linearly approximated by [32]:

Vdc
Vds = t (1)
2trv

where t represents the time since the voltage rising moment. It

should be pointed out that the analysis here is hold for the case
with two devices in series. Therefore, the drain-source voltage
FIGURE 1 Circuit diagram of 9.6 kV/200A power module. Only two of the two devices Vds1 (t), Vds2 (t) can be represented by:
pairs of external driving signals through fibre optics are required. GD: gate ( )
driver Vdc Δt
Vds1 (t ) = t+
2trv 2
( )
V Δt
Vds2 (t ) = dc t − (2)
2trv 2

where Δt is the time deviation among the devices. Thus, the

voltage deviation ΔV among the devices is:

Vdc
ΔV = Δt (3)
2trv

To investigate the time delay on the voltage imbalance, the

voltage imbalance sensitivity VIS is defined as:

ΔV V
VIS = = dc (4)
Δt 2trv
FIGURE 2 Linearized turn-off voltage rising time. If there is Δt delay in
The parameter VIS has a clear physical meaning that for a
the PWM signal, after trv , the voltage deviation is ΔV
unit time delay of the turn-off signal, the induced voltage imbal-
ance is VIS. Thus, VIS can be adopted to evaluate the voltage
controller are isolated by fiber optics. DC+, AC and DC- are imbalance in the series connection of the power devices. VIS
power terminals of the power block. The RC snubber is used for should be as small as possible to increase the disturbance immu-
transient voltage balancing. Besides, a parallel resistor is adopted nity resulting in voltage imbalance in the series connection. To
for static voltage balancing. decrease VIS, the voltage rising time should be increased. How-
ever, when the voltage rising time is increased, the switching
loss increases as a result. There exists a tradeoff in designing the
2.2 Snubber capacitor design voltage imbalance and the gate driver.
Generally, it is complex to get the analytical model of the volt-
RC snubber has been widely used in the series connection of age rising time of the SiC MOSFETs. In review of the turn-
power devices due to its simplicity and robustness. But extra off process of the SiC MOSFETs, the external drain current ids
switching loss is caused by the RC snubber. Therefore, the equals the channel current ich1/2 and the charging current ioss1/2
proper parameter selection of the snubber is of vital importance of the parallel capacitance of the devices [25, 33], as demon-
to achieve a tradeoff between switching loss reduction and volt- strated in Figure 3.
age imbalance limitation. However, it is challenging to find the If the devices are turned off fast enough, which is due to the
mathematical boundary of the snubber capacitor to meet the fast-switching speed of the SiC MOSFETs, it can be assumed
voltage balancing issues. that all the load current flows to the parallel capacitance dur-
If the turn-off voltages are ideally balanced, the behaviour of ing this process. Therefore, the smallest turn off voltage rising
the series-connected devices is the same as the single device. time can be acquired at the assumption that all the load current
If there is a turn-off deviation Δt between two devices, owing charges and discharges the parallel capacitor, which indicates:
to the asymmetrical designs of the circuit parameters, typically
Δt is far less than the voltage rising time. The turn-off voltage Vdc (Coss + Cs )
trv ≥ (5)
rising waveform is demonstrated in Figure 2. The voltage rising IL
608 LI ET AL.

FIGURE 3 Equivalent circuit during the voltage fast-rising stage. Coss1/2 FIGURE 4 Parameter selection of the snubber capacitor under different
is the equivalent parallel capacitance load currents. Coss = 1.7 nF is selected at 650 V DC bus voltage

where Coss is the output capacitance of the devices; Cs is the

snubber capacitance; IL is the load current. As a result, VIS sat-
isfies:

IL
VIS ≤ (6)
2 (Coss + Cs )

Although it is difficult to get the exact number of the volt-

age rising time due to the nonlinear parameters and various par-
asitic parameters, the maximum VIS can be easily calculated.
From the application point of view, it is sufficient to ensure
the design to be lower than the maximum value. Thus, here,
we use (6) to evaluate the performance of the voltage balanc-
ing effect. The method is a relatively conservative parameter
selection strategy. In the proposed design, since the current is
FIGURE 5 Experimentally measured VIS from two devices in series at
assumed to flow through the parallel capacitors, the gate chan- 1300 V/200 A. The data is achieved by adjusting the gate driver delay time
nel current has little influence on the voltage of the devices manually
[33], which means the influence of the device parameter varia-
tion is less of a concern here. Nevertheless, accurately modelling
the influence of the parameters is still meaningful to achieve
the exact mathematical boundary of the design to reduce the
snubber capacitor, which is not discussed in the scope of the
paper.
Figure 4 demonstrates a series of curves on the influence
of the snubber capacitance on the VIS under different current
conditions. When the current increases and the snubber capac-
itor decreases, the VIS increases. In the practical design, it is
easy to choose the desired value of the snubber capacitor. For FIGURE 6 Equivalent circuit for the current commutation loop resonant
example, in a series of series-connected devices, the measured circuit. LESL is the equivalent series inductor of DC bus capacitor. N is the
number of series-connected devices
maximum gate driver time delay is 15 ns [30]. And the desired
largest unbalanced voltage at a 15 ns time delay is 250 V at 200
A, which means VIS should be less than 16.7 V/ns. From the 14.3 V/ns. The calculated VIS at 10 nF is 8.5 V/ns. The mea-
curve, 4.7 nF snubber capacitor is selected. sured VIS is 7.2 V/ns. The calculated VIS defines the upper
To verify the validity of the analysis, experimental verifica- limit in the selection of the snubber capacitor.
tion is performed in a two device in series setup. During the Another important consideration is the selection of the snub-
experiment, the gate driving time delay is actively adjusted to ber resistor. The ultimate motivation in the selection of snubber
measure the influence of time delay on the unbalanced voltage. resistor is to offer enough damping for the current communica-
The results is shown in Figure 5. In the experiment, two snub- tion loop, especially for the series connection configuration with
ber capacitors, namely 4.7 and 10 nF, are installed and measured. relatively large stray inductance. The total equivalent circuit for
The calculated VIS at 4.7 nF is 15.6 V/ns. The measured VIS is the current commutation loop is demonstrated in Figure 6.
LI ET AL. 609

The equivalent circuit is a third-order circuit. Except for the

snubber resistor, all other parameters can be extracted from the
device datasheet or through the FEM simulation. It has been
investigated that the above circuit has the optimized damping
ratio at a certain snubber resistance, which is [36]:
√
1 Coss + Cs
Rs = (7)
𝜔0Cs Cs

where

1
𝜔0 = √ (8)
Coss
(LESL + Ld )
N

where N is the number of devices; LESL is the ESL of the capac-

FIGURE 7 Demonstration of a typical package of SiC power module.
itor bank. In the proposed design, LESL = 90 nH, Ld = 219 The insulation voltage between the terminal and the heatsink is designed based
nH, Coss = 1.7 nF, N = 8, Cs = 4.7 nF. Therefore, the calcu- on the voltage class of the power device
lated Rs = 3.4 Ω. In the real design, Rs = 5 Ω is selected in the
end.
Apart from the snubbers, the static voltage balancing resistor
should be considered as well. The design of the parallel resistor
is related to the maximum leakage current of the power devices.
From [35], a simple equation is adopted to calculate the parallel
resistor, as:

(1 − a ) Vds − (1 + a ) (1 + b ) Vdc
Rstatic ≤ (9)
(n − 1 ) (1 − a2 ) IDSS

where a is the tolerance of the voltage balancing resistor; b is

the tolerance of dc-link voltage; Vds is the rated drain-source
resistance; Vdc is the dc bus voltage; n is the number of series-
connected devices; IDSS is the maximum cutoff current, which
can be found in the datasheet. The Rstatic could be even increased
since SiC MOSFETs of some suppliers have high avalanche FIGURE 8 Layout of the 9.6 kV/200 A module. The middle point of the
stability. In the designed case, a = 0.1, b = 0.0, Vds = 9.6 kV, two series-connected power modules is connected to the heatsink
Vdc = 5 kV, IDSS = 3.2 mA, n = 8 are adopted, the calculated
results is:
of the top-most device in the series-connected leg may exceed
Rstatic ≤ 141 kΩ (10) this voltage level if the heatsink is connected to the ground.
Therefore, in the proposed scheme, the floating heatsink must
In the design, Rstatic = 110 kΩ is adopted considering the be adopted. Two power modules or four devices are placed
availability of the resistors. on one heatsink, as demonstrated in Figure 8. To reduce the
insulation voltage stress among the bond wire and the copper
baseplate, the middle point of the four devices is connected to
the heatsink. Thus, the higher devices to the heatsink are lower
2.3 Insulation coordination design than 2.4 kV, owing to the two devices in the power module
being series-connected. Besides, the insulation coordination of
In the proposed high-power module, the commonly available the other zones is designed to comply with the medium voltage
Econo-Dual type package is adopted. In each module, there is standard IEC 61800-5-1.
a half-bridge circuit inside. Since the power module is designed
for 1.2 kV applications, proper insulation considerations should
be accounted for to be able to operate in much higher volt- 2.4 Auxiliary power supply design
age. The package inside the power module is demonstrated in
Figure 7. From the datasheet, the insulation voltage between The auxiliary power supply is of vital importance to ensure the
the chip and the copper base plate (usually mounted on the safe operation of the power block. Since there are 16 power
heatsink) is 2.5 kV. Due to the cascading, the operating voltage devices in the circuit, 16 independent power supplies should
610 LI ET AL.

is the precision LCR meter LCR-6300 from GW Instek. The

capacitance is measured at 100 kHz when the primary and sec-
ondary side of the transformer is short-circuited. The measured
parasitic capacitance of CT is 3.2 pF and the gate driver iso-
lated transformer is 0.5 pF. The total parasitic capacitance is
0.4 pF.

2.5 Gate driver design

In general, the gate driver of the series-connected device is dif-

FIGURE 9 Architecture of the auxiliary power supply for driver board.
Two stage isolation is adopted to achieve high insulation voltage and low
ferent from the single device. To achieve the successful series
parasitic coupling capacitance connection, a specially designed gate driver is developed. The
normal gating driving of the devices is similar to the single
high voltage devices. The overvoltage, overcurrent and over-
temperature protection are all integrated in the gate driver [30].
However, the main difference lies in the protection. When one
of the devices detects the fault condition, the device cannot
be turn-off locally as the single high voltage device does. Here,
the fault information is sent to a central controller and then all
the devices are turned off at the same time. Thus, a fast cen-
tral controller, normally FPGA, is necessary to hand the fault
information to ensure fast responding time. The gate driver uses
fibre optics to receive the PWM signal and feedback fault signal.
FIGURE 10 The parasitic capacitance of the (a) CT and (b) PCB
Besides, a digital controller is adopted to communicate with the
mounted transformer central controller. Moreover, the authors use the active Miller
clamping method proposed in [38] to prevent the potential false
switching of the device, which is a typical solution for driving
be supplied. The desired auxiliary should satisfy two condi- SiC MOSFETs.
tions: Firstly, enough insulation voltage must be guaranteed.
Secondly, the coupling capacitance between the input supply
and the gate driver board should be as small as possible, espe- 2.6 Prototyping of 9.6 kV/200 A power
cially for the high side SiC MOSFETs in the string of devices. block
Due to the cascading, the high side SiC MOSFETs may have
a dv/dt (to the ground) larger than 100 V/ns, which implies Finally, based on the previous design, the final power block is
a high requirement on the coupling capacitance across the implemented. The continuous on-state current is 204 A, which
transformers. is the same as the single device. The on-state resistance when
Considering these facts, based on the previous architectures the gate driving voltage keeps at 18 V is 97.7 mΩ. The driving
in [34, 37], an auxiliary power scheme is proposed in this paper, voltage is +18 V/−2 V, which is suggested by the datasheet.
as demonstrated in Figure 9. Normally, one single magnetic core The turn-on and turn-off resistor is 2.25 Ω.
is adopted in the gate driver power supply. However, to satisfy The stray inductance of the power block is the result of the
the insulation voltage in MV range, a large core size is required stray inductance of the laminated busbar and the device’s inter-
to ensure insulation distance. In the paper, the current source nal stray inductance. The laminated bus bar design has been dis-
power scheme is adopted. A high-frequency AC current link is cussed in [31] and the total inductance is 115 nH. The internal
generated by a DC/AC inverter, then the power for the gate inductance of the power module is 13 nH, which is obtained
driver board is obtained through a current transformer (CT). In from the datasheet. Since there are eight power modules in the
the gate driver board, to further reduce the parasitic capacitance, loop, the total inductance is 115 nH + 13 × 8 nH = 219 nH.
a N1 (input winding) :1:N2 (output winding) transformer based Figure 11 demonstrates the picture of the proposed 9.6 kV/200
on two separate cores along the PCB is adopted, as demon- A module. The total size of the power block (including control
strated in Figure 9. Since the input winding and output wind- boards and auxiliary power supply) is 30 cm × 30 cm × 15 cm.
ing is connected by only one turn in the middle, the coupling The designed converter achieves an overall power density of
capacitance is greatly reduced. 25 kW/L, with forced air cooling.
The current transformer or the PCB transformer has one- Above all, with the proposed design, the series-connected SiC
turn in the primary or secondary side, which greatly reduces the MOSFETs can be viewed as a single high voltage device. The
overlap area between the two sides and consequently, the par- device specifications are given in Table 1. It should be pointed
asitic capacitor is reduced. The experimentally measured cou- out that the solution in the section can also be adapted to other
pling capacitance is demonstrated in Figure 10. The instrument kinds of power blocks with SiC MOSFETs connected in series.
LI ET AL. 611

FIGURE 11 Picture of the proposed module FIGURE 12 Double pulse test waveform at 5 kV/200 A

TABLE 1 Parameters of the designed module

Parameters Symbol Test condition Value

Drain voltage Vds gate-source shorted circuit 9.6 kV

Drain current Ids Continues DC current 204 A
On state resistance Rds,on 25°C 97.7 mΩ
Gate driving voltage Vg_on /off – 18 V/−2 V
Gate resistor Rg – 3.75 Ω
Leakage inductance Ld – 219 nH
Snubber circuit Rs /Cs – 5 Ω/4.7 nF

3 DYNAMIC PERFORMANCE
ASSESSMENT OF 9.6 KV/200 A SIC POWER FIGURE 13 Zoomed turn off waveform at 5 kV/200 A
BLOCK

The switching performance is one of the most important per-

formances of the power devices. The dynamic performances of
the 9.6 kV/200 A module, including the medium voltage switch-
ing speed, switching loss, temperature variations, and the voltage
balancing evaluation are characterized in this section. Consider-
ing the general application scenario, the measurement is con-
ducted with inductive load under hard switching.
The definitions of switching time and switching loss are taken
from IEC60747-9 standard. For comparison, the results are
compared with the advanced high-power modules, including Si
devices and SiC MOSFETs. The devices for reference include
CREE 10 kV/100 A SiC module, 6.5 kV/400 A IGBT from
ABB, and 6.5 kV/250 A IGBT from Infineon [8]. In the pulse
test, the voltage probe is SI-9010A from Sapphire, with 70 Mhz
bandwidth and ±7000 V voltage range. The current is measured FIGURE 14 Zoomed turn-on waveform at 5 kV/200 A
by CWT MiniHF 3 from PEM, with 30 MHz bandwidth and
600 A peak current. the double pulse waveform at 5 kV/200 A. The reason for
choosing 5 kV DC bus voltage is considering the application
with leg output AC voltage of 3.3 kV or lower, with a rela-
3.1 Switching speed tively conservative selection of the total blocking voltage. And
Figures 13 and 14 are the zoomed waveform at switching
Taking the lower device as the switching device and the upper device turn-on and switching device turn-off. Judging from the
device as freewheel diodes for example, Figure 12 demonstrates switching waveform, the designed power block functions
612 LI ET AL.

TABLE 2 Switching speed comparison under typical conditions

Turn-on and turn-off

Devices Test point di/dt (A/ns) dv/dt (V/ns) di/dt (A/ns) dv/dt (V/ns)

Proposed 9.6 kV/200 A 5 kV/200 A 2.00 −33.3 −2.0 55.0

5 kV/100 A 2.00 −50.0 −0.67 38.0
CREE 10 kV/100 A 5 kV/87 A 0.99 −25.8 −0.56 43.4
Si IGBT 3.5 kV/60 A 0.48 −6.11 −0.34 1.2

appropriately and acts as a single high voltage device. The

demonstrated gate driving voltage is the gate voltage of one of
the eight devices.
Due to the parasitic parameters in the circuits, there exist
significant oscillations in the current and voltage waveform,
which are commonly found in the power electronics circuits.
It is essential to check the overshoot is within the safe opera-
tion area of the devices. The overshoot voltage at turn-off of
the switching device is 6.5 kV. And the overshoot current at
the turn-on of the switching device is 260 A. Typically, there FIGURE 15 Illustration of the current path during the switching of the
devices: (a) Switching device turn-on; (b)switching device turn-off; (c)
exist parallel SiC Schottky diodes in the power module. Ideally, Freewheel diode turn on; (d) freewheel diode turn-off
there is no overshoot current at turn-on. In reality, due to the
existence of the parallel capacitor, there is a charging current of
the parallel capacitor of the upper device. Therefore, there is an TABLE 3 Contents of the power losses
inrush current at turn-on of the lower device. The test results Power losses Symbol Stage
demonstrate that all the devices operate under the voltage safe
Turn-on loss of switching device Eon_switch (a)
operation area.
Turn-off loss of switching device Eoff_switch (b)
Further, the switching speed of the devices is measured and
compared with the state-of-the-art power devices, as demon- Snubber loss when devices are turned on Eon_switch_snubber (a)
strated in Table 2. The data for comparison is from [8]. At Snubber loss when devices are turned off Eoff_switch_snubber (b)
5 kV/200 A condition, the turnon di/dt is 2.0 A/ns and the Freewheel diode snubber loss when device is turned off Eon_diode_snubber (c)
turnoff di/dt is −2.0 A/ns. The di/dt of the series-connected Freewheel diode snubber loss when device is turned on Eoff_diode_snubber (d)
device is comparable to the single device and far larger than Si
IGBT devices. Besides, the turn-on dv/dt is −33.3 V/ns and the
turn-off dv/dt is 55 V/ns. The dv/dt during switching is similar
to the single high voltage device and is far larger than Si IGBT. loss. However, due to the extra RC snubber, the switching loss
Due to the existence of the snubber capacitor, there is a con- of the series-connected devices should also include the power
cern that the switching speed of the SiC MOSFETs may be loss on the snubbers. These losses are included in the switching
reduced. Generally, the test results demonstrate that the switch- losses in the following section accordingly.
ing speed of the series-connected devices is at the same level When the snubber circuit is in parallel with the series-
with one single high voltage device and much faster than Si connected devices, the power loss contains more elements.
IGBTs. Figure 15 demonstrates the power loss on different parts of
In conclusion, the proposed power block has extremely fast a single switching event. During switching, different kinds of
switching speed, which is the foundation of the low loss switch- power loss are generated and can be measured from the voltage
ing. It should be noticed that the test condition, such as the gate and current waveform. And Table 3 gives the description of the
driving resistor, or the stray inductance is not the same for dif- power loss in total.
ferent power devices. Yet, the measured data still verifies that The power losses are all calculated from the measured wave-
the proposed power block has an extremely high-speed switch- form based on IEC60747-9 standard. For the sake of brevity,
ing capability. the power loss related to the turn-on/turn-off event and the
power loss on the freewheel diodes are added together in the
following analysis, namely:
3.2 Switching losses
Eon = Eon_switch + Eon_switch_snubber
Based on the measured waveform, the switching losses can be
Eo f f = Eo f f _switch + Eo f f _switch_snubber
calculated. In general, the switching loss of the power devices
includes the turn-on loss, turn-off loss, and reverse recovery Ediode = Err_diode + Eon_diode_snubber + Eo f f _diode_snubber (11)
LI ET AL. 613

TABLE 4 Switching loss comparison under typical conditions. (Note: Ediode refers to reverse recovery loss or snubber loss;‘-’ means data unavailable.)

Devices Test conditions Eon (mJ) Eoff (mJ) Ediode (mJ) Etot (mJ)

Proposed 9.6 kV/200 A 5 kV/200 A 31 56 13 100

5 kV/121 A 18 35 19 72
3 kV/53 A 4 9 10 23
CREE 10 kV/100 A 5 kV/200 A 161 50 0 210
3 kV/53A 13 8 – 21
Si IGBT, ABB 6.5 kV/200 A 5 kV/200 A 1328 1595 – 2923
Si IGBT, Infinenon, 6.5 kV/250 A 5 kV/200 A 1556 1333 522 3411

Compared with the switching loss, the balancing resistor

power loss is relatively small. In the proposed design, at any
time, there are eight series-connected balancing resistors to
withstand the DC bus voltage. The total power loss is 28
W, which means for each resistor, the average power is only
1.7 W.
Table 4 demonstrates the switching loss at different volt-
age and current points. At 5 kV/200 A condition, the turn-
on switching energy dissipation is 30.96 mJ, turn-off switching
energy dissipation is 56.09 mJ and freewheel diode switching
energy dissipation is 13.37 mJ. The total switching energy dissi-
pation is only 100.42 mJ.
In comparison among the high voltage devices, since the data
are from datasheets and literature, the operating point is not
the same. The data of IGBT is from the linear fitting curve
assumption of the datasheet. It should be pointed out that in
reality, it is challenging for 6.5 kV IGBT to operate at 5 kV.
Thus the data here is for reference only. In general, the switch- FIGURE 16 Current dependence of switching loss at 5 kV DC bus
ing loss of the series-connected devices is at the same level as voltage
the single high voltage SiC device. Compared with Si IGBT,
the total switching loss is lower than 10% of the Si devices
at the same voltage and current condition if linear interpo- 3.3 Temperature dependence
lation approximation is adopted. Series connected SiC MOS-
FETs demonstrate a huge improvement over high voltage Si Since the single-device parameters vary with the junction tem-
devices. perature, it is meaningful to investigate the temperature depen-
Figure 16 demonstrates the load current and bus voltage dence of the performance of the series-connected devices. In
dependence of the switching loss. When the bus voltage stays at this section, at 5 kV/200 A, the turn-on and turn-off waveforms
5 kV, the switching loss increases with the load current. Under at different junction temperatures are further investigated.
lower currents, turn-on loss is higher than turn-off loss. When Figure 17a demonstrates the turn-on waveform from 25 to
the load current is in the higher range, the turn-on loss is lower 75 ◦ C. As the junction temperature increases, the turn-on delay
than the turn-off loss. It is the result of the relatively large leak- time decreases. It is the result of the negative dependence of the
age inductance in the power loop due to the series connec- threshold voltage of the SiC MOSFETs. Generally, the differ-
tion. The higher stray inductance increases the turn-off loss and ence among different junction temperatures is relatively small.
reduces the turn-on loss [39]. The current overshoot keeps nearly constant when the junc-
The freewheel diode loss keeps almost the same under differ- tion temperature rises, owing to the charging current of the
ent load currents, which is different from the conventional P-i- parallel capacitor of the upper device being independent of the
N diode. The reason is that there is no reverse recovery current temperature.
caused by the extra carriers for the Schottky diode. The free- Figure 17b demonstrates the turn-off waveform of the power
wheel diode loss is only related to the power loss dissipated on block under test under different temperatures. When the junc-
the snubber resistor, which is mainly determined by the blocking tion temperature increases, the turn-off time increases, which
voltage of the device. In general, the switching loss tendency of is the result of the decreased threshold voltage. In general,
the series-connected device is the same as the single high voltage when the junction temperature rises, the spikes of the electrical
device. parameters during switching keep nearly the same, whereas the
614 LI ET AL.

FIGURE 18 Switching loss at different junction temperatures at

5 kV/200 A

general, the series-connected device has relatively stable switch-

ing loss along with the temperature variation.

3.4 Voltage balancing effect

Another concern is the voltage sharing among the eight devices

when the device is turned off, which is highly important to
the safe operation of the devices. Figure 19a demonstrates the
FIGURE 17 Measured drain voltage and drain current waveform at voltage sharing when the device is turned off and turned on.
different junction temperatures: (a) Turn-on transient of the active device (left)
and freewheel diode (right); (b) turn-off transient of the active device (left) and
Besides, Figure 19b demonstrates the unbalanced voltage when
freewheel diode (right) the freewheel diode is turned off and turned on. The wave-
forms are measured at 100 ◦ C. The maximum unbalanced volt-
age among the eight devices is less than 100 V. The highest peak
voltage is less than 800 V. In conclusion, the voltage stress in the
switching delay time obviously changes. Compared with the series-connected devices is well below the safe operation margin
turn-on waveform, the turn-off waveform is more sensitive to of the 1200 V device.
the junction temperature. When the junction temperature increases, the threshold
Figure 18 demonstrates the switching loss at 5 kV/200 A voltage decreases and consequently, the voltage rising time
conditions at different temperatures. The switching loss is calcu- decreases. As shown in (4), the voltage imbalance sensitivity
lated under different junction temperature conditions from 25 increases, which leads to an increased unbalanced voltage. To
to 100 ◦ C. Experimental data suggests that the freewheel diode investigate the voltage sharing under different junction temper-
losses are temperature independent, which is due to the stable atures, Table 5 demonstrates the measured unbalanced voltage
parameters of the snubber capacitor and the resistor within rea- from 25 to 100 ◦ C. The experimental results indicate that the
sonable temperature range. Whereas the turn-on and turn-off maximum unbalanced voltage is under 100 V in all the cases,
loss decrease slightly with the temperature rising. The sensitiv- which can ensure the thermally stable operation. The unbal-
ity of the switching loss on temperature dependence relies on anced peak voltage increased from 60 to 94 V, which verifies
a series of influential factors. The threshold voltage is one of the analysis of the influence of the temperature.
them. During the turn-off, the device current flows through Above all, the proposed 9.6 kV/200 A device has excellent
the MOS channel and the parallel capacitors. If extra snubber switching performance compared with the existing high-power
is added, the influence of the threshold on the switching loss is devices. Although the RC snubbers are added to balance the
reduced due to the turn-off current will partially flow through dynamic voltage, the low loss switching can still be ensured
the snubber capacitor, which is not influenced by the junction under the high-speed switching. The general tendency of the
temperature of the device. As a result, the influence of junction switching loss of the series-connected device is similar to the
temperature on switching loss exists but is not significant. In single high voltage device.
LI ET AL. 615

FIGURE 20 Structure of medium voltage test platform

TABLE 6 Maximum parameters of the Pumpback test platform

Parameters Value

Apparent power Sb 3 MVA

DC bus voltage Vdc 10 kV
AC voltage Vac 6.3 kV
Load inductor L 3 mH

Besides, the EMI noises increase due to the continuous switch-

ing. A robust design should ensure the safe and highly effi-
cient functionality of the power block. Nowadays, the series-
connected technique is seldom reported in continuous opera-
tion conditions due to the challenges in handling the medium
voltage fast switching speed.
To verify the designed module’s thermal and electrical per-
formance under continuous running in the field application, the
pumpback test is the commonly adopted method. The scheme
FIGURE 19 Drain voltage waveform of the eight devices: (a) Turn-off of the pumpback system is demonstrated in Figure 20 and the
transient of the active device (left) and freewheel diode (right); (b) turn-on parameters of the system are demonstrated in Table 6. The
transient of the active device (left) and freewheel diode (right) grid voltage is firstly passed through a voltage regulator and
then rectified by a multi-phase diode rectifier and generates
TABLE 5 Measured unbalanced voltage at different junction temperatures an adjustable DC link, which can be as high as 10 kV. The
maximum current can be 0.5kA. With this configuration, the
MOSFET number 25 ◦ C (V) 50 ◦ C (V) 75 ◦ C (V) 100 ◦ C (V) active input power is only the power for the losses in the sys-
1 655 660 679 654 tem. Such a test simulates the operation condition of the power
2 625 628 640 653 block in the real application, which is the critical test in the
3 608 597 598 602
early-stage design of the high-power converter systems. Typi-
cally, two power blocks are required to test the devices under
4 605 606 620 598
different power factors. However, in this paper, for simplicity,
5 610 598 600 582 the output of the half-bridge module is connected back to the
6 620 612 607 573 middle point of the DC-link through the load inductor. Within
7 596 599 613 607 this configuration, the experiments under different power fac-
8 646 660 677 676 tors cannot be verified. However, it is enough to investigate the
ΔVmax 60 63 81 94
switching performance of the power block under different load
currents.

4 VERIFICATION IN CONTINUES 4.1 Continuous running results

RUNNING
When the power block is installed into the enclosed cabinet,
The continuous running capability is the critical index that veri- the SPWM signal is sent to the power block to generate a sinu-
fies the application of the 9.6 K/200 A power block. Under con- soidal fundamental voltage waveform at the AC terminal. The
tinuous running, the load current varies within the fundamen- switching frequency is selected to be 5 kHz and a piece of 4 µs
tal period, which may affect the voltage sharing of the devices. turn-on delay, referred to as the deadtime, is added to avoid
616 LI ET AL.

FIGURE 21 Measured waveform at thermal steady state at 5 kV/100 A

RMS /5 kHz

FIGURE 22 Measured heatsink temperature at thermal steady state at

5 kV/100 A/5 kHz RMS

FIGURE 23 Measured drain voltage waveform at different load current

shoot-through of the DC link. Therefore, there will be a sinu-
conditions during continues switching: (a) Switching current = 150 A; (b)
soidal current flowing through the inductor. Besides, in the test, switching current = 0 A;
forced air cooling is adopted. The airflow at the input of the
heatsink is 6 m/s.
Figure 21 is the total drain-source voltage and inductor cur- 4.2 Voltage balancing under continuous
rent at 5 kV/5 kHz/100 A RMS condition. The experimen- running
tal results demonstrate that the designed module can oper-
ate at 5 kV/100ARMS conditions. Considering the current Further, the above measurement only considers the total volt-
ripple of the inductor, the peak current reaches 170 A and age. It is critical to measure the voltage unbalance for different
varies from zero to the peak range in a fundamental period. In devices during continuous operation.
the whole switching cycle, the peak voltage is less than 7 kV The voltage balancing effect is demonstrated in Figure 23. In
and satisfies the safe operating condition at any switching cur- the figure, due to the power module being mounted into the
rents. There is current distortion at the zero-cross point of the medium-voltage cabinet, the drain voltage of the four devices in
inductor current, which is due to the influence of the dead one leg and the total leg are given to simplify the measurement
time. setup. The current waveform is measured at 0 and 150 A con-
Figure 22 is the measured heatsink temperature at the thermal ditions separately. The experimental results demonstrate that,
steady state in an enclosure cabinet. The environmental temper- under all the cases, the voltage is properly balanced. It should
ature is 20 ◦ C. Wherein, the first heatsink and second heatsink, be noticed that under 0 A, the drain-source voltage rising speed
from left to right, are in the input side of the cooling air, which is lower than high current conditions, which is due to the rela-
is the eight devices in the upper leg. And the third heatsink and tively slow charging rate of the parallel capacitor. The voltage is
fourth heatsink are at the output of the cooling air, which is the still properly balanced under low current conditions.
eight devices in the lower leg. The experimental results demon- The experiments verify that the series connection technique
strate that the case temperature rising of the eight devices is can be adopted in the continuous running condition. The
under 16 ◦ C. And for the eight devices in series, the tempera- 9.6 kV/200 A device can run at 5 kV/100 A RMS conditions.
ture deviation is below 3 ◦ C. The measured temperature verifies The test also demonstrates the high switching frequency of the
the effectiveness of the thermal design. proposed power block. As a comparison, for high voltage Si
LI ET AL. 617

FIGURE 24 Circuit diagram of a grid-connected wind converter

TABLE 7 Parameters of investigated system

DC bus voltage 5 kV

Grid voltage 3.3 kV

FIGURE 25 Efficiency versus output load at different switching
Apparent power 1 MVA frequencies. The results of SiC MOSFETs and Si IGBTs based solution are
Load inductor 3 mH covered

5.2 Power loss calculation results

IGBT (higher than 1.7 kV) based solutions, the switching fre- Figure 25 demonstrates the load power dependence of the con-
quency of the power device is typically less than 1 kHz. verter at the unit power factor. In the calculation, the output
power points at 25%, 50%,75% and 100% are selected. And
the switching frequency varies from 1 to 17 kHz. The calcu-
5 PERFORMANCE ANALYSIS IN lation results demonstrate that at 5 kHz, the overall efficiency
MEDIUM VOLTAGE CONVERTERS is higher than 99.1%. At the low-frequency conditions, the
efficiency is increased at the light load. However, at relatively
It has been demonstrated that the series connection of SiC high switching frequencies, the overall efficiency is decreased
MOSFETs can achieve impressive dynamic performance with and at light load conditions, the efficiency increases first and
a simple RC snubber for voltage balancing. Going one step fur- decreases in the light load. The tendency is generally related to
ther, it is of interest to investigate the performance achieved of the loss distribution of the power devices. Moreover, a com-
the proposed power block in the medium voltage converter. In parison of the Si IGBT-based solution is also demonstrated in
this section, a typical application is selected to discuss power loss Figure 25. The 1.2 kV/200 A Si IGBTs connected in series
under different conditions. Taking the direct driving medium are adopted in the calculation. The 1.2 kV Si IGBT is from
voltage wind converter for example, based on the proposed Infineon FF200R12KS4. Compared with the series connection
10 kV/200 A module, the power loss under various conditions of SiC MOSFETs, it displays a significantly lower conversion
can be calculated. In the analysis, the energy conversion effi- efficiency at the same switching frequency condition. In con-
ciency is especially stressed. clusion, the proposed power block has relatively stable energy
conversion efficiency and is less influenced by switching
frequency.
5.1 System configuration and general At the 1MW output power, modulation index is 0.8 and unit
considerations power factor condition, the variation of the power loss with
the switching frequency is demonstrated in Figure 26. At each
The circuit scheme for efficiency analysis is demonstrated in switching frequency, the power loss includes the reverse con-
Figure 24, the converter is made of a three-phase back-to-back duction loss, forward conduction loss, snubber loss and the
converter. The dc bus voltage is 5 kV, the grid connect voltage switching loss. It clearly demonstrates that with the increase of
is 3.3 kV. The apparent power of the converter is 1 MVA. The the switching frequency, the conduction loss stays the same.
parameter of the grid-connected converter is demonstrated in However, the switching loss keeps increasing. At the given
Table 7. Firstly, the typical process to evaluate the power loss frequency, the dominant power loss is the conduction loss,
of the high-power converters is adopted [40]. The calculation especially under the low switching frequency conditions. With
is based on the conduction loss from the device datasheet at a respect that the selected power module being based on the first
given temperature and the switching loss from the double pulse generation of SiC devices, the potential low on-state loss hasn’t
test. In the calculation, the third-order harmonic injection is been fully explored. There is still a huge improvement for reduc-
adopted to increase the DC bus voltage utilization ratio. In the ing the conduction loss of the power module in the future if the
calculation, the junction temperature at 125 ◦ C is adopted. next-generation SiC chip is adopted.
618 LI ET AL.

FIGURE 26 Semiconductor loss versus the switching frequency for

series connected SiC MOSFETs FIGURE 28 Semiconductor loss at different modulation indexes

In this section, the power loss under different frequencies

and modulation indexes are given. The 9.6 kV/200 A power
block achieves a superior performance, which demonstrates the
potential of the application of the series connection technique
in medium voltage high power converters. Although the calcu-
lation is conducted in the simplest half-bridge circuit, the pro-
posed method can be applicable to any other kinds of topologies
and applications under hard switching conditions.

6 CONCLUSION
Here, the design, characterization and assessment in MV con-
verters of a 10 kV/200 A power block based on series connec-
tion are demonstrated. The snubber selection, insulation coor-
dination, and auxiliary power supply design are presented. The
FIGURE 27 Semiconductor loss versus the switching frequency for Si proposed power block adopts the simple RC snubbers and with
IGBTs based solutions the optimized design, fast switching can still be ensured. The
maximum dv/dt is as high as 55 V/ns, and di/dt is 2.0 A/ns,
which are both higher than state-of-the-art high voltage high
For comparison, the loss breakdown of Si IGBT based results power devices. The voltage imbalance at 5 kV/200 A/100 ◦ C
is demonstrated in Figure 27. In the calculation, the snubber among the eight devices is below 100 V, which ensures the safe
loss of Si IGBT is assumed to the same as SiC MOSFETs here. operation of the series connection. The total switching loss at
In reality, the actual power loss will be more significant since a 5 kV/200 A is only 100.42 mJ, which is smaller than the state-of-
larger snubber is required for voltage balancing of the Si IGBT. the-art power devices. Moreover, the proposed module demon-
It can be found that the proposed module demonstrates far less strates stable junction temperature dependence. The total loss
switching loss compared with Si IGBT based solutions. is nearly constant with the junction temperature rising. The pro-
The power loss distribution with the modulation index is posed power block functions as a half-bridge module and can
demonstrated in Figure 28. The figure is calculated at 5 kHz be adopted in medium voltage converters directly as the fun-
and unit PF condition. When the modulation index increases, damental power electronics building block. In conclusion, the
the power loss increases as well. The main difference occurs at series-connection of SiC MOSFETs is an attractive approach to
the conduction loss. Under light modulation index conditions, acquiring high voltage, highly efficient power devices. In the fol-
the devices at the same leg conduct with nearly 50% duty cycle. lowing work, insulation capability of the single module could be
Thus, there exists a large portion of time for the reverse conduc- improved by the proper package design to achieve the simpli-
tions, leading to reduced conduction loss compared with high fied design and the reliable operation for much higher operating
modulation index conditions. voltages.
LI ET AL. 619

ACKNOWLEDGEMENTS Annual IEEE Conference on Applied Power Electronics Conference and

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