Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 141 views

    DLD Lab 9

    Uploaded by

    Muhammad Rehan
    This document describes Lab 09 for the course EE221: Digital Logic Design. The lab has two parts: 1. Design and implement an excess-3 to Gray code converter using NAND gates on a hardware platform. Students are required to show the hardware results for input decimals 5 and 8 (for even group numbers) and 4 and 9 (for odd group numbers). 2. Design and simulate the excess-3 to Gray code converter circuit in Verilog dataflow modeling. Students must provide the code, testbench, and waveform. The pre-lab tasks involve making truth tables for the excess-3 and Gray codes, deriving the output equations from K-maps, and drawing logic diagrams using

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    DLD Lab 9

    Uploaded by

    Muhammad Rehan
    141 views6 pages
    This document describes Lab 09 for the course EE221: Digital Logic Design. The lab has two parts: 1. Design and implement an excess-3 to Gray code converter using NAND gates on a hardware platform. Students are required to show the hardware results for input decimals 5 and 8 (for even group numbers) and 4 and 9 (for odd group numbers). 2. Design and simulate the excess-3 to Gray code converter circuit in Verilog dataflow modeling. Students must provide the code, testbench, and waveform. The pre-lab tasks involve making truth tables for the excess-3 and Gray codes, deriving the output equations from K-maps, and drawing logic diagrams using

    Original Description:

    Dld Lab for instruction

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes Lab 09 for the course EE221: Digital Logic Design. The lab has two parts: 1. Design and implement an excess-3 to Gray code converter using NAND gates on a hardware platform. Students are required to show the hardware results for input decimals 5 and 8 (for even group numbers) and 4 and 9 (for odd group numbers). 2. Design and simulate the excess-3 to Gray code converter circuit in Verilog dataflow modeling. Students must provide the code, testbench, and waveform. The pre-lab tasks involve making truth tables for the excess-3 and Gray codes, deriving the output equations from K-maps, and drawing logic diagrams using

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    141 views6 pages

    DLD Lab 9

    Uploaded by

    Muhammad Rehan
    This document describes Lab 09 for the course EE221: Digital Logic Design. The lab has two parts: 1. Design and implement an excess-3 to Gray code converter using NAND gates on a hardware platform. Students are required to show the hardware results for input decimals 5 and 8 (for even group numbers) and 4 and 9 (for odd group numbers). 2. Design and simulate the excess-3 to Gray code converter circuit in Verilog dataflow modeling. Students must provide the code, testbench, and waveform. The pre-lab tasks involve making truth tables for the excess-3 and Gray codes, deriving the output equations from K-maps, and drawing logic diagrams using

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 6

    Department of Electrical Engineering

    Faculty Member: Dr Nasir Mahmood Dated: 4/26/2021

    Semester: 2nd Section: Bese-11A

    Group No.:01

    SE-221: Digital Logic Design

    Lab 09: Excess-3 to Gray Code Conversion using Nand Gates

    PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7


    Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
    Performanc of data in Tool Usage Safety and Team marks
    e Lab Report Work Obtained

    5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks


    Muhammad Rehan 342377

    Umair 359652

    Lab 09: Excess-3 to Gray Code Conversion using Nand Gates

    EE221: Digital Logic Design Page 1


    This Lab has been divided into two parts: Psychomotor Level P-4
    In first part you are required to design and implement a Excess-3 to gray code converter.
    The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
    lab.
    Objectives:

     Understand steps involved in design of combinational circuits


     Understand binary codes for decimals and their hardware realization
     Write code for combinational circuits using Verilog Gate Level Modeling
     Design a circuit in Verilog by calling different modules

    Lab Instructions

     This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva
    session.
     The lab report will be uploaded on LMS three days before scheduled lab date. The
    students will get hard copy of lab report, complete the Pre-lab task before coming to
    the lab and deposit it with teacher/lab engineer for necessary evaluation.
     The students will start lab task and demonstrate design steps separately for step-
    wise evaluation(course instructor/lab engineer will sign each step after ascertaining
    functional verification).
     Remember that a neat logic diagram with pins numbered coupled with nicely
    patched circuit will simplify trouble-shooting process.
     After the lab, students are expected to unwire the circuit and deposit back
    components before leaving.
     The students will complete lab task and submit complete report to Lab Engineer
    before leaving lab.
     There are related questions at the end of this activity. Give complete answers.

    Pre-Lab Tasks: (To be done before coming to the lab)

    EE221: Digital Logic Design Page 2


    1. In the lab you would be implementing a Excess-3 to gray code converter. Make a truth
    table for both the codes by filling in the following tables and Simplify the expressions for
    W,X,Y,Z in terms of A,B,C,D.( Use backside of the page if necessary). Use unused
    combinations as don’t care conditions.

    (2Marks- Individual. and Team Work)


    HINT:
    Dec Excess 3 code Gray Code
    Our inputs and outputs are of 4-bit decimal
    A B C D W X Y Z
    values. You will have to make 4 K-Maps
    0 0 0 0 x x x x (Consider W as independent function of
    0 0 0 1 x x x x input variables A,B,C,D, Make K-Map and
    simplify it). Arrive at the simplest
    0 0 1 0 x x x x
    expression for each output. Show your k-
    0 0 0 1 1 0 0 0 0 mapping and equation simplification in
    1 0 1 0 0 0 0 0 1 your lab report. Don’t copy and paste from
    2 0 1 0 1 0 0 1 1 this link, other-wise you will get zero.

    3 0 1 1 0 0 0 1 0
    4 0 1 1 1 0 1 1 0
    5 1 0 0 0 0 1 1 1 W= ACD + AB
    6 1 0 0 1 0 1 0 1 X= BCD + A
    7 1 0 1 0 0 1 0 0
    Y= BD + BC + B'C'D'
    8 1 0 1 1 1 1 0 0
    Z= 9 1 1 0 0 1 1 0 1 C'
    1 1 0 1 x x x x
    1 1 1 0 x x x x
    1 1 1 1 x x x x

    2. Draw the logic diagram for Excess-3 to gray code converter using AND, OR and NOT
    gates in the space provided below. You can use 2,3,4 input gates if required. (2 Marks-
    Modern tool usage)

    EE221: Digital Logic Design Page 3


    Logic Diagrm :

    3. Draw the logic diagram for Excess-3 to gray code converter using only NAND gates in
    the space provided below, You can use 2,3,4 input Nand gates if required (3 Marks-
    Individual. and Team Work)

    Logic diagram :

    EE221: Digital Logic Design Page 4


    Lab Tasks: (To be completed in the lab)

    Lab Task 1:

    Implement Excess-3 to gray code converter using only NAND gates on hardware (tinkerCAD).
    Paste the complete circuit diagram, depicting hardware results of

    hardware results of decimal input 5 and decimal input 8. (For even group numbers)

    hardware results of decimal input 4 and decimal input 9. (For odd group numbers)

    (5 Marks – Analysis)

    Dec Excess 3 Gray Code


    Hardware result
    A B C D W X Y Z
    0
    1
    2
    3
    4
    5
    6
    7
    8
    9

    Lab Task2:Design and simulate the circuit k-map equations you obtained in Pre-lab task 1 in
    Verilog dataflow modeling. Give the code and testbench and waveform in the space provided
    below. (3Marks – Modern tool
    usage)

    EE221: Digital Logic Design Page 5


    EE221: Digital Logic Design Page 6

    You might also like