Department of Electrical Engineering: Lab No # 2: Introduction To Verilog (CLO4, P3)

Department of Electrical Engineering
Faculty Member: Ma’am Quartulain Dated: 13-3-2021
Semester: 2nd Section: Bese-11A
Group: 1 st(Rehan+Umair)
SE-221: Digital Logic Design

Lab No # 2: Introduction to Verilog (CLO4, P3)
CLO4/PLO4 CLO4/PLO5 CLO6/PLO8 CLO7/PLO9

Name Reg. No Viva / Analysis Modern Tool Ethics and Individual
Quiz / Lab of data Usage Safety and Team
Performa in Lab Work
nce Report
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

Rehan Ramzan 342377
Umair 359625
EE-221: Digital Logic Design Page 1

Lab2: Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware
Implementation of Basic Logic Circuit
This Lab has been divided into two parts.
In first part you will be introduced to Verilog and Gate-Level Modeling.

The next part is the hardware implementation of a Boolean function given to you.
Objectives:
 Understand HDL and compare it with normal programming languages.

 Simulate Basic Gates using Verilog withModelSim
 Write stimulus using Verilog
 Derive algebraic expression for a Boolean function from the given schematics.
 Hardware Implementationof Logic Circuit
Lab Instructions
 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The students will get
hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
report on LMS for grading.
 The students failing to submit Pre-Lab will not be allowed to perform Lab work.
 The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
 The students will complete lab task and submit complete report to Lab Engineer before leaving
lab. Verilog tutorial part is non-printable and for reference only.
 There are related questions at the end of this activity. Give complete answers.

Pre-Lab Task: (To be done before coming to the lab) (2 marks)
1. Read the manual Getting Started with Verilog and answer the following questions.
a) HDL stands for
b) Two standard versions of HDL are
c) Give the different levels of abstraction in Verilog HDL
Ans(a) : HDL Stands for Hardware Description Languages.
Ans(b) : Two Standard version of HDL are:
1) VHDL
2) Verilog HDL
Ans(c) : Levels of abstraction in Verilog HDL are given below:
1) Gate Level Modeling {using the basic gates and, or, Not, etc }
2) Dataflow Modeling {defining the flow of data among different components}
3) Behavioral Modeling {defining the overall behavior of system}
4) Switch Level Modeling {in which the transistor level of hardware is dealt with}
Lab Tasks: (8 marks)

Lab Task 1: (3 marks)
Write the Verilog Code using Gate Level modeling for the following circuit. List the code for design as well as
stimulus below:

// Lab Task:01 Module name Task1!
module Task1(SUM,CARRY,A,B);
input A,B;
output SUM,CARRY;
wire w1,w2,w3,w4; //w1,w2,w3,w4 represent wires
not a1(w1,A);
and b1(w2,w1,B);
not a2(w3,B);
and b2(w4,A,w3);
or c1(SUM,w2,w4);
and b3(CARRY,A,B);
endmodule
module Test1;
reg Inp1 , Inp2;
wire Out1 , Out2;
Task1 t1(Out1,Out2,Inp1,Inp2);
initial
begin
#110 Inp1=1'b0 ; Inp2=1'b0; // Time Delay 110 seconds!
#110 Inp1=1'b0 ; Inp2=1'b1;
#110 Inp1=1'b1 ; Inp2=1'b1;
#110 Inp1=1'b1 ; Inp2=1'b0;
#110;
end
endmodule

Circuit form;
Wave form;
Lab Task 2 (2 marks)
Modify the test bench to print the results of the simulation using the Verilog $monitor statement. The output
should look like this
t = 10, A = 0, B = 0, SUM = 0 CARRY = 0 and so on.
Example Syntax for $ monitor $monitor ("req0=%b,req1=%b,gnt0=%b,gnt1=%b", req0,req1,gnt0,gnt1);

Output will be displayed whenever input will change, e.g.,:
//Task2 module name is Task2

module Task2(SUM,CARRY,A,B);
input A,B;
Output;

Wave form;
Circuit form;
Lab Task 3:(3 marks)
After determining the function performed by the circuit given in Lab Task 1, write the Verilog description of the
circuit at dataflow level. Comment on the two different modeling levels you used to model the same circuit.
(Paste snapshots of the codes and stimulus’s below)
Dataflow modeling utilizes Boolean equations, and uses a number of operators that can apply on
inputs to produce outputs operators like +, - , & , !, ~ , etc. Boolean equations are used in place of
logical gates’ modules. Some of the dataflow operators are shown below in modules.
 Continuous Assignment:
The keyword assign declares a continuous assignment that binds the Boolean expression on the
right-hand side (RHS) of the statement to the variable on the left-hand side (LHS). Verilog
arithmetic and logical operations can be used in assign .The syntax of assign is as follows:
assign <net_name> = <expression>;
assign out = in1 & in2;
Write your code and result below;
Output here : (Code on page:9)

Circuit form;
Wave form;

module Task3(SUM,CARRY,A,B); //LabTask:03//
input A,B;
output SUM,CARRY;
wire w1,w2,w3,w4;
assign w1 = ~A; //not operation
assign w2 = w1&B; // and operation
assign w3 = ~B; //not operation
assign w4 = A&w3; //and operation
assign SUM = w2|w4; // or operation
assign CARRY = A&B; //and operation
endmodule
module Test3; //Test module name is Test3.
reg Inp1 , Inp2;
wire Out1 , Out2;
Task3 t1(Out1,Out2,Inp1,Inp2);
initial
begin
#80 Inp1=1'b0 ; Inp2=1'b0;
#80 Inp1=1'b0 ; Inp2=1'b1;
#80 Inp1=1'b1 ; Inp2=1'b1; //Time Delay 80 Second.
#80 Inp1=1'b1 ; Inp2=1'b0;
#80;
end
endmodule

Department of Electrical Engineering: Lab No # 2: Introduction To Verilog (CLO4, P3)

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Department of Electrical Engineering: Lab No # 2: Introduction To Verilog (CLO4, P3)

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Department of Electrical Engineering

Faculty Member: Ma’am Quartulain Dated: 13-3-2021

Semester: 2nd Section: Bese-11A

SE-221: Digital Logic Design

CLO4/PLO4 CLO4/PLO5 CLO6/PLO8 CLO7/PLO9

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

EE-221: Digital Logic Design Page 1

This Lab has been divided into two parts.

In first part you will be introduced to Verilog and Gate-Level Modeling.

 Understand HDL and compare it with normal programming languages.

EE-221: Digital Logic Design Page 2

Ans(a) : HDL Stands for Hardware Description Languages.

Ans(b) : Two Standard version of HDL are:

Ans(c) : Levels of abstraction in Verilog HDL are given below:

Lab Tasks: (8 marks)

EE-221: Digital Logic Design Page 3

wire w1,w2,w3,w4; //w1,w2,w3,w4 represent wires

reg Inp1 , Inp2;

wire Out1 , Out2;

#110 Inp1=1'b0 ; Inp2=1'b0; // Time Delay 110 seconds!

#110 Inp1=1'b0 ; Inp2=1'b1;

#110 Inp1=1'b1 ; Inp2=1'b1;

#110 Inp1=1'b1 ; Inp2=1'b0;

EE-221: Digital Logic Design Page 4

Lab Task 2 (2 marks)

t = 10, A = 0, B = 0, SUM = 0 CARRY = 0 and so on.

Example Syntax for $ monitor $monitor ("req0=%b,req1=%b,gnt0=%b,gnt1=%b", req0,req1,gnt0,gnt1);

//Task2 module name is Task2

EE-221: Digital Logic Design Page 6

Lab Task 3:(3 marks)

Output here : (Code on page:9)

EE-221: Digital Logic Design Page 8

assign w1 = ~A; //not operation

assign w2 = w1&B; // and operation

assign w3 = ~B; //not operation

assign w4 = A&w3; //and operation

assign SUM = w2|w4; // or operation

assign CARRY = A&B; //and operation

module Test3; //Test module name is Test3.

reg Inp1 , Inp2;

wire Out1 , Out2;

#80 Inp1=1'b0 ; Inp2=1'b0;

#80 Inp1=1'b0 ; Inp2=1'b1;

#80 Inp1=1'b1 ; Inp2=1'b1; //Time Delay 80 Second.

#80 Inp1=1'b1 ; Inp2=1'b0;

EE-221: Digital Logic Design Page 9

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