Sir Syed CASE Institute of Technology, Islamabad

EE2401 Digital Logic Design

Lab No. 4

Name of Student: Roll No. :

Date of Experiment: Report submitted on:

Marks obtained: Instructor’s Signature:

Instructor: Engr. Safdar Munir

 Introduction to Verilog, Implementation of All Logic Gates
in Verilog.
Hardware Description Language (HDL)
Objectives
a. To understand the concept of Hardware Description Language.
b. To understand and learn syntax of Verilog HDL.
c. To learn how to use Modelsim
d. To implement all logic gates using Verilog

Introduction:
A hardware description language (HDL) used in the design, verification, and implementation of
digital logic chips. It used to describe electronic circuits and digital systems. In practice it is
generally used for simulating, testing, and programming PLD (programmable logic devices) or
other similar hardware.
 On paper it is almost impossible to check the working of a circuit containing hundreds or
thousands of gates.
A hardware description language is used for describing and testing logic circuits. It is a text based way to
talk about designs.

Verilog HDL:
Verilog is very much similar to C, it is used by hardware designers in industry and academia. It is
an easy to learn language. Verilog HDL although looks similar to C but it is not a software
programming language, rather it is a hardware description language. It is important for verilog
programmers to know about the hardware.

Simulator:
The simulator that we will use is the ModelSim simulator.
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Verilog Program
A verilog program consists of two parts;
1. Device Under Test (DUT).
2. Stimulus

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 1. DUT
A digital design coded in Verilog consists of one or several modules. The contents of a module
are also critical from synthesis perspective. A module is the basic building block in Verilog.

Verilog •C/C++
void main()
module name (portlist); {

// data types declaration // data types declaration

.. ..
… …
// data manipulation // data manipulation

endmodule }

Modules start with keyword module and end with keyword endmodule.

Module for AND gate

module my_and(in1,in2,o);
input in1,in2;
output o;
and aa(o,in1,in2);
endmodule

Module Ports:
 These are similar to the pins on chip.
 Ports provide a way of communication with outside world.
 The Ports of a module can be input, output or inout.

Module Declarations:

METHOD # 1 METHOD # 2
module name (in1, in2,out); module name (input in1,in2,
output out);
input in1,in2;
output out;

endmodule endmodule

2. Stimulus / Test Bench:

To provide input values to our design and to get the required output, we need a test bench. It is
written in separate or same file in which main module has been designed.

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The following is an example of a stimulus in verilog.

Stimulus for AND gate:

module stim_and;
reg in1,in2;
wire o ;
my_and n1 (in1,in2,o);
initial
begin
in1=0;
in2=0;
#20 in1=0;
in2=1;
#20 in1=1;
in2=0;
#20 in1=1;
in2=1;
end
endmodule.
------------------------------------------------------------------------------------------------------------------
Constants
A constant in Verilog can be of any size and it can be written in decimal, binary, octal or
hexadecimal format. The decimal is the default format. A number 13 can be written in different
format as shown.

Decimal (default)
w = 12; r = 14;
Binary
w = 4’b1100; r = 4’b1110;
Time Control
The programmer can insert delays in the code by placing #<number>. On encountering this
statement, the simulation halts the execution of the statement until <number> time units have
passed. The Control is released from that statement or block so that other processes can
execute.

Initial block:
Initial block executes only once starting at t=0 simulation time.

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Initial block starts with initial keyword, if multiple statements are used in an initial block, they
are enclosed within begin and end Verilog constructs.
1. This block is used only in stimulus.
2. Simulator Kernel executes initial block until the execution come to a #delay operator.
Then the execution is suspended and the simulator kernel places the execution of this
block in the event list for delay-time units in the future.
3. After completing delay-time units, the execution is resumed where it was left off.
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Levels of Abstraction
Verilog is a hardware description language. The HW can be described at several levels of details.
To capture these details Verilog provides the designer the following four levels of abstractions:
1. Switch level
2. Gate level
3. Dataflow level
4. Behavioral or algorithmic level
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Gate Level:
Gate level modeling is also a low level of abstraction and not used for coding design at RTL
(Register Transfer Level) level. Our interest in this level is from the fact that the Synthesis tools
compile high level code and generate code at gate level. The code at gate level is built from
Verilog primitives. These primitives are built-in gate-level models of basic functions. These basic
functions include nand, nor, and, or, xor, not etc. Modeling at this level requires describing the
circuit using logic gates. This description looks much like an implementation of a circuit in logic
design course. Delays can also be modeled in this level. A typical gate instantiation is
and instance-name (out, in1, in2, in3, …)
First parameter in the primitive, out, is always one-bit output following by several one bit
inputs in1, in2, in3.
In Verilog, #delay specifies the delay from input to output of the gate.

Example

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 1. 2×1 MUX

------------------------- MAIN MODULE ---------------------------

module my_mux21_gate(in1,in2,sel,out);
input in1,in2,sel;
output out;
wire out1,out2,out3;
not aa(out3,sel);
and bb(out1,in1,out3);
and cc(out2,sel,in2);
or dd(out,out1,out2);
endmodule

----------------------- STIMULUS -------------------------------

module stim_mux21_gate;
reg in1,in2,sel;
wire out;
my_mux21_gate rr(in1,in2,sel,out);
initial
begin
in1=0;
in2=1;
sel=0;
#20 in1=1;
in2=0;
sel=0;
#20 in1=1;
in2=0;
sel=1;
end
endmodule

-------------------------------------------------------------------

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Output

Example

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Code
---------------------MAIN MODULE ---------------------------------

module my_circuit( a,b,o);

input a,b;
output o;
wire o1,o2;
nand aa(o1,a,b);
or bb(o2,a,b);
and cc(o,o1,o2);
endmodule

-------------------- STIMULUS ----------------------------------

module stim_circuit;
reg a,b;
wire o;
my_circuit dd(a,b,o);
initial
begin
a=0;
b=0;
#20 a=0;
b=1;
#20 a=1;
b=0;
#20 a=1;
b=1;
end
endmodule

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Output

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 LAB TASKS
1. Implement XOR with gate level modeling.

2. Implement the following circuit using gate level modeling.

A B C Q
1 0 1 0
0 0 1 1
1 1 1 1
3. Implement the following circuit using gate level modeling.

A B C D O

0 0 0 0 0

0 0 0 1 1

1 0 1 0 0

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