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    Hardware Description Language (HDL) What Is The Need For Hardware Description Language? Model, Represent, and Simulate Digital Hardware

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    Gohar Ayub
    The document discusses Hardware Description Language (HDL) and Verilog HDL. It covers the need for HDLs to model, represent and simulate digital hardware. It describes basic Verilog concepts like modules, ports, data types, operators and modeling styles. It provides examples of structural, dataflow and behavioral modeling in Verilog. It also covers procedural constructs, conditional statements, registers and blocking/non-blocking assignments.

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    Attribution Non-Commercial (BY-NC)
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    Hardware Description Language (HDL) What Is The Need For Hardware Description Language? Model, Represent, and Simulate Digital Hardware

    Uploaded by

    Gohar Ayub
    32 views26 pages
    The document discusses Hardware Description Language (HDL) and Verilog HDL. It covers the need for HDLs to model, represent and simulate digital hardware. It describes basic Verilog concepts like modules, ports, data types, operators and modeling styles. It provides examples of structural, dataflow and behavioral modeling in Verilog. It also covers procedural constructs, conditional statements, registers and blocking/non-blocking assignments.

    Original Description:

    electrical

    Original Title

    verilog_1

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    The document discusses Hardware Description Language (HDL) and Verilog HDL. It covers the need for HDLs to model, represent and simulate digital hardware. It describes basic Verilog concepts like modules, ports, data types, operators and modeling styles. It provides examples of structural, dataflow and behavioral modeling in Verilog. It also covers procedural constructs, conditional statements, registers and blocking/non-blocking assignments.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    32 views26 pages

    Hardware Description Language (HDL) What Is The Need For Hardware Description Language? Model, Represent, and Simulate Digital Hardware

    Uploaded by

    Gohar Ayub
    The document discusses Hardware Description Language (HDL) and Verilog HDL. It covers the need for HDLs to model, represent and simulate digital hardware. It describes basic Verilog concepts like modules, ports, data types, operators and modeling styles. It provides examples of structural, dataflow and behavioral modeling in Verilog. It also covers procedural constructs, conditional statements, registers and blocking/non-blocking assignments.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 26

    Hardware Description Language (HDL) What is the need for Hardware Description Language?

    ? Model, Represent, And Simulate Digital Hardware


    Hardware Concurrency Parallel Activity Flow Semantics for Signal Value And Time

    Special Constructs And Semantics


    Edge Transitions Propagation Delays Timing Checks

    VERILOG HDL Basic Unit A module Module


    Describes the functionality of the design States the input and output ports

    Example: A Computer
    Functionality: Perform user defined computations I/O Ports: Keyboard, Mouse, Monitor, Printer

    Module General definition


    module module_name ( port_list ); port declarations; variable declaration; description of behavior endmodule

    Example
    module HalfAdder (A, B, Sum Carry); input A, B; output Sum, Carry; assign Sum = A ^ B; //^ denotes XOR assign Carry = A & B; // & denotes AND endmodule

    Lexical Conventions Comments


    // Single line comment /* Another single line comment */ /* Begins multi-line (block) comment All text within is ignored Line below ends multi-line comment */

    Number
    decimal, hex, octal, binary unsized decimal form size base form include underlines, +,-

    String
    " Enclose between quotes on a single line"
    4

    Lexical Conventions (cont.) Identifier


    A ... Z a ... z 0 ... 9 Underscore

    Strings are limited to 1024 chars First char of identifier must not be a digit Keywords: See text.

    Operators: See text. Verilog is case sensitive


    5

    Description Styles Structural: Logic is described in terms of Verilog gate primitives Example: not n1(sel_n, sel); and a1(sel_b, b, sel_b); and a2(sel_a, a, sel); or o1(out, sel_b, sel_a); b sel
    n1 a1

    sel_b

    sel_n

    a
    a2 sel_a

    o1

    out

    Description Styles (cont.) Dataflow: Specify output signals in terms of input signals Example: assign out = (sel & a) | (~sel & b); b sel
    sel_b sel_n

    out
    sel_a

    a
    7

    Description Styles (cont.) Behavioral: Algorithmically specify the behavior of the design

    Example: if (select == 0) begin out = b; end else if (select == 1) begin out = a; end

    a b

    2x1 MUX sel

    Black Box

    out

    Structural Modeling Execution: Concurrent Format (Primitive Gates):


    and G2(Carry, A, B);

    First parameter (Carry) Output Other Inputs (A, B) - Inputs

    Behavioral Modeling Example:


    module mux_2x1(a, b, sel, out); input a, a, sel; output out; always @(a or b or sel) begin if (sel == 1) out = a; else out = b; end endmodule

    Sensitivity List

    10

    Behavioral Modeling (cont.) always statement : Sequential Block Sequential Block: All statements within the block are executed sequentially When is it executed?
    Occurrence of an event in the sensitivity list Event: Change in the logical value

    11

    Procedural Constructs Two Procedural Constructs


    initial Statement always Statement

    initial Statement : Executes only once always Statement : Executes in a loop Example:
    initial begin Sum = 0; Carry = 0; end always @(A or B) begin Sum = A ^ B; Carry = A & B; end

    12

    Conditional Statements if Statement Format:


    if (condition) procedural_statement else if (condition) procedural_statement else

    procedural_statement Example:
    if (Clk) Q = 0; else Q = D;
    13

    Verilog: The Module

    Gate Level Description

    Procedural Assignment with always

    Verilog Registers

    Mix-and-Match Assignments

    The case Statement

    The Power of Verilog: Integer Arithmetic

    Dangers of Verilog: Incomplete Specification

    Avoiding Incomplete Specification

    The Sequential always Block

    Blocking vs. Nonblocking Assignments

    Assignment Styles for Sequential Logic

    Test Bench - Generating Clock (cont.)


    Initialize the Clock signal initial begin Clock = 0; end Caution: Clock is of data type wire, cannot be used in an initial statement Solution: reg Clock; initial begin Clock = 0; end forever loop can also be used to always begin generate clock #10 Clock = ~ Clock; end
    26

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