Compressed Pattern Diagnosis For Scan Chain Failures

Yu Huang, Wu-Tung Cheng, Janusz Rajski

Mentor Graphics Corporation Wilsonville, OR, USA

hardware block called Compactor that is placed along the

Abstract scan path on the output side transforms the data captured
In scan based designs, 10%-30% defects are in scan in the large number of internal scan chains into a data
chains. Hence scan chain fault diagnosis becomes an stream that is delivered on few scan output channels for
important process for silicon debug and yield ramp up. comparison with the expected values by the ATE. EDT
With embedded compression techniques getting popular, has successfully been adopted by many companies to
chain diagnosis on devices with the embedded achieve dramatic reduction in test data volume and test
compression techniques becomes a challenge. In this application time. EDT architecture is illustrated in Figure
paper, we provide a general methodology that can be 1.
applied for performing chain diagnosis in the context of
any embedded compression techniques with any existing
chain diagnosis algorithms. The proposed methodology
enables seamless reuse of the existing chain diagnosis
infrastructure with compressed test data. Experimental
results show that with compressed patterns, the chain
diagnosis resolution can be enhanced up to one order of
magnitude with only 25% of failure cycles collected from
ATE, compared to the diagnosis results with
uncompressed patterns.

1. Introduction

With the increase of design size and the importance of at-

speed test and multiple-detect test, the test data volume far
exceed the capacities of the automatic test equipment
(ATE). Due to the limited bandwidth between the IC and
Figure 1: High Level EDT Architecture
the ATE, this increased test data also results in increased
test time and hence increased test costs.
IC manufacturing test typically includes two phases. The
Several compression techniques such as Embedded
first test phase is chain test. The purpose of chain test is to
Deterministic Test (EDT) [RAJ02], OPMISR [BAR02],
check if the scan chains work as expected. With the
X-Compactor [MIT02] and X-DBIST [WOH03] have
compression techniques such as EDT, chain test also
recently been proposed to contain the test costs while
checks the embedded compression logic in addition to
achieving the required test quality levels. These
scan chains. If the chain test passed, it will go to the
compression techniques involve two complimentary
second test phase, which is called scan test. The purpose
aspects – hardware that is placed on chip and software
of scan test is to check if there are any faults in the system
ATPG techniques that exploit the on-chip hardware to
logic.
create highly compressed test sets that give dramatic
reduction in test data volume and test application time. In When a test failed, automatic diagnosis plays a vital role
EDT for example, a hardware block called Decompressor in the failure analysis process wherein the root cause of a
is placed along the scan path between the scan input failure is determined. Failure analysis has several
channels and inputs of the scan chains. This applications – for example yield learning and
Decompressor performs a transformation of the data that improvement when a new technology is introduced or
is supplied by the ATE on few scan input channels and identifying systemic manufacturing issues that impact the
feeds the large number of internal scan chains. A yield. The diagnosis results report the suspect sites that

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are used in probing the IC with devices such as scanning Multiple faulty chain diagnosis is discussed in Section 5
electron microscope (SEM). followed by the conclusions drawn in Section 6.
Accordingly, there are two types of fault diagnosis. Chain
diagnosis is performed to locate which scan chain(s) and 2. Prior Chain Diagnosis Algorithms
scan cell(s) have defects. Scan diagnosis is performed to
identify the suspect fault sites in the system logic. In this
paper, we investigate the chain diagnosis in the context of The existing chain diagnosis algorithms can be classified
embedded compression techniques. into two main categories. The first category is hardware-
based chain diagnosis, which uses special scan cell and
Without embedded compression techniques, automated additional scan circuitry [SCH92] [WU98] [EDI95]
chain diagnosis has widely been studied [KUN94] [NAR97]. The second category is software-based chain
[GUO01] [STA01] [HUA03] [HUA04]. With the diagnosis [KUN94] [GUO01] [STA01] [HUA03]
compression techniques, however, the automated chain [HUA04]. The hardware-based methods use some special
diagnosis needs additional efforts. This is due to the fact scan chain designs to facilitate the scan chain diagnosis
that the data that is applied to IC and the response that is process. E.g., in [SCH92], it is proposed to connect the
captured undergo a transformation. Thus what is observed output of each scan cell to another scan cell on another
on the ATE from scan channel outputs is a compacted scan chain such that its value can be observed by the other
version of what is captured in the internal scan elements scan chain in diagnosis mode. In [EDI95], XOR gates are
of the IC. Automated fault diagnosis has to be able to take inserted between scan cells to enhance chain diagnosis. In
failure log corresponding to the compacted response [NAR97] special set/reset circuitry is used to enhance
stream and determine the suspects. One way, to avoid chain diagnosis. In [WU98], special circuitry is proposed
having to deal with the failure log of compacted response to flip and set/reset scan cells to identify defective cells.
stream would be to completely bypass the on-chip
compression hardware. Doing so provides direct access to The software-based algorithms do not need any
the scan cells enabling the application of the well- modification of the basic scan circuitry. In [KUN94],
established standard ATPG based fault diagnosis. sequential ATPG algorithm is used to diagnose chain
However, one of the major drawbacks of such an failures. In [GUO01] and [STA01] fault simulation and
approach is the requirement for two separate test sets – a matching algorithms are applied to identify the defective
compressed test set for volume production testing scan cells. In [HUA03] and [HUA04], algorithms are
purposes to contain the test costs and an uncompressed proposed to diagnose realistic chain defects by targeting
test set for fault diagnosis purposes. In addition, such an intermittent scan chain faults. Compared with the
approach does not facilitate on-line diagnosis, which is hardware-based methods, software-based techniques are
fast diagnosis based on the volume production test results. more attractive due to no design modification.
Thus it is desirable to enhance the fault diagnosis Without embedded compressions, a chain diagnosis
techniques to be applicable in the context of compressed procedure typically includes two steps.
test sets.
Step 1: Identify faulty chains and fault types by chain
In recent work [CHE04], a compactor-independent direct patterns [GUO01] [HUA03].
scan diagnosis methodology was proposed. For chain
diagnosis, however, there is no prior work to solve the
problem. In this paper, we propose a compactor- Table 1: Various Scan Chain Fault Types
independent compressed pattern chain diagnosis Fault Types Unloaded Values- Unloaded Values-
Permanent Faults Intermittent Faults
methodology, which is based on circuit transformation
technique that can be applied for performing chain Slow-to-Rise 00100010001X 00110010001X
diagnosis in the context of any compression method. The
Slow-to-Fall 01110111011X 01110011011X
proposed technique enables seamless reuse of the existing
chain diagnosis infrastructure. Slow 01100110011X 00100111011X
The rest of this paper is outlined as follows. Section 2 Fast-to-Rise X01110111011 X01110110011
reviews chain diagnosis methodologies without embedded Fast-to-Fall X00100010001 X00100110001
compression techniques. Section 3 outlines a general flow
and algorithm for chain diagnosis in the context of Fast X00110011001 X00100111001
embedded compression techniques. Moreover, single Stuck-at-0 000000000000 001000010000
faulty chain diagnosis by using the proposed methodology
is illustrated by a popular industrial compactor – EDT Stuck-at-1 111111111111 101111111011
compactor. Experimental results on single faulty chain Stuck-at-X  100100111110
diagnosis with EDT compactor are given in Section 4.

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This step is illustrated by a chain test example given in the test response after compaction. The original circuit is
Table 1. Suppose a scan chain is loaded with a chain then transformed into a circuit with pseudo-scan chains by
pattern 001100110011, where the leftmost bit is loaded incorporating compactor function Φ. This step is same as
into the scan cell (cell 11) connected to scan chain input proposed in [CHE04].
and the rightmost bit is loaded into the scan cell (cell 0)
connected to scan chain output. Column 2 in Table 1 gives (2) Read the failure log file for chain test and identify
the unloaded faulty values for each type of permanent faulty chains and fault types. In this step, masking patterns
fault. Column 3 gives examples of the unloaded faulty (explained below) are required to apply in chain test. It is
values for each type of intermittent fault. Note that the straightforward to identify faulty chain(s) from pseudo-
“X”s depend on the previous or the next chain pattern. scan chains by using masking chain patterns.

Step 2: Locate the faulty scan cells by special scan (3) Read the failure log file for scan test. With scan test
circuitry (hardware-based diagnosis) or by simulation of patterns, apply any previously proposed chain diagnosis
scan patterns (software-based diagnosis). algorithm by performing the fault simulation on faulty
scan chain against the transformed circuit. Compare the
In this step, suspect scan cells will be located. This is the simulation results with the compacted failure data
step where hardware-based chain diagnosis is different collected from tester. Report the best matching scan
from software-based chain diagnosis. In hardware-based cell(s) as suspect(s).
chain diagnosis, some known values are loaded into the
faulty chain by special chain circuitry (e.g. special The advantages of the proposed chain diagnosis
set/reset). The defective scan cells will be located during methodology include:
the unloading procedure. For example, it is known that (1) It can be generally applied to a variety of embedded
chain1 has a stuck-at-0 fault in the first step. Then the compression techniques.
circuit is set to chain diagnosis mode and all the scan cells
on chain1 are set to “1” by using special scan chain (2) It can exploit a variety of existing scan chain
circuitry. During the unloading procedure, the first cell diagnostic algorithms.
unloaded a “0” will tell where the defective scan cell is. In (3) As to be shown later in Section 4, chain diagnosis with
software-based diagnosis, this step is usually based on embedded compressions can achieve better diagnosis
simulation with scan patterns. A fault is “injected” on a resolution with less collected failure cycles.
scan cell in software simulation context. Loading values
in the downstream of this scan cell on this faulty chain
will be modified for all scan patterns due to the fault.
E.g., a scan pattern has good machine loading value
001110011010 on chain1. If we inject a stuck-at-0 fault
on scan cell 3, the loading value will be modified as
001110010000. After pulsing the capture clock, the
captured values in the upstream of the faulty scan cell on
this faulty chain will be modified. E.g., if the simulated
captured value is 101011101011, the unloading values
will be 000000000011. This simulation results will be
compared with the observed results from ATE. The best
matching cell(s) will be reported as suspect(s). However,
these chain diagnosis methodologies cannot be applied
directly for designs with embedded compression
techniques.

3. Proposed Scan Chain Diagnosis

Methodology With Compressed Patterns
Figure 2: An Example of a Design with an EDT
In the following sections, we focus on single faulty scan Compactor.
chain diagnosis methodology. Diagnosis for multiple
faulty chains will be discussed in Section 5.
In the rest part of this section, we use EDT Compactor as
A general flow of diagnosing defects in scan chains with an example to illustrate the proposed scan chain
compressed patterns includes the following three steps. diagnostic methodology. EDT Compactor [RAJ02] is a
(1) Model a compactor as a function Φ such that Φ(R) = r, linear space compactor. It is essentially an XOR tree with
where R is the test response before compaction and r is scan chain masking logic to select one chain per channel

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to observe. A simple example circuit with EDT Chain1 Chain2 Compactor Output
Compactor is shown in Figure 2. It has 2 scan chains that Load Load
Expected Observed
feed into an XOR gate.
Pattern 1 101 001 101 000
Assuming a stuck-at-0 fault is at cell 1 of chain 1, we
apply the 3 steps proposed above on this example. Pattern 2 110 100 100 100

Step (1): We transform the circuit into a circuit with an

embedded compactor function and build a pseudo scan
For this example, chain pattern 1 failed and chain pattern
chain. We represent the test responses for each pattern
2 passed. We deduce that chain 1 has a stuck-at-0 fault.
before compaction and after compaction as matrixes R
and r respectively. The compaction function is Φ(R)=r. Step (3): To narrow down the defect location on chain 1,
For the given example, Φ=[1 1] if no scan chain is regular scan patterns are used. One candidate fault is
masked, Φ=[0 1] if the first scan chain is masked and injected at a time. Fault simulation is then performed on
Φ=[1 0] if the second scan chain is masked. Note that Φ the transformed circuit by taking consideration of
could be pattern dependent. compaction function Φ on the test responses. Then the
compacted simulation results on the channel outputs are
Step (2): For EDT compactor [RAJ03], a masking pattern compared with the data observed from the tester. Finally,
is a pattern such that only one scan chain is observed from the most matched suspect cell(s) is reported. The
one compactor channel output while all the other scan compressed pattern chain diagnosis is achieved.
chains connecting to the same channel output are masked
(blocked). An example of EDT masking logic is
4. Experimental Results
illustrated in Figure 3. A masking code is shifted into the
mask register. After decoding, only chain output 1 is
observed from channel output 1 while all the other chains By using EDT as an example, we perform two sets of
are masked for this specific masking pattern. experiments. The purpose of the first set of experiments
is to investigate the diagnosis accuracy, resolution and
performance of the proposed compressed pattern chain
diagnosis algorithm. The purpose of the second set of
experiments is to investigate how the diagnosis resolution
varies with the number of collected failure patterns.
We use one small circuit (Ckt1) and one large industrial
circuit (Ckt2) to perform the experiments, hoping the
experimental results are valid for a large number of
designs of different sizes. Information about these two
circuits is given in Table 3. The numbers of gates, scan
cells and scan chains are given for these two circuits.
After incorporating EDT, the compaction ratios used for
the experiments are set to 2X, 4X, 8X, 16X, 32X and 64X.
The numbers of scan channels are fixed. Ckt1 has 2 scan
channels and Ckt2 has 14 scan channels respectively. For
Figure 3: EDT Compactor Masking Logic a compaction ratio N, we break each original scan chain
into N scan chains in a balanced manner such that the
length of each internal scan chain is close to 1/N of the
In EDT chain test set, each internal chain is observed original scan chain length. We connect every N scan
uniquely from one channel output with one masking chain chains to one scan channel output through EDT
test pattern. Hence, for a NX compaction configuration, it compactor. For chain defect, the number of failure cycles
must have at least N chain masking patterns. Using per pattern is typically proportion to the faulty scan chain
masking chain patterns, it is straightforward to identify the length. To make a fair comparison of the diagnosis results,
faulty chain and to model the chain fault. In the given we have to collect the similar number of failure cycles no
example, assuming chain pattern 1 is a masking pattern to matter which N we select. Thus for a NX compaction
observe chain 1 and chain pattern 2 is a masking pattern to scheme, the number of failing patterns we used for chain
observe chain 2. Also suppose the patterns have loading diagnosis is about N times of the patterns for the situation
values on internal chains and expected / observed values without EDT. E.g. we inject a stuck-at-1 fault at one scan
on channel output shown in Table 2. cell in Ckt1. Without EDT, we apply 5 scan patterns on
Ckt1 with 2 scan chains and collect about 500 failure
cycles. If set N=16, Ckt1 has 32 internal scan chains with
Table 2. An Example of EDT Chain Patterns

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2 EDT compactor channels. We now can apply 80 scan failure cycles collected from ATE, compared to the same
patterns and collect about 500 failure cycles. design without EDT. As illustrated in Table 4, applying
320 patterns to Ckt1 design with 64X EDT only results in
397 failure cycles in average while applying 5 patterns to
Table 3. Circuit Information Ckt1 design without EDT results in 473 failure cycles in
Ckt1 Ckt2 average. As illustrated in Table 5, applying 256 patterns to
# Gates 9.4K 6.5M Ckt2 design with 32X EDT results in 126K failure cycles
in average while applying 8 patterns to Ckt2 design
# Scan Cells 495 529826 without EDT results in 139K failure cycles in average.
# Scan Chains 2 14 This is because that EDT designs have much shorter
faulty chains, which causes much less number of failure
cycles and these failures are compacted at the channel
output.
4.1 Experiments with the Proposed Chain Diagnosis
Methodology Therefore we collect 320 failed patterns for Ckt1 with
64X EDT and 256 failed patterns for Ckt2 with 32X EDT,
which are shown in column 6 of Tables 4 and 5. To
To validate the proposed chain diagnosis methodology compare the diagnosis results with the same number of
and compare the chain diagnosis accuracy, resolution and patterns, we also collect 320 failed patterns for Ckt1
performance with and without EDT, we create chain without EDT and 5 failed patterns for Ckt1with 64X EDT,
failure test cases in the following way. as illustrated in Columns 4 and 5 in Table 4. Also, we
collect 256 failed patterns for Ckt2 without EDT and 8
Since Ckt1 has only 495 scan cells, we make 495 test failed patterns for Ckt2 with 32X EDT, as illustrated in
cases by injecting one permanent stuck-at-1 fault per test Columns 4 and 5 in Table 5.
case. Each case has a fault at a different scan cell. With
Ckt1, we also make 495 test cases by injecting one
intermittent stuck-at-1 fault per test case. For each Table 4. Ckt1 Chain Diagnosis Results
injected intermittent fault, we set fault triggering No No EDT EDT
probability to 50%. EDT EDT 64X 64X
# Patterns 5 320 5 320
Similarly, we randomly select 100 scan cell locations in
Avg. #
Ckt2 to inject one fault per case. We end up with 100
Failure 473 30126 6 397
permanent stuck-at-1 failure cases (Prob=100) and 100 Cycles
intermittent stuck-at-1 (Prob=50) failure cases by using Avg. Prob=100 10.38 3.01 2.57 1.01
Ckt2. # Prob=50 20.98 6.11 3.03 1.62
For these (495*2+100*2) chain failure cases, we first get Susp.
one failure log file per case by simulating the patterns |Susp| Prob=100 37.7% 80.7% 50.2% 100%
against the circuit with the injected fault. Note that the ≤2 Prob=50 13.6% 44.3% 38.1% 57%
failure response is compacted if using EDT. We then Avg. Prob=100 0.54 2.32 0.15 1.21
perform chain diagnosis on each failure log file. We use Time Prob=50 4.76 8.71 0.32 2.05
EDT with 64X compaction for Ckt1 and 32X compaction (s)
for Ckt2 in the experiments. All the diagnosis reports
include the injected failure scan cell. So diagnosis Table 5. Ckt2 Chain Diagnosis Results
accuracy has no problem. The diagnosis resolution and No No EDT EDT
performance are shown in Table 4 and Table 5 for Ckt1 EDT EDT 32X 32X
and Ckt2 respectively. # Patterns 8 256 8 256
In Tables 4 and 5, row 2 shows the number of failure Avg. #
patterns used for diagnosis. Row 3 shows the average Failure 139K 4535K 5.5K 126K
Cycles
number of failure cycles over (495*2) test cases for Ckt1
Avg. Prob=100 19.75 4.9 16.9 1.25
in Table 4 and (100*2) test cases for Ckt2 in Table 5.
# Prob=50 87.44 19.2 78.8 13.9
As shown in Column 3 of Tables 4 and 5, we initially Susp.
collect 5 failed patterns for Ckt1 and 8 failed patterns for |Susp| Prob=100 50% 91% 50% 93%
Ckt2 without EDT. These numbers of patterns are selected ≤2 Prob=50 9% 25% 13% 35%
randomly such that it leads to reasonable number of Avg. Prob=100 358 2468 296 1621
failure cycles in this scenario. As we pointed out above, Time Prob=50 607 3077 592 2674
for a design with NX EDT compaction, N times of scan (s)
patterns can be applied resulting in similar number of

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Rows 4 and 5 in Tables 4 and 5 show the average number without compressions, a datalog of such size would result
of the reported suspects after diagnosis. The diagnosis in only 8 failing patterns given that the average chain
resolution is defined as 1 / (# Average Suspects). When length is more than 37K. Collecting this magnitude of
applying the same number of scan patterns (i.e., data on some types of ATE may take hours. In this
comparing column 3 vs. column 5 and column 4 vs. subsection, we investigate how the diagnosis resolution
column 6), the diagnosis resolution is always enhanced by varies with the number of collected failure patterns in the
incorporating EDT for both Ckt1 and Ckt2. The context of EDT.
enhancement ratios vary for different circuits, different
number of patterns and different fault types. Note that
when applying the same number of patterns, the number Table 6. Average # Suspects Vs. # Patterns
of failure cycles becomes much less if incorporating EDT. Ckt1 with 64XEDT Ckt2 with 32XEDT
When applying the similar number of failure cycles (i.e., #Patterns Avg. Suspects #Patterns Avg. Suspects
comparing column 3 vs. column 6), for Ckt1, the
diagnosis resolution is improved about 10 times and 13 5 2.57 8 16.9
times for permanent faults and intermittent faults 10 2.22 16 6.78
respectively by incorporating EDT. The diagnosis
resolution for Ckt2 is improved 15.8 times and 6.3 times 20 1.79 32 2.16
for permanent faults and intermittent faults respectively 40 1.25 64 1.53
by incorporating EDT.
80 1.08 128 1.25
Rows 6 and 7 in Tables 4 and 5 show the percentage of
the test cases with only one or two suspects after chain 160 1.03 256 1.25
diagnosis. If the number of suspects is small (e.g. less than 320 1.01 - -
3), it will be quite helpful for failure analysis at physical
level. The experimental results indicate that for permanent
stuck-at-1 fault, we have 100% chances for Ckt1 and 93% The average number of suspects vs. the number of failed
of chances for Ckt2 to get useful diagnosis results for patterns is illustrated in Table 6 and plotted in Figure 4
failure analysis if we use EDT with reasonable number of when using Ckt1 with 64X EDT and Ckt2 with 32X EDT.
failure cycles. We calculate the average number of suspects by using 495
The last two rows in Tables 4 and 5 show the average permanent stuck-at-1 test cases for Ckt1 and 100
diagnosis run time for each set of test cases. The run time permanent stuck-at-1 test cases for Ckt2.
of chain diagnosis is determined by two factors: (1) the
number of simulated scan patterns and (2) the number of
candidates that need simulation.
Because for the similar number of failure cycles, the
simulated patterns with NX EDT is typically N times of
the patterns without EDT, the diagnosis run time with
EDT designs is usually longer due to reason (1) list above.
However, for EDT designs, because they have shorter
chains, they usually have a smaller number of candidates
to simulate than without using EDT, which may explain
why the run time with EDT is even shorter than without
EDT for Ckt1, when fault triggering probability is set to
50% and using similar number of failure cycles. When
using the same number of patterns, diagnosis of EDT
designs always runs faster. Figure 4: Avg. # Diag Suspects vs. # Patterns

4.2 Diagnosis Resolution Vs. Number of Simulated

From Table 6, it shows that for Ckt1, after applying 80
Patterns scan patterns, the diagnosis resolution is almost saturated.
Applying 80 scan patterns with 64X EDT for Ckt1 can
As we know, one of the factors limiting the resolution of improve the chain diagnosis resolution about 10 times
the chain diagnostics is the amount of failing patterns / with only 25% of the number of collected failure cycles
cycles that can be logged in reasonable time. In the compared to applying 5 patterns on Ckt1 without EDT.
experiments described in the previous subsections, for For Ckt2, after applying 64 scan patterns, the diagnosis
Ckt2, if we set the datalog limit to 150K failure cycles, resolution is almost saturated. Applying 64 scan patterns
with 32X EDT for Ckt2 can improve the chain diagnosis

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resolution about 13 times with only 25% of the number of From Figure 5, it shows that for Ckt1, Factor A has more
collected failure cycles compared to applying 8 patterns contribution for the enhanced diagnosis resolution than
on Ckt2 without EDT. The chain diagnosis run times for Factor B, whereas for Ckt2, Factor B has much larger
EDT designs are now close to the ones without EDT. contribution for the enhanced diagnosis resolution.
Note that: This observation is probably due to the fact that Ckt1 has
very short chains (only a few scan cells per chain) after
(1) The experiments in Sections 4.1 and 4.2 use stuck-at-1
incorporating EDT. Therefore Factor A leads to larger
fault model as examples. Similar results are expected for
contribution to the enhanced diagnosis resolution. In
other types of fault such as stuck-at-0 and timing-related
contrast, Ckt2 still has long chains (>1K cells) even after
scan chain fault.
incorporating EDT, which probably makes the Factor A
(2) All experiments in Section 4 use EDT. The proposed has smaller contribution to the enhanced diagnosis
chain diagnosis methodology and experiments can also be resolution. In general, for large industrial designs, we
applied to any other type of embedded compression would expect Factor B plays a more important role to
techniques. enhance chain diagnosis resolution.
(3) We have illustrated with sampled test cases that chain
diagnosis with EDT can achieve better diagnosis 5. Multiple Faulty Chain Diagnosis
resolution. This would probably be also true for any type
of compression techniques other than EDT. This is due
In the previous sections, we illustrated the single faulty
to:
chain diagnosis in the context of embedded compression
Factor A: with embedded compressions, the internal scan techniques. A methodology with three steps was described
chains become much shorter. A defect on a shorter chain in Sections 3. For multiple faulty chain diagnosis, we need
will have smaller impact on the scan patterns applied, distinguish two scenarios.
which makes chain diagnosis easier.
The first scenario is that there is only one faulty chain per
Factor B: for NX compaction configuration, the channel output. Although there are multiple defective
compacted test responses from the channel output contain scan chains, the faulty chains are distributed at different
the information from N times of failed scan patterns scan channels such that their faulty responses are
without increasing the number of collected failure cycles, compacted independently at different channels. Therefore
compared to non-compaction version. we can perform diagnosis one faulty chain at a time. The
previous published multiple faulty chain diagnosis
To further analyze which factor has larger impact on [GUO01] [HUA03] can be adopted in the context of
diagnosis results, let’s look at Figure 5. compression techniques for this scenario.
The second scenario is that there are multiple faulty
chains per channel output. In this case, Steps (1) and (2)
of the proposed methodology are still the same as before.
As mentioned earlier, Step (2) requires masking patterns
in the chain pattern set such that each internal chain is
observed uniquely from one channel output with one
masking chain test pattern. Therefore, even it has multiple
faulty chains per channel, it is straightforward to identify
the faulty chains and the corresponding fault types by
applying the masking chain patterns.
After we know the faulty chains and fault type for each
faulty chain, the Step (3) of the proposed diagnosis
algorithm can be implemented by two approaches:
Figure 5: Break Down of Contributions of (1) If masking scan patterns are applied and each failed
Different Factors scan chain is uniquely observed by at least one failed
masking scan pattern (Ref. Figure 3), the diagnosis
The contribution ratios of Factor A are calculated from algorithm can be applied by using these masking scan
Columns 3 and 5 in Tables 4 and 5 for Ckt1 and Ckt2 patterns. In this case, for each failed masking scan pattern,
respectively. The contribution ratios of Factor B are only one defective chain is observed and diagnosed.
calculated from Columns 3 and 5 in Tables 4 and 5 for Hence the multiple faulty chain diagnosis can be
Ckt1 and Ckt2 respectively. We only consider permanent accomplished one chain at a time.
stuck-at-1 fault (row 4 in Tables 4 and 5) for this
comparison.

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(2) Alternatively, if there are no appropriate masking scan Design and Test of Computers, Vol. 19, Issue
patterns available, it is required to consider injecting faults 5, pp. 65-73, Sep.-Oct. 2002.
on multiple faulty chains simultaneously to compute the [CHE04] W.-T. Cheng, K.-H. Tsai, Y. Huang, N.
compacted test responses. The simulation and suspect Tamarapalli and J. Rajski, “Compactor
searching procedure is no different than diagnosing single Independent Direct Diagnosis,” Proc. Asian
chain except that the search space is expanded from one Test Symp. 2004, pp. 204-209.
dimension for single chain to M dimensions, where M is [EDI95] S. Edirisooriya and G. Edirisooriya,
the number of faulty chains per channel. The simulation “Diagnosis of Scan Failures,” Proc. VLSI Test
time could be exponentially increased with the increase of Symposium 1995, pp. 250-255.
M. In our future work, we need investigate new [GUO01] R. Guo and S. Venkataraman, “A Technique
technology and algorithm in this step in order to contain for Fault Diagnosis of Defects in Scan
the cost of searching by reducing the run time for Chains,” Proc. Int’l Test Conference, 2001, pp.
simulation. 268-277.
[HUA03] Y. Huang, W.-T. Cheng, S.M. Reddy, C.-J.
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