Digital Circuits

DIGITAL CIRCUITS
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DIGITAL CIRCUITS
SYLLABUS
ELECTRONICS & COMMUNICATION ENGINEERING
Boolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL,
TTL, ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, code converters,
multiplexers, decoders, PROMs and PLAs. Sequential circuits: latches and flip-flops,
counters and shift-registers. Sample and hold circuits, ADCs, DACs. Semiconductor
memories. Microprocessor(8085): architecture, programming, memory & I/O interfacing.
ELECTRICAL ENGINEERING
Combinational and sequential logic circuits; multiplexer; A/D and D/A converters; 8-bit
microprocessor basics, architecture, programming and interfacing.
INSTRUMENTATION ENGINEERING
Combinational logic circuits, minimization of Boolean functions. IC families, TTL, MOS

and CMOS. Arithmetic circuits. Comparators, Schmitt trigger, timers and mono-stable
multi-vibrator. Sequential circuits, flip-flops, counters, shift registers. Multiplexer, S/H
circuit .Analog-to-Digital and Digital-to-Analog converters. Basics of number system.
Microprocessor applications, memory & input-output interfacing, Microcontrollers.
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ANALYSIS OF GATE PAPERS
ELECTRONICS ELECTRICAL INSTRUMENTATION

1 Mark 2 Mark 1 Mark 2 Mark 1 Mark 2 Mark
Exam Year Ques. Ques. Total Ques. Ques. Total Ques. Ques. Total
2003 5 7 19 2 5 12 5 9 23
2004 6 7 20 2 4 10 4 7 18
2005 2 5 12 2 4 10 3 7 17
2006 - 6 12 - 5 10 1 9 19
2007 2 7 16 1 1 3 1 11 23
2008 - 8 16 - 3 6 2 8 18
2009 1 6 13 2 1 4 4 4 12
2010 2 2 6 - 4 8 2 3 8
2011 3 2 7 1 2 5 4 4 12
2012 4 1 6 2 1 4 3 1 5
2013 1 2 5 1 2 5 1 2 5
2014 Set-1 2 3 8 1 2 5 1 4 9
2014 Set-2 3 2 7 1 3 7 - - -
2014 Set-3 2 3 8 2 3 8 - - -
2014 Set-4 2 2 6 - - - - - -
2015 Set-1 2 3 8 1 3 7 3 2 7
2015 Set-2 2 3 8 1 2 5 - - -
2015 Set-3 2 3 8 - - - - - -
2016 Set-1 1 2 5 2 2 6 2 4 10
2016 Set-2 3 2 7 1 1 3 - - -
2016 Set-3 2 3 8 - - - - - -
2017 Set-1 3 4 11 1 2 5 2 2 6
2017 Set-2 3 4 11 1 1 3 - - -
2018 3 4 11 1 3 7 3 3 9
CONTENTS
Topics Page No
1. NUMBER SYSTEMS
1.1 Introduction 1
1.2 Binary Number System 1
1.3 Octal Number System 3
1.4 Hexadecimal Number System 5
1.5 Binary Codes 6
1.6 Complements 8
Gate Questions 11
2. BOOLEAN ALGEBRA
2.1 Introduction 15
2.2 SOP & POS expressions 17
2.3 Karnaugh Map 18
Gate Questions 21
3. LOGIC GATES
3.1 Introduction 36
3.2 Basic Gates 36
3.3 Universal Gates 37
3.4 Special Purpose Gates 38
3.5 Implement of SOP & POS 39
Gate Questions 41
4. LOGIC FAMILIES
4.1 Introduction 56
4.2 Characteristics of Digital ICs 56
4.3 Transistor-Transistor Logic 58
4.4 Emitter-Coupled Logic 60
4.5 MOS Logic 61
4.6 CMOS Logic 62
Gate Questions 64
5. COMBINATIONAL CIRCUITS
5.1 Introduction 75
5.2 Adders 75
5.3 Subtractors 77
5.4 Multiplexer 78
5.5 Demultiplexer 79
5.6 Decoder 79
5.7 Encoder 81
Gate Questions 82
6. SEQUENTIAL CIRCUITS
6.1 Introduction 98
6.2 Flip-Flops 98
6.3 Registers 102
6.4 Counters 104
Gate Questions 107
7. CONVERTERS
7.1 Introduction 134
7.2 Digital to Analog Converter 134
7.3 Binary-Weighted Resistors DAC 135
7.4 R-2R Ladder DAC 135
7.5 Analog to digital converters 135
7.6 Counter types ADC 136
7.7 Successive Approximation ADC 136
7.8 Dual Slope ADC 137
7.9 Flash ADC 138
Gate Questions 139
8. SEMICONDUCTOR MEMORIES

8.2 RAM 150
8.3 ROM 150
8.4 Programmable Logic Devices 151
Gate Questions 153
9. MICROPROCESSOR

9.2 Pin Diagram 158
9.3 Internal Architecture of 8085 159
9.4 Addressing Modes 161
9.5 Instruction Set 163
Gate Questions 173
10. ASSIGENMENT QUESTIONS (DIGITAL) 198
11. ASSIGENMENT QUESTIONS (MICROPROCESSOR) 218
1 NUMBER SYSTEMS
1.1 INTRODUCTION the number. In other words, we have the

following.
Whenever we use numbers in an everyday =
Symbol value Face value × Place value
way we use certain conventions. For e.g The symbol value of 2 in (26)10 is
example we all understand that the number
2 ×10 =20
1234 is a combination of symbols which
means one thousand, two hundreds, three
1.2 BINARY NUMBER SYSTEM
tens and four units. We also accept that the
symbols are chosen from a set of ten
The binary number system is a numbering
symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. This is
system that represents numeric values
the decimal number system; it is part of the
using two unique digits (0 and 1). This is
language of dealing with quantity.
also known as the base-2 number system. A
A number has a base or radix. These terms
number in binary form can be written as
both mean: how symbols or digits are used
(1011) 2 . In this representation, the first
to express a number. A base 10 number has
ten symbols; the base 10 number system is digit ‘1’ is called most significant bit (MSB)
the decimal number system. Sometimes the & the last bit ‘1’ is called least significant bit
base of a number is shown as a subscript: (LSB).
(1234 )10 . Here the 10 is a subscript which 1.2.1 DECIMAL TO BINARY CONVERSION
indicates that the number is a base 10
1) For numbers greater than 1
number.
• Write the decimal number as the
dividend. Write the base of the
Note:
destination system (in our case, "2" for
• In a number system, the digit (number)
binary) as the divisor on the left side.
used cannot be equal to or greater than
• Write the integer answer (quotient)
its base number. E.g. In base 10, the
under the dividend, and write the
largest number that is used is 10-1=9.
remainder (0 or 1) to the right of the
• When we count in Base Ten, we count
quotient.
starting with zero and going up to nine
• Continue downwards, dividing each
in order 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 …Once
new quotient by two and writing the
we reach the last symbol, we create a
remainders to the right of each
new placement in front of the first and
dividend. Stop when the quotient is 0.
count that up. 8, 9, 10, 11, 12…19, 20…
• Starting with the bottom remainder,
This continues when we run out of
read the sequence of remainders
symbols for that placement. So, after 99,
upwards to the top.
we go to 100.
1.1.1 POSITIONAL NUMBER SYSTEM Example: Convert (156 )10 to binary (base-2).
Positional numbering system uses a set of

symbols. The value that each symbol
represents, however, depends on its face
value and its place value, the value
associated with the position it occupies in
Base Quotient Remainder • Define a variable n whose value whose
2 156 value 0, 1, 2, 3… on the left side of
2 78 0
decimal point &−1, −2, −3, −4… on the
2 39 0
2 19 1 right side of decimal point.
2 9 1 • Multiply each binary digit with 2n by
2 4 1 taking corresponding value of n & add
2 2 0 all the multiplications.
2 1 0
2 0 1 Example: Convert (10011100.001) 2 to its
2
decimal equivalent.
Solution:
Writing the remainders from bottom to top
10011100.001
10011100 we get
n = 7 6 5 4 3 2 1 0 -1 -2 -3
(156)10 = (10011100 )2
Now,
(10011100.001)2 = 1× 27 + 0 × 26 + 0 × 25 + 1× 24 + 1× 23
Note: This method can be modified to +1× 22 + 0 × 21 + 0 × 20 + 0 × 2−1 + 0 × 2−2 + 1× 2−3 =(156.125)10
convert from decimal to any base. The
divisor is 2 because the desired destination
1.2.3 BINARY ADDITION
is base 2 (binary). If the desired destination
is a different base, replace the 2 in the Rules for Binary Addition:.
method with the desired base. For example, 1) 0+0=0
if the desired destination is base 9, replace 2) 0+1=1
the 2 with 9. The final result will then be in 3) 1+0=1
the desired base. 4) 1+1=10 (=decimal 2) first ‘1’ will go as a
carry
2) For the numbers less than 1 5) 1+1+1=11 (=decimal 3) first ‘1’ will go
• Multiply the decimal number by 2. The as a carry
integer part of the result is kept aside as
a carry.
Example: Add (1101) 2 + ( 0101)2
• Again multiply the fraction part of the
result until we get only integer part in Solution:
the result (no fraction part). 1 1
1101
Example: Convert ( 0.75 )10 into its binary + 0101
equivalent. 10010
∴ (1101) 2 + ( 0101)2 =
(10010) 2
Multiplication Carry
0.125 × 2 = 0.25 0
1.2.4 BINARY SUBTRACTION
0.25 × 2 = 0.5 0
0.5 × 2 = 1.0 1
Rules for Binary Subtraction:
1) 0-0=0
Writing carry from top to bottom, we get 2) 0-1=1 (It is not possible to subtract 1
(0.75)10 = (.001) 2 . from 0 hence we take a borrow equal to
the base of number system (for binary it
1.2.2 BINARY TO DECIMAL CONVERSION is 2)).
3) 1-0=1
• 4) 1-0=0
Example: Subtract (1100) 2 − (0011) 2 . 4) 1Megabyte(MB)=1024kilobytes=
22 1,048,576 bytes
//
1100 5) 1 Gigabyte (GB) =1024 megabytes=
− 0011 1,073,741,824 bytes
11 1.3 OCTAL NUMBER SYSTEM
1001
∴ (1100) 2 − (0011) 2 =
(1001) 2 Octal is another number system with fewer
symbols to use than our conventional
number system. Octal is fancy for Base
1.2.5 BINARY MULTIPLICATION
Eight meaning eight symbols are used to
Rules for Binary Multiplication:
represent all the quantities. They are 0, 1, 2,
3, 4, 5, 6, and 7.
1) 0×0=0
When we count up one from the 7, we need
2) 0×1=0
a new placement to represent what we call
3) 1×0=0
8 since an 8 doesn't exist in Octal. So, after
4) 1×1=1
7 is 10. A number can be represented in
Octal as (526)8 .
Example: Multiply (1100) 2 × (101) 2 .
Solution:
1100 1.3.1 DECIMAL TO OCTAL CONVERSION
×101
1100 The procedure to convert decimal to octal
+ 00000 is exactly same as to convert decimal to
+ 110000 binary.
111100
∴ (1100) 2 × (101) 2 =
(111100) 2 Example: Convert (63.625)8 into decimal.
Base Quotient Remainder
1.2.6 BINARY DIVISION 8 63
8 7 7
Binary division is the repeated process of 0 7
subtraction, just as in decimal division. Writing the remainder from bottom to top,
the octal conversion of (63)10 is (77)8 .
Example: Perform (1100) 2 ÷ (100) 2 .
100 )1100 (1 Multiplication Carry
− 100 0.625 × 8 = 5.0 5
0100 (1 ∴ (63.625)10 =
(77.5)8
− 100
0000 1.3.2 OCTAL TO DECIMAL CONVERSION
∴ (1100) 2 ÷ (100) 2 =
(11) 2
The procedure to convert octal to decimal
1.2.7 BINARY EQUIVALENTS is exactly same as to convert binary to
decimal.
1) 1 Nybble (or nibble)=4 bits
2) 1 Byte=2 nybbles =8 bits Example: Convert (77.5)8 to decimal.
3) 1 Kilobyte (KB)=1024 bytes 77.5
N = 10-1
Now, 5
(77.5)8 = 7 × 81 + 7 × 80 + 5 × 8−1 +6
11
= (63.625)10
As we cannot represent a number
greater than 8, 11 is not a valid octal
1.3.3 OCTAL TO BINARY CONVERSION number.
11 = 1(carry) × 8(base) + 3
An octal number can be converted into
Hence 1 will go to carry & the addition
binary by representing each octal digit into
its bit binary equivalent. will be 13i.e. (5)8 + (6)8 =(13)8
iii)
Example: Convert ( 24.53)8 into binary. 23
Solution: + 11
2 4 . 5 3 34
[ ↓ ↓ ] ∴ (23)8 + (11)8 = (34)8
010 100 101 011
∴ (24.53)8 =(010100.101011) 2 iv)
Note: A binary number can be converted 23
into octal by grouping 3 binary bits & + 64
converting each group into its octal 107
equivalent. Here, 6 + 2 = 8 is not a valid octal number.
8 = 1× 8 + 0 hence 1 will go to carry.
Example: Convert (10001.0101) 2 into octal.
010 001 . 010 100 1.3.5 OCTAL SUBTRACTION
] ↓ ↓ [
2 1 . 2 4 The subtraction in octal follow the same
∴ (10001.0101) 2 =
(21.24)8 rules as in case of decimal. The only
difference is that when we are subtracting
a larger number from a smaller one, we
1.3.4 OCTAL ADDITION
have to take 8 as borrow instead of 10 as in
The addition of octal numbers is not case of decimal number system.
difficult provided you remember that Example: Perform (46)8 − (7)8 .
anytime the sum of two digits exceeds 7, a Solution:
carry is produced. 8+6 = 14
Example: Perform 3 14
i) (5)8 + (1)8 4 6
ii) (5)8 + (6)8 − 7
3 7
iii) (23)8 + (11)8
In the octal example (7)8 cannot be
iv) (23)8 + (64)8
subtracted from (6)8 , so you must borrow
Solution:
i) from the 4. Reduce the 4 by 1 and add base
5 (i.e.8) to the (6)8 . By subtracting (7)8
+1 from 14 you get a difference of (7)8 . Write
6 this number in the difference line and bring
∴ (5)8 + (1)8 =
(6)8 down the 3.
ii) ∴ (46)8 − (7)8 =(37)8
Like binary to decimal conversion here also
1.4 HEXADECIMAL NUMBER SYSTEM define a variable n & conversion can be
done by following same procedure.
The hexadecimal system is Base Sixteen. As
its base implies, this number system uses Example: Convert (A6)16 to decimal.
sixteen symbols to represent numbers. Solution:
Unlike binary and octal, hexadecimal has A6
six additional symbols that it uses beyond n=10
the conventional ones found in decimal. But Now,
what comes after 9? 10 is not a single digit (A6)16 = 10 ×161 + 6 ×160 = (166)10
but two… Fortunately, the convention is
that once additional symbols are needed 1.4.3 HEXADECIMAL TO BINARY
beyond the normal ten, letters are to be CONVERSION
used. So, in hexadecimal, the total list of
symbols to use is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, A number in base 16 can be converted into
B, C, D, E, and F. base 2 by representing each hexadecimal
bit into its 4 bit binary equivalent.
1.4.1 DECIMAL TO HEXADECIMAL
CONVERSION
Example: Convert ( 2FD.B61)16 into binary.
The procedure to convert decimal to Solution:
hexadecimal is exactly same as to convert
decimal to binary only we have replace
base 2 with 16. ∴ (2FD.B61)16 =
(001011111101101101100001) 2
Example: Convert ( 55.03125)10 to its

hexadecimal equivalent.
1.4.4 HEXADECIMAL ADDITION
Solution:
Base Quotient Remainder While adding two hexadecimal numbers if
16 55 the result exceeds 15, a carry is generated.
16 3 7 Example: Perform
0 3 i) (5)16 + (1)16
Writing remainders from bottom to top we ii) (5)16 + (6)16
get,
(55)10 = (37)16 iii) (A)16 + (F)16
Now, iv) (CC)16 + (58)16
Multiplication carry Solution:
0.03125×16=0.5 0 i) ii)
0.5×16=8 8 5 5
Writing carry from top to bottom we get, +1 +6
(0.03125)10 = (0.08)16 6 B
∴ (55.03125)10 = (37.08)16 iii)
A
1.4.2 HEXADECIMAL TO DECIMAL +F
CONVERSION 19
Here A(10) + F(15) =25 this is not a valid
hexadecimal number.
As 25 =1(carry) ×16(base) + 9 • All arithmetic operations on all other
∴ (A)16 + (F)16 =
(19)16 base systems like base-5, base-7 and
iv) base-9 will be carried out by following
1 the same proceed
CC 1.4.6 CONVERSION TABLE
+1 58
Decimal Hexadecimal Base4 Octal Binary
124 0 0 0 0 0
C + 8 = 20 = 1(carry) ×16(base) + 4 1 1 1 1 1
C + 5 + 1 = 18 = 1(carry) ×16(base) + 2 2 2 2 2 10
3 3 3 3 11
4 4 10 4 100
5 5 11 5 101
1.4.5 HEXADECIMAL SUBTRACTION 6 6 12 6 110
7 7 13 7 111
The subtraction in hexadecimal follows the 8 8 20 10 1000
same rules as in case of decimal. The only 9 9 21 11 1001
10 A 22 12 1010
difference is that when we are subtracting
11 B 23 13 1011
a larger number from a smaller one, we 12 C 30 14 1100
have to take 16 as borrow instead of 10 as 13 D 31 15 1101
in case of decimal number system. 14 E 32 16 1110
15 F 33 17 1111
Example: Perform (46)16 − (D)16 . 16 10 100 20 10000
17 11 101 21 10001
Solution: 18 12 102 22 10010
16 + 6 =22 19 13 103 23 10011
3 22 20 14 110 24 10100
4 6
− D 1.5 BINARY CODES
3 9 In the coding, when numbers, letters or
In the octal example (D)16 cannot be words are represented by a specific group
subtracted from (6)16 , so we must borrow of symbols, it is said that the number, letter
or word is being encoded. The group of
from the 4. Reduce the 4 by 1 and add base
symbols is called as a code. The digital data
(i.e. 16) to the (6)16 . By subtracting (D)16 is represented, stored and transmitted as
from 22 we get a difference of (9)16 . Write group of binary bits. This group is also
this number in the difference line and bring called as binary code. The binary code is
down the 3. represented by the number as well as
∴ (46)16 − (D)16 = (39)16 alphanumeric letter.
1.5.1 CLASSIFICATION OF BINARY CODES
Note:
• Multiplication & Division in Octal & The codes are broadly categorized into
Hexadecimal is exactly same as in case following three categories.
of decimal. The only thing which is to
keep in mind that the result should not 1) Weighted Codes:
contain any invalid octal or hexadecimal. Weighted binary codes are those binary
• To convert a base-4 number into binary codes which obey the positional weight
simply represent each digit with its 2 principle. Each position of the number
bit binary equivalent. represents a specific weight. Several
systems of the codes are used to
express the decimal digits 0 through 9. 2 5 7
In these codes each decimal dig it is [ ↓ ]
represented by a group of four bits. 0010 0101 0111
(257)10 = (001001010111) BCD
Example: Perform 66+99 using BCD

addition.
Solution:
66 = 0110 0110
+99 = + 0110 1001
1111 1111
1111 is an invalid BCD code. To convert it
into
a) Binary Coded Decimal Code: 1111 11
In this code each decimal digit is 1111 1111
represented by a 4-bit binary number. + 0110 0110
BCD is a way to express each of the 1 0110 0101
decimal digits with a binary code. In the ] ↓ [
BCD, with four bits we can represent 165
sixteen numbers (0000 to 1111). But Valid BCD code add 0110
in BCD code only first ten of these are ∴ 66 + 99 = 165
used (0000 to 1001). The remaining six
code combinations i.e. 1010 to 1111 are 2) Non-Weighted Codes:
invalid in BCD. In this type of binary codes, the positional
weights are not assigned. The examples of
Decimal BCD non-weighted codes are Excess-3 code &
0 0000 Gray code.
1 0001
VALID a) Excess-3 Code:
2 0010
BCD The Excess-3 code is also called as XS-3
3 0011
CODES code. It is non-weighted code used to
4 0100
5 0101 express decimal numbers. The Excess-3
6 0110 code words are derived from the 8421
7 0111 BCD code words adding (0011) 2 or (3)10
8 1000 to each code word in 8421. The excess-
9 1001 3 codes are obtained as follows.
10 1010
11 1011 INVALID Decimal BCD Excess-3
BCD (BCD+0011)
12 1100
CODES 0 0 11
13 1101
1 1 100
14 1110
2 10 101
15 1111 3 11 110
4 100 111
Example: Convert (257)10 into its BCD 5 101 1000
6 110 1001
equivalent.
7 111 1010
Solution:
8 1000 1011
A decimal number can be converted into 9 1001 1100
BCD by representing each decimal digit
into its BCD equivalent.
Excess-3 code is also known as self- Number Decim Hexad
complimenting code or reflective System Binary Octal al ecimal
code, as compliment of any number Base (r) r=2 r=8 r=10 r=16
(r-1)’s
between 0 & 9 is available within these complement 1’s 7’s 9’s 15’s
r's
10 numbers. For example complement complement 2’s 8’s 10’s 16’s
of 9 (1100) is 0011.
b) Gray Code: It has a very special feature Note:
that has only one bit will change, each • (r-1)’s complement of any number in
time the decimal number is any number system can be calculated
incremented as shown in the table. As by subtracting each digit in the number
only one bit changes at a time, the gray from the largest number in the number
code is called as a unit distance code. system.
The gray code is a cyclic code. • r's complement is then calculated by
adding to the (r-1)’s complement of the
Decimal Binary Gray Code number.
0 0 0
1 1 1 Example:
2 10 11 Calculate 9’s & 10’s complement of (56)10 .
3 11 10
4 100 110 Solution: The largest number in base 10 is
5 101 111 99
6 110 101 −5 6
7 111 100 9 4 3 − 9 's complement
8 1000 1100 + 1
9 1001 1101
4 4 − 10 's complement
10 1010 1111
11 1011 1110
12 1100 1010 Example: Calculate 1’s & 2’s complement
13 1101 1011 of (1001101) 2 .
14 1110 1001
15 1111 1000 Solution: The largest number in base 2 is 1
11 111 11
−1 0 0 1 1 0 1
Note: Gray code cannot be used for
arithmetic operation. 0 1 1 0 0 1 0 1's complement
+ 1
1.6 COMPLEMENTS 0 1 1 0 0 1 1 2 's complement
Complements are used to simplify the 1.6.1 NUMBER REPRESENTATION

subtraction operation for logical
manipulation. Consider ‘r’ is the base of a 1) Signed Magnitude:
number, then there exist 2 types of
complement. It is also called "sign-magnitude" or "sign
and magnitude" representation. In the first
1) r's complement approach, the problem of representing a
2) (r-1)’s complement number's sign can be to allocate one sign
E.g. for binary number system there are bit to represent the sign: set that bit (often
two complements 2’s(r's) & 1’s((r-1)’s) the most significant bit) to 0 for a positive
complement. number, and set to 1 for a negative number.
The remaining bits in the number indicate
the magnitude (or absolute value).
Hence in 4 bits with only 3 bits (apart from +(8)10 =
’0’1000
the sign bit), the magnitude can range from Now to represent −(8)10 take 1’s
000 (0) to 111 (7). Thus we can represent
complement of 01000
numbers from (−7)10 to (+7)10 once we add
∴ − (8)10 = 10111
the sign bit (the 4th bit).
Note:
Note: • Using 4 bits (including sign bit) we can
• With n bits we can represent from Represent numbers from −(7)10 to + (7)10
− ( 2n −1 − 1) to + ( 2n −1 − 1) . • Hence using n bits we can represent
numbers from − ( 2n −1 − 1) to + ( 2n −1 − 1) .
• A consequence of this representation is
that there are two ways to represent • A consequence of this representation is
zero, ‘0’000 (0) and ‘1’000 (−0). that there are two ways to represent
zero, ‘0’000 (0) and ‘1’111 (−0).
Example: Represent −(43)10 in an eight-
bit signed magnitude.
Solution: 3) 2’s Complement:
+(43)10 = 101011
Its seven bit representation will be Positive numbers are represented as they
0101011 are (simple binary) with ‘0’ before it. To get
Now using signed magnitude representation, a negative number, write the positive
−(43)10 = ‘1’0101011. number in binary with 0 before it & find its
2’s complement.
2) 1’s Complement: Example: Represent i) +(7)10 & −(7)10
Positive numbers are represented as they ii) −(8)10 in 2’s complement form.
are (simple binary) with ‘0’ before it. To get Solution:
a negative number, write the positive i) (7)10 = 111
number in binary & find its 1’s +(7)10 = '0'111
complement.
Now to represent −(7)10 take 2’s
complement of '0'111
Example Represent i) +(7)10 & − (7)10
∴ − (7)10 = 1001
ii) −(8)10 in 1’s complement form.
Note: If we are to represent +(7)10 & −(7)10
Solution:
in 6 bits then simply add 2 ‘0’ for +ve
i) (7)10 = 111
number & 2 ‘1’ for –ve number.
+(7)10 = '0'111 +(7)10 = 000111
Now to represent −(7)10 take 1’s −(7)10 =
111001
complement of '0'111
∴ − (7)10 = 1000 ii) +(8)10 =
’0’1000
Now to represent −(8)10 take 2’s
Note: If we are to represent +(7)10 & −(7)10
complement of 01000
in 6 bits then simply add 2 ‘0’ for +ve ∴ − (8)10 =11000
number & 2 ‘1’ for –ve number.
Note:
+(7)10 =000111
• −(8)10 can also be represented in 4 bit
−(7)10 =
111000
2’s complement for by removing 1st ‘1’
ii)
as in the starting repeated 1s have no • Always discard the carry generated
significance. after subtraction.
• Using 4 bits (including sign bit) we can • The result of subtraction is always in 2’s
represent numbers from −(8)10 to + (7)10 . complement form. +7 − 2 =+5 & +5 is
• Hence using n bits we can represent represented in 2’s complement form as
numbers from − ( 2n −1 ) to + ( 2n −1 − 1) 0101.
Signed 1’s 2’s Example: Add –5 + (–4)
Decimal magnitude complement complement
0 0 0 0 Solution:
1 1 1 111 +5 = 00101
2 10 10 10 –5 =11011
3 11 11 11 +4 = 00100
4 100 100 100 –4 =11100
5 101 101 101
6 110 110 110
Now,
7 111 111 111 −5 11011
8 N/A N/A N/A −4 + 11100
−0 1000 1111 0 −9 1 10111
−1 1001 1110 1111
−2 1010 1101 1110
−3 1011 1100 1101
110111=10111 when we discard the
−4 1100 1011 1100 carry.10111 is negative, as indicated by the
−5 1101 1010 1011 leading 1. Flip the bits to get 01000. Add 1
−6 1110 1001 1010 to get 01001. The result is 9. Since it is
−7 1111 1000 1001 negative, we really have –9.
−8 N/A N/A 1000
1.6.2 SUBTRACTION USING 2’s

COMPLEMENTS
Earlier we have discussed binary

subtraction but if a greater number is
subtracted from a smaller one the
subtraction can be performed using 2’s
complement method.
Example: Add +7 and –2 using 2’s

complement.
Solution:
+7 = 0111
+2 = 0010
–2 = 1110
Now,
7 0111
−2 + 1110
5 1 0101
Discard the extra carry to give 0101 = 5
Note:
GATE QUESTIONS(EC)
Q.1 The 2’s complement representation 010100. In this numbering system,

of -17 is the BCP code 100010011001
a)101110 b)101111 corresponds to the following
c) 111110 d) 110001 number in base -5 system
[GATE -2001] a) 423 b) 1324
c) 2201 d) 4231
Q.2 4-bit 2’s complement representation [GATE -2006]
of a decimal number is 1000. The
number is Q.7 X=01110 and Y =11001 are two 5 –
a) +8 b) 0 bit binary numbers represented in
c) -7 d) -8 two’s complement format .The sum
[GATE -2002] of X and Y represented in two’s
complement format using 6 bits is
Q.3 The range of signed decimal a) 100111 b) 001000
numbers that can be represented by c) 000111 d) 101001
6-bit 1’s complement number is [GATE -2007]
a) −31to + 31 b) −63to + 63
c) −64to + 63 d) −32to + 31 Q.8 The two numbers represented in
[GATE -2004] signed 2’s complement form are
P=11101101 and Q=11100110. If Q
Q.4 11001, 1001 and 111001 is subtracted from P, the value
correspond to the 2’s complement obtained in signed 2’s complement
representation of which one of the form is
following sets of number? a)100000111 b)00000111
a) 25, 9 and 57 respectively c) 11111001 d) 111111001
b) -6,-6 and -6 respectively [GATE -2008]
c) -7,-7 and -7 respectively
d) -25,-9 and -57 respectively Q.9 The number of bytes required to
[GATE -2004] represent the decimal number
1856357 in packed BCD (Binary
Q.5 Decimal 43 in Hexadecimal and BCD Coded Decimal) form is ________.
number system is respectively [GATE-2014]
a)B2,0100 0011 b)2B,0100 0011
c)2B,0011 0100 d)B2,0100 0100
[GATE -2005]
Q.6 A new Binary coded Pentary (BCP)

number system is proposed in
which every digit of a base -5
number is represented by its
corresponding 3-bit binary code.
For example, the base -5 number 24
will be represented by its BCP code
ANSWER KEY:
1 2 3 4 5 6 7 8 9
(b) (d) (a) (c) (b) (d) (c) (b) 4
EXPLANATIONS
Q.1 (b) Carry is discarded in the addition of

17 = 010001 numbers represented in 2’s
-17 = 101111 (2s’complement) complement form. X+Y in 6 bits is
000111.
Q.2 (d)
1000 Q.8 (b)
MSB is 1 so, -ve number Take Q Signed 2’s complement of
2’scomplement for magnitude 0111 P = 11101101
1= 8 ∴ No. P = 00010011
1000 = −8 Q Signed 2’s complement of
Q = 11100110
Q.3 (a) P − Q = P + (2’s complement of Q)
− ( 2n −1 − 1) to + ( 2n −1 − 1)
Range = =00010011
11100110
− ( 26−1 − 1) to + ( 26−1 − 1)
= 11111001
=
−31 to + 31 2’s complement of
(P − Q) = 00000111
Q.4 (c)
11001 → 00111( +7 ) Q.9 (4)
In packed BCD (Binary Coded
1001 → 0111( +7 ) Decimal) typically encoded two
111001 → 000111( +7 ) decimal digits within a single byte
∴ Numbers given in question in 2’s by taking advantage of the fact that
complement correspond to -7 four bits are enough to represent
the range 0 to 9. So, 1856357 is
Q.5 (b) required 4-bytes to stored these
BCD digits.
∴ (43)d = ( 2B )H = ( 01000011)BCD
Q.6 (d)
100010011001 → 4231
Q.7 (c)
X = 01110
Y = 11001
X+Y = 00111
GATE QUESTIONS(IN)
Q.1 A number N is stored in a 4-bit2’s a) 8 b) 7
complement representation as c) 6 d) 5
a3 a2 a1 a0 [GATE-2011]
It is copied into a 6-bit register and
a few operations, the final bit Q.4 The result of ( 45)10 − ( 45)16
pattern is expressed in 6-bit 2’s complement
a3 a3 a2 a1 a0 1 representation is,
The value of this bit pattern in 2’s a) 011000 b) 100111
complement representation is given c) 101000 d) 101001
in terms of the original number is N as [GATE-2011]
a) 32a 3 +2N+1 b) 32a 3 -2N-1
c) 2N-1 d) 2N+1 Q.5 The representation of the decimal
[GATE-2006] number (27.625) in base-2 number
system is
Q.2 The binary representation of the a) 11011.110
decimal number 1.375 is, b) 11101.101
a) 1.111 b) 1.010 c) 11011.101
c) 1.011 d) 1.001 d) 10111.110
[GATE-2009] [GATE-2018]
Q.3 The base of the number system for

the addition operation 24+14=41 to
be true is
ANSWER KEY:
1 2 3 4 5
(d) (c) (b) (c) (c)
EXPLANATIONS
Q.1 (d) Q.5 (c)

It is equal to 2N+1
(27.625)10 = (?)2
Q.2 (c) → Integer part

0.375 ×2 = 0.750
0.750 ×2 = 1.5 2 27
0.5 ×2 = 1.0 2 13 − 1
Hence answer is 1.011 2 6 −1
2 3−0
Q.3 (b)
1−1
⇒ (27)10 = (11011)2
4+4 gives 1 as sum and 1 as carry.
So, base is 4 + 4 – 1 = 7 → Fractional part
0.625× 2 = 1.250 ⇒1
Q.4 (c)
0.250 × 2 = 0.500 ⇒ 0
( 45)10 − ( 45)16 =
( −24 )10 =
(101000 )2 0.500 × 2 = 1.000 ⇒1
(24)10 = (011000)2
0.000 × 2 = 0.000 ⇒ 0
(-24)10 = (101000)2
⇒ (0.625)10 = (0.101)2
⇒ (27.625)10 = (11011.101)2
2 BOOLEAN ALGEBRA
2.1 INTRODUCTION A+A = A

A+A = 1
Boolean algebra is the subarea of algebra in 3. AND Theorem:
which the values of the variables are the 0.0 = 0
truth values true and false, usually denoted 0.1 = 0
1 and 0 respectively. The most obvious 1.0 = 0
way to simplify Boolean expressions is to 1.1 = 1
manipulate them in the same way as 0.A = 0
normal algebraic expressions are 1.A = A
manipulated. With regards to logic A.A = A
relations in digital forms, a set of rules for A.A = 0
symbolic manipulation is needed in order
4. Commutative Law:
to solve for the unknowns.
A+B = B+A
A set of rules formulated by the English
AB = BA
mathematician George Boole describe
5. Associative Law:
certain propositions whose outcome would (A + B) + C =A + (B + C)
be either true or false. With regard to digital
logic, these rules are used to describe circuits (AB)C = A(BC)
whose state can be either, 1 (true) or 0 6. Distributive Law:
(false). In order to fully understand this, the A(B + C) = AB + AC
relation between AND gate, OR gate and NOT A + (BC) = (A + B)(A + C)
gate operations should be appreciated. 7. Redundancy Law:
A + AB = A
OPERATOR SYMBOL A(A + B) = A
NOT ‘ or - A + AB =A +
B
AND .
OR + (
A A+B =
AB )
8. De Morgan's Theorem:
2.1.1 LAWS & THEOREMS ( A + B) =
AB
1. NOT Theorem: AB= A + B

9. Consensus Theorem:
0 =1
AB + AC + BC = AB + AC
1= 0
A=A
( A + b ) ( A + C ) ( B + C ) = ( A + B) ( A + C )
2. OR Theorem:
0+0 = 0 2.1.2 BOOLEAN FUNCTION
0 +1 =1
1+ 0=1 A Boolean (logical) function described by
1+ 1=1 an algebraic expression consists of binary
0+ A=A variables, the constants 0 and 1, and the
1+ A = 1 logic operation symbols. For a given value
of the binary variables, the function can be
equal to either 1 or 0.
As an example, consider the Boolean 1 0 1 0
function 1 1 0 0
F= x + y'z
1 1 1 1
Here F is function of 3 independent
Example: Write the logical expression for
variables x, y, z.
function Y in the given truth table.
F = 1 ; if x = 1 or both = ( y 0 ) and z = 1.
y’ 1=
B C Y
F = 0 ; Otherwise 0 0 0
A Boolean function expresses the logical 0 1 1
relationship between binary variables and 1 0 0
is evaluated by determining the expression 1 1 1
for all possible values of the variables. Solution: The function Y = 1 when B = 0 &
C = 0 or B = 1 & C = 1
2.1.3 TRUTH TABLE
∴ Y = B.C + B.C
A truth table is a means for describing how
2.1.4 PRINCIPLE OF DUALITY
a logic circuit’s output depends on the logic
levels present at the circuit’s inputs. The
The duality principle states that every
table lists all possible combinations of logic
algebraic expression deducible from the
levels present at inputs A and B, along with
theorems of Boolean algebra remains valid
the corresponding output level x. Note that
if the operators and identity elements are
there are 4 table entries for the two-input
interchanged.
truth table, 8 entries for a three-input truth
e.g. If X + Y = Y + X then by duality
table, and 16 entries for the four-input
X.Y = Y.X
truth table. The number of input
If X + 0 = X then by duality X.1 = X
combinations will equal 2n for an n-input
To find dual of any logical expression
truth table.
1. Interchange the OR and AND operations
A B X
of the expression.
0 0 1
2. Interchange the 0 and 1 elements of the
0 1 0
expression.
1 0 0 3. Do not change the form of the
1 1 0 variables.
Example: Write the truth table for logic
Example: Find the dual of =F xy + xy.
function F= x + yz .
Solution: Interchanging the OR and AND
Solution: We know that the function F =1
operations of the expression
if x = 1 or y = 1 & z = 1
F = 0 other wise (
FD =x + y x + y )( )
This information about function F can be
show in truth table as 2.1.5 COMPLEMENT OF A FUNCTION
x y z F Complement of a function can be calculated

0 0 0 0 by
0 0 1 0 1. Interchanging the OR and AND
operations of the expression.
0 1 0 0
2. Interchanging the 0 and 1 elements of
0 1 1 0 the expression.
1 0 0 0 3. Changing the form of the variables.
Example: Calculate the complement of • SOP expression for a function is the
=
F xy + xy. combination of min terms. For the
Solution: complement of above given table F in SOP form can be
written as
F=
F =+
x y x+y( )( ) F = ABC + ABC + ABC + ABC
The function F can also be written as
2.1.6 MIN & MAX TERMS F = m1 + m3 + m5 + m 7 = ∑m(1,3,5, 7)
The combinations of independent variables The numbers 1, 3, 5 & 7 represents the
for which the function has value 1 are combinations of A, B & C for which the
called min terms & the combinations for function F = 1 .
which the function has value 0 are called
max terms. Consider a function Y(A,B) • POS expression for a function is
whose truth table is as shown below combination of max terms. For the
above given table
Combin A B Y Min term Max term F’ = ABC + ABC + ABC + ABC
ation ∴F = ( A + B + C) .( A + B + C).( A + B + C).( A + B + C)
0th 0 0 0 AB(m 0 ) A + B (M 0 ) The function F can also be written as
1st 0 1 1 AB(m1 ) A + B (M1 ) F = M 0 + M 2 + M 4 + M 6 = ∏M(0, 2, 4, 6)
2nd 1 0 0 AB(m 2 ) A + B (M 2 ) The numbers 0, 2, 4 & 6 represents the
combinations of A, B & C for which the
3rd 1 1 1 AB (m 3 ) A + B (M 3 ) function F = 0.
min terms for the function are AB & AB 2.2.1 CANONICAL FORMS
(1st& 3rd combination of A & B) A canonical SOP or POS expression is the
1. max terms are =
AB ( A + B) one in which each product or sum term
contains all the independent variables.
=
AB ( A + B) (0 th & 2nd combination
of A & B) Example: Convert A + AB to canonical SOP
form.
Note:
• While writing min terms there will
Solution: A + AB= A B + B + AB ( )
always be AND operator between = AB + AB + AB
variables.
• While writing max terms there will Example: Convert A(A+B) into canonical
always be OR operator between POS form.
variables.
( ) (
Solution: A A + B = A + BB A + B )( )
2.2 SOP & POS EXPRESSIONS
(
( A + B) A + B A + B
= )( )
Example: Write the expression for function
Y in SOP & POS forms.
B C Y
0 0 0
0 1 1
1 0 0
1 1 1
Solution: Q ( x + y ) z’ + z = ( x + y ) + z
=
1. In SOP Y ∑m (1,3=) m1 + m3 =x + y(1 + x) + z
= BC + BC = x+y+z
Y ∏M ( 0, =
= 2) M0 + M2
2. In POS 2.3 KARNAUGH MAP
= ( B + C) B + C ( )
The Karnaugh map (K-MAP) provides a
simple and straight-forward method of
Example: Simplify
minimizing Boolean expressions. With the
i. xy + xy'
Karnaugh map Boolean expressions having
ii. xyz + x ' y + xyz' up to four and even six variables can be
iii. ABC+A’B+ABC’+AC simplified.
iv. (x’y’ + z)’ + z + xy + wz
Solution: 2.3.1 2-VARIABLE K-MAP
i. xy + xy ' = x ( y + y ' ) = x
A function F(A,B) with 2 variables can be
Q ( y + y' ) =
1 simplified using a two variable K-map
ii. xyz + x ' y + xyz ' = xyz + xyz + x ' y + xyz ' shown below by substituting the values of
F for different combinations of A & B in the
(Repetition of xyz term won’t make any
respective block.
difference)
= y ( xz + x ' ) + xy(z + z ' )
= y ( z + x ' ) + xy
Q ( xz + x ' ) =(z + x ' )
= y(z + x ' + x) Procedure:
= y(z + 1)
• Consider a Y(B,C) function with truth
Q ( x + x' ) =
1 table
=y B C Y
iii. ABC + A’B + ABC’ + AC = ( AC + A’) B 0 0 0
+ A(BC’ + C) 0 1 1
= (C + A’)B + A(B + C) 1 0 0
= BC + A’B + AB + AC 1 1 1
= BC + (A’ + A)B + AC Here m 0 = 0 , m1 = 1 , m 2 = 0 , m3 = 1
= BC + B + AC • Substitute the values of m 0 , m1 , m 2 , m3
= B ( C + 1) + AC in the K-map
= B + AC
iv. ( x’y’ + z ) ’ + z + xy + wz =
( x’y’) z’ + z + xy + wz • Make groups of 1,2,4,8,16 for 1’s in the
'
K-map
Q using De − Morgan 's Law
= ( x "+ y") z’ + xy + (1 + w)z
= ( x + y ) z’ + xy + z
= ( x + y ) + z + xy
• Write the expression for the groups 5. Groups may overlap.
1. For both the 1s in the group B = 1 i.e.
B is same for both 1s, hence it will
be taken into consideration while
writing the expression.
2. For upper 1, A = 0 & for lower 1,
A = 1 . As is different for both 1s, 6. Groups may wrap around the table.
hence it will not be taken into The leftmost cell in a row may be
consideration. grouped with the rightmost cell and
∴The expression for F = B the top cell in a column may be
grouped with the bottom cell.
Rules for grouping:
1. Groups may not include any cell
containing a zero
7. Four 1s at the corner of K-map can

form a group of 4.
2. Groups may be horizontal or vertical,
but not diagonal.
Example: Simplify the function

f ( A, B ) = ∑m(1, 2,3)
3. Groups must contain 1, 2, 4, 8, or in
Solution:
general 2 cells. That is if n = 1, a
n
group will contain two 1's since 2 =

1
2. If n = 2, a group will contain four

1's since22 = 4.
f ( A, B=
) A+B
2.3.2 3-VARIABLE K-MAP
A 3 variable K-map can be used for

simplification of 3 variable functions. The
4. Each group should be as large as possible sizes of groups in 3 variables K-
possible. map are 1, 2, 4 & 8.
Example:Simplify
f (A, B, C) = ∑m(0, 2, 4,5, 6) . 2.3.4 DON’T CARE CONDITION
Solution:
Don't cares in a Karnaugh map, or truth
table, may be either 1s or 0s, as long as we
don't care what the output is for an input
condition we never expect to see. We plot
these cells with a cross, ×, among the
f ( ABC
= ) AB + C normal 1s and 0s. When forming groups of
cells, treat the don't care cell as either
a 1 or a 0, or ignore the don't cares. This is
Example: Simplify
helpful if it allows us to form a larger group
f (A, B, C) = ∏M(1, 2,3,5, 7) than would otherwise be possible without
Solution: the don't cares. There is no requirement to
group all or any of the don't cares. Only use
them in a group if it simplifies the logic.
Example:Simplify
F ( A, B, C, D ) ∑m (1,3, 7,11,15 ) + ∑d(0, 2,5)
=
f ( ABC
= ) C A+B ( ) Solution:Substituting all the 1s & don’t
cares in the 4 variable K-map we get
2.3.3 4-VARIABLE K-MAP
A 4 variable K-map can be used for

simplification of 4 variable functions. The
possible sizes of groups in 4 variables K-
map are 1, 2, 4, 8 & 16.
In the upper quad we have covered 2 don’t

cares so that a pair can be converted into a
quad while the 3rd don’t is left unconvered
because it is not necessary to cover all the
don’t cares. f ( A, B, C, D
= ) AB + CD
Example:Simplify
f ( A, B, C, D ) = ∑m(1, 2, 4,9,10,11,12,14,15)
Solution:
f ( A, B, C, D ) =AC + BCD + BCD + BCD
GATE QUESTIONS(EC)
Q.1 The number of distinct Boolean [GATE -2005]

expressions of 4 variables is
a) 16 b) 256 Q.5 The Boolean function = Y AB + CD
c) 1024 d) 65536 is to be realized using only 2-input
[GATE -2003] NAND gates. The minimum number
of gates required is
Q.2 If the function W,X Y, and Z are as a)2 b)3
follows c)4 d)5
W =R + PQ + RS [GATE -2007]
X = PQRS + PQRS + PQRS
Q.6 The Boolean expression
Y = RS + PR + PQ + PQ Y = ABCD + ABCD + ABCD + ABCD
Z = R + S + PQ + PQR + PQS Then can be minimized to
a)=W Z, = X Z b)=W Z, =X y a) Y = ABCD + A B C + A C D
c) W = Y d) W = Y = Z b) Y = ABCD + BCD + ABCD
[GATE -2003] c) Y= ABCD + BCD + ABCD
d) =
Y A B C D + BCD + A B CD
Q.3 The Boolean expression AC+BC is [GATE -2007]
equivalent to
a) AC + BC + AC Q.7 If X=1 in the logic equation
b) BC + AC + BC + ACB  {  }
 X+Z Y+ ( Z+XY )  {X+Z ( X+Y )} =1
c) AC + BC + BC + ABC then
d) ABC + ABC + ABC + ABC a) Y=Z b) Y = Z
[GATE -2004] c) Z = 1 d) Z = 0
[GATE -2009]
Q.4 The Boolean expression for the
truth table shown is Q.8 In the sum of products function
A B C f f ( X, Y, Z ) = ∑(2,3, 4,5)
0 0 0 0
The prime implicants are
0 0 1 0
a) XY + XY
0 1 0 0
b) XY + XYZ + XYZ
0 1 1 1
1 0 0 0 c) XYZ + XYZ + XY
1 0 1 0 d) XYZ + XYZ + XYZ + XYZ
1 1 0 1 [GATE -2012]
1 1 1 0
a) B ( A + C ) (A + C) Q.9 In the circuit shown below Q1 has
negligible collector –to –emitter
b) B ( A + C ) (A + C)
saturation voltage and the diode
c) B ( A + C ) (A + C) drops negligible voltage across it
number forward bias. If I Vcc is +5V,
d) B ( A + C ) (A + C)
X and Y are digital signals with 0 Vas
logic 0 and Vcc as logic 1, then the
Boolean expression for Z is
a) (X Y
+ + Z).(X + Y + Z).(X + Y + Z)
b) ( X + Y + Z ) .(X + Y + Z).(X + Y + Z)
c) (X + Y + Z).(X + Y + Z).(X + Y + Z).
(X + Y + Z). ( X + Y + Z )
d) ( X + Y + Z ) .(X + Y + Z).(X + Y + Z).
a) XY b) XY (X + Y + Z).(X + Y + Z)
c) XY d) XY [GATE-2015]
[GATE -2013]
Q.14 Following is the K-map of a Boolean
Q.10 The Boolean express to function of five variables P, Q, R, S
and X. The minimum sum-
( X + Y ) ( X + Y ) + (X + Y) + X
simplifies to
a) X b) Y
c) XY d) X + Y
[GATE-2014]
Q.11 Consider the Boolean function,

a) PQSX + PQS X + QRSX + QRSX
F ( w, x, y, z ) = wy + xy + wxyz
b) QSX + QSX
+ wxy + xz + xyz. Which one of the
c) QSX + QSX
following is the complete set of
essential prime implicants? d) QS + QS
a) w, y, xz, xy b) w, y, xz [GATE-2016]
c) y, x y z d) y, xz, xz
Q.15 Which one of the following gives the
[GATE-2014]
simplified sum of products
expression for the Boolean function
Q.12 For an n-variable Boolean function,
F=m0+m2+m3+m5, where m0, m2, m3,
the maximum number of prime
m5, are minterms corresponding to
implicants is
the inputs A, B and C as the MSB and
a) 2 ( n − 1) b) n / 2
C as the LSB?
c) 2n d) 2(n −1) a) AB+ABC+ABC
[GATE-2014]
b) AC+AB+ABC
Q.13 A function of Boolean variables X, Y c) AC+AB+ABC
and Z is expressed in terms of the d) ABC+AC+ABC
min‒terms F ( X, Y, Z ) = ∑(1, 2,5, 6, 7) [GATE-2017, Set 1]
Which one of the product of sums
given below is equal to the function Q.16 A function F (A, B, C) defined by
F ( X, Y, Z ) ? three Boolean variables A, B and C
when expressed as sum of products
is given by F = A.B.C + A.B.C + A.B.C
where A , B , C are the
complements of the respective
variables. The product of sum (POS)
form of the function F is
a) F = ( A + B + C) ( A + B + C) ( A + B + C)
b) F = ( A + B + C )( A + B + C )( A + B + C )
c)
F= ( A + B + C )( A + B + C )( A + B + C )( A + B + C )( A + B + C )
d)
F= ( A + B + C )( A + B + C ) ( A + B + C ) ( A + B + C ) ( A + B + C )
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
(d) (a) (d) (a) (b) (d) (d) (a) (b) (a) (d) (d) (b) (b) (b)
16
(c)
EXPLANATIONS
Q.1 (d) = RS + PQ + PQ + PQR + PQR + QR
2= 2= 2= = RS + PQ + QR ( P + P ) + QR
2n 24 16
65536
Q.2 (a) = RS + PQ + QR
a)
d)
b)
Z = R + S + PQ + PQR + PQS
= R + S + PQ • PQR • PQS
= R + S + ( P + Q ) ( P + Q + R ) (P + Q + S)
W =R + PQ + RSX = PQRS + PQRS + PQRS
c) =R + S + ( PQ + PR + PQ + QR ) (P + Q + S)
=R + S + PQ + PQ + PQS + PR + PQR
+ PRS + PQ + PQS + PQR + QRS
=R + S + PQ + PR + PQS + PQR
+ PRS + PQS + PQR + QRS
= R + S + PQ (1 + S) + PR(1 + Q)
Y = RS + PR + PQ + PQ + PRS + PQS + PQR + QRS

=R + S + PQ + PR + PRS + PQS + PQR + QRS
= RS + PR.PQPQ
=R + S + PQ + PR + PQS + PQR + QRS
= RS + ( P + R )( P + Q ) (P + Q)
= R + S + PQ + PR (1 + Q ) + PQS + QRS
= RS + ( P + PQ + PR + QR ) (P + Q)
=R + S + PQ + PR + PQS + QRS
K-Map (1) = K-Map (4) = B ( AC + AC )
∴W = Z
From map (2) & (4) =B ( A + C ) (A + C)
X=Z SOP of XOR = POS of XNOR
Q.3 (d)
AC + BC
Q.5 (b)
Y = AB + CD = A.B + C.D
a) AC + BC + AC
b) BC + AC + BC + ACB
Q.6 (d)
K-map corresponding to given
Boolean expression
Simplified expression from the

K=map
c) AC + BC + BC + ABC Y = ABCD + ABCD + BCD
d) ABC + ABC + ABC + ABC
Q.7 (d)
 {  }
 X + Z Y + ( Z + XY )   X + Z ( X + Y )  =
 1
↑ ↓ ↓
=1 =0 =1
_______________________
=1
⇒ Z (1 + Y ) =1
⇒Z=
1
⇒Z=0
∴ Figure (d) matches with question. Q.8 (a)
Alternate method
f ( X, Y, Z ) = ∑(2,3, 4,5)
ABC + ABC + ABC + ABC
AC ( B + B ) + BC ( A + A ) = AC + BC
Q.4 (a)
=f ABC + ABC
∴ f ( X, Y, Z ) =
XY + XY
So, the essential prime implicants

Q.9 (b) (EPI) are y, xz, xz
Q.12 (d)
For an n-variable Boolean function,
the maximum number of prime
implicants = 2(n −1)
Z = XY
Q.10 (a)
Given Boolean Expression is Q.13 (b)
Given min term is:
( X + Y ) ( X + Y ) + (X + Y) + X F ( X, Y, Z ) = ∑ (1, 2,5, 6, 7)
As per the transposition theorem So, max term is :
( A + BC ) =( A + B )( A + C ) F ( X, Y, Z ) = πM ( 0,3, 4 )
so, ( X + Y ) (X + Y) =X + YY =X + 0 POS = ( X + Y + Z ) ( X + Y + Z )( X + Y + Z )
( X + Y ) ( X + Y ) + (X + Y) + X
= X + (XY).X Q.14 (b)
=X + (X Y).X
+ =X + XX. + Y.X
= X + 0 + Y.X
Apply absorption theorem
= X (1 + Y ) = X .1 = X
Q.11 (d)
Given Boolean Function is
F ( w, x, y, z ) = wy + xy + wxyz + wxy + xz + xyz.
By using K-map
Minimum sum of product
expression of the function is
QSX + QSX
Q.15 (b)
F = m 0 + m 2 + m3 + m5
Q.16 (c)
F ( A, B, C ) = ABC + ABC + ABC

F ( A, B, C ) = Σm ( 000, 010,100 )
= Σm ( 0, 2, 4 )
=Πm (1,3,5, 6, 7 )
=Πm ( 001, 011,101,110,111)
F= ( A + B + C )( A + B + C )( A + B + C )( A + B + C )( A + B + C )
GATE QUESTIONS(EE)
Q.1 The Boolean expression Q.4 In the sum of products function

XYZ+XYZ+XYZ+XYZ+XYZ can be f ( X,Y,Z ) = ∑(2,3,4,5)
simplified to The prime implicants are
a) XZ+XZ+YZ b) XY+YZ+Y Z a) XY+XY
c) XY+YZ+XZ d) XY+YZ+XZ b) XY+XYZ+XYZ
[GATE-2003] c) XYZ+XYZ+XY
d) XYZ+XYZ+X Y¯ Z+XYZ
Q.2 The simplified from of the Boolean
[GATE-2012]
expression
Y= ( ABC+D )( AD+BC ) can be written as Q.5 Which of the following is an invalid
a) AD+BCD b) AD+BCD state in an 8-4-2-1. Binary Coded
c) ( A+D)(BC+D ) d) AD+BCD Decimal counter
a) 1 0 0 0 b) 1 0 0 1
[GATE-2004] c) 0 0 1 1 d) 1 1 0 0
[GATE-2014-01]
Q.3 Which of the following circuits is a
realization of the above function F? Q.6 The SOP (sum of products) form of a
a)
Boolean function is E ( 0,1,3, 7,11) ,
where inputs are A, B, C, D (A is
MSB, and D is LSB). The equivalent
minimized expression of the
function is
b) a) ( B + C ) ( A + C ) + ( A + B )( C + D )
b) ( B + C ) ( A + C ) + ( A + C )( C + D )
c) ( B + C ) ( A + C ) + ( A + C )( C + D )
d) ( B + C )( A + B ) + ( A + B )( C + D )
c) [GATE-2014-01]
Q.7 f ( A,B,C,D ) = ΠM ( 0,1,3,4,5,7,9,11,12,13,14,15)
is a maxterm representation of a
Boolean function f ( A, B, C, D )
where A is the MSB and D is the LSB.
The equivalent minimized
d) representation of this function is
a) (A + C + D)(A + B + D)
b) ACD + ABD
c) ACD + ABCD + ABCD
d) (B + C + D)(A + B + C + D)(A + B + C + D)
[GATE -2010] [GATE-2015-01]
Q.10 The Boolean expression
Q.8 Consider the following Sum of (a + b + c + d) + (b + c) Simplifies to
products expression,
F = ABC + ABC + ABC + ABC + ABC a) 1 b) a.b
The equivalent Product of Sums c) a.b d) 0
expression is [GATE-2016-02]
a) F = (A + B + C)(A + B + C)(A + B + C)
b) F = (A + B + C)(A + B + C)(A + B + C) Q.11 The Boolean expression,
AB + AC + BC simplifies to
c) F = ( A + B + C ) ( A + B + C ) (A + B + C)
d) F = (A + B + C)(A + B + C)(A + B + C) a) BC + AC
[GATE-2015-02] b) AB + AC + B
c) AB + AC
Q.9 The output expression for the d) AB + BC
Karnaugh map shown below is [GATE-2017-01]
Q.12 Digital input signals A, B, C with A as

the MSB and C as the LSB are used to
realize the Boolean function
F = m 0 + m 2 + m3 + m5 + m 7 , where
+
a) A B +
b) A C
mi denotes the ith minterm. In
+
c) A C +
d) A C
addition. F has a don't care for m1 .
[GATE-2016-02]
The simplified expression for F is
given by
a) AC + BC + AC
b) A + C
c) C + A
d) AC + BC + AC
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12
(b) (a) (d) (a) (d) (a) (c) (a) (b) (d) (a) (b)
EXPLANATIONS
Q.1 (b)
By K-map
∴ f ( X,Y,Z ) =XY+XY
The simplified from is XY+YZ+YZ
Q.5 (d)
Q.2 (a) In binary coded decimal (BCD)
Y= ( ABC+D )( AD+BC ) counter the valid states are from 0
=ABCD+AD+BCD to 9 only in binary system 0000 to
1001 only. So, 1100 in decimal it is
= ( AD+BCD ) (A+1=1)
12 which is invalid state in BCD
counter.
Q.3 (d)
From the figure it is clear that, two
NAND gates generate the X and Y Q.6 (a)
and now two AND gates with i/ps X
and Y and inputs Y and Z is used to
generate two terms of SOP form and
now OR gate is used to sum them
and generate the F.
Q.4 (a)
f ( X,Y,Z ) = ∑(2,3,4,5)
The equivalent minimized

expression of this function is
( B + C ) ( A + C ) + ( A + B)( C + D )
Also, F has don’t care at m1
Q.7 (c)
f ( A, B, C,=D ) ACD + ABD F ( A, B, C ) = Σm ( 0, 2,3,5, 7 ) + Σφ (1)
In options (c)
f ( A, B, C, D ) =ACD + ABCD + ABCD
=ACD + ABD(C + C)
= ACD + ABD.1
= ACD + ABD.
Σm ( 0,1, 2,3) =
F1 = A
Σm (1,3,5, 7 ) =
F2 = C
F = F1 + F2 = A + C
Hence, the correct option is (B).
Q.8 (a)
Given minterm is
F = Σm(0,1,3,5, 7)
F = πm ( 2, 4, 6 )
So product of sum expression is
F = (A + B + C)(A + B + C)(A + B + C)
Q.9 (b)
F ( A, B, C ) = A + C
Q.10 (d)
F = (a + b + c + d) + (b + c)
=a + d + (b + b) + (c + c)
= a + d + 1+ 1 = 1 = 0
Q.11 (a)
Q.12 (b)
F = m 0 + m 2 + m3 + m5 + m 7
GATE QUESTIONS(IN)
Q.1 Min-term (Sum of products) Q.5 The minimal sum- of products

expression for a Boolean function is expression for the logic function f
given as follows. represented by the given Karnaugh
f ( A,B,C ) = ∑m ( 0,1, 2,3,5, 6 ) map is
where A is the MSB and C is the LSB.
The minimized expression for the
function is
a) A + (B ⊕ C) b) ( A ⊕ B ) + C
c) A + ( B ⊕ C ) d) ABC
[GATE-2006]
a) QS+PRS+PQR+PRS+PQR
Q.2 A logic circuit implements the b) QS+PRS+PQR+PRS+PQR
Boolean function F=X.Y+X.Y.Z .It c) PRS+PQR+PRS+PQR
is found that the input combination d) PRS+PQR+PRS+PQR
X=Y=1 can never occur. Taking this
[GATE-2009]
into account, a simplified expression
for F is given by
Q.6 For the Boolean expression
a) X+Y.Z b) X+Z
f = abc+abc+abc+abc+abc, the
c) X+Y d) Y + XZ
minimized Product of Sum (POS)
[GATE-2007]
expression is
Q.3 Let X= X1X 0 and Y=Y1Y0 be ( b + c ) .(a + c)
a) f =
unsigned 2- bit numbers. The ( b + c ) .(a + c)
b) f =
function F=1 if X>Y and F = 0
otherwise. The minimized sum of
c) f =( b + c ) .(a + c)
products expression for F is d) f= c + abc
a) Y1Y0 +X 0 Y0 +X1.X 0 .Y1 [GATE-2011]
b) X 0 .Y1 + Y1 Y 0 + X1 .X 0 Q.7 The output Y of a 2-bit comparator

is logic 1 whenever the 2- bit input A
c) Y1.X1 +Y0 .X1.X 0 +Y1.Y0 .X 0 is greater than the 2-bit input B. The
d) X1.Y1 +X 0 .Y 0 Y1 +X1.X 0 .Y 0 number of combinations for which
[GATE-2007] the output is logic 1, is
a) 4 b) 6
Q.4 The minimum sum of products form c) 8 d) 10
of the Boolean expression [GATE-2012]
Y = PQRS + PQRS + PQRS + PQRS Q.8 In the sum of products function
+ PQRS + PQRS is f ( X,Y,Z ) = ∑(2,3, 4,5)
a) Y=PQ+QS b) Y=PQ+QRS The prime implicates are
c) Y=PQ+QRS d) Y=QS+PQR a) XY,XY
[GATE-2008] b) XY,XYZ,XYZ
c) XYZ,XYZ,XY Q.10 The Boolean expression XY+(X’+Y’)Z
equivalent to
d) XYZ,XYZ,XYZ, XYZ
a) XYZ’ + X’Y’Z’ b) X’Y’Z’ + XYZ
[GATE-2012] c) (X+Z)(Y+Z) d)(X’+Z)(Y’+Z)
Q.9 A bulb in a star case has two [GATE-2016]
switches, one switch being at the
ground floor and the other one at
the first floor. The bulb can be Q.11 The product of sum expression of a
turned ON and also can be turned Boolean function F(A, B, C) of three
OFF by any one of the switch
variables is given by
irrespective of the state of the other
switch. The logic of switching of the F ( A, B, C ) = ( A + B + C )( A + B + C )( A + B + C )( A + B + C )
bulb resembles The canonical sum of product
a) An AND gate b) An OR gate expression of F(A, B, C) is given by
c) A XOR gate d)A NAND gate
[GATE-2013] a) ABC + ABC + ABC + ABC
b) ABC + ABC + ABC + ABC
c) ABC + ABC + ABC + ABC
d) ABC + ABC + ABC + ABC
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11
(c) (d) (d) (a) (d) (a) (b) (a) (c) (c) (b)
EXPLANATIONS
Q.1 (c) Q.4 (a)

From K –map Y=PQRS+PQRS+PQRS+PQRS+
PQRS+PQRS
By k-map
f=A+BC+BC
= A+B ⊕ C
Q.2 (d)
Since, the combination X=Y=1
cannot occur, this can treated as Y=PQ+QS
don’t care input combination.
Q.5 (d)
In the first step group of 4 is
consider. The group of 4 can
avoided since, four number of
From the K-map F=Y+XZ groups each of two1S (duets) will
exhaust all the 1S present. For this
Q.3 (d) case, the solution will be
F=1 if X>Y ,so following will K- PRS+PQR+PRS+PQR
map of function F. K map for function f,
Q.6 (a)
F=X1Y1 +X 0 Y1Y0 +X1X 0 Y0 f = abc + abc + abc + abc + abc
= ac ( b + b ) + abc + ab(c + c)
=ac + abc + ab
∴ f ( X,Y,Z ) =XY+XY
S1 S2 Bulb
0 0 0 Q.9 (c)
0 1 1 When both switches in on position
1 0 1 bulb is off When both switches in off
1 1 0 position bulb is off
It is a XOR gate
=ac + a[b + bc]
=ac+a ( b+b ) (b+c)  Q.10 (c)
XY+(X+Y)Z=XY+XYZ
=ac + a(b + c)
=(XY + XY)(XY + Z)
= ac + ab + ac
= XY + Z
=ab + c(a + a)
=(X + Z)(Y + Z)
= ab + c
= (c + a)(c + b)
Q.11 (b)
= (b + c)(a + c)
F ( A, B, C ) = ( A + B + C )( A + B + C )( A + B + C )( A + B + C )
= π m(1,3, 4, 7)
Q.7 (b)
A A B B Y = ΣM (0, 2,5, 6)
1 0 1 0 = m0 + m2 + m5 + m6
0 0 0 0 0 = ABC + ABC + ABC + ABC
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
From the truth table we see that the
number of times ‘Y’ becomes 1 is 6
Q.8 (a)
f ( X,Y,Z ) = ∑(2,3, 4,5)
3 LOGIC GATES
3.1 INTRODUCTION
A logic gate is a general purpose electronic

device used to construct logic circuits. All
logic gates have inputs and outputs. The
If the time propagation delay of each NOT
state of the output is set by the input states
gate is t pd , then the time period of output
using different rules depending on the type
of gate. square wave is T =TON + TOFF =3t pd + 3t pd
Voltages at the inputs can be set to +5v =
2 × 3t pd =
6t pd
(called 'logic 1' or 'high') or to 0v (called
If n (odd) number of NOT gates are used
'logic 0' or 'low'). The logic gates are
T= 2 × nt pd
classified as:
3.2 BASIC GATES b. Bistable Multivibrator:
1. NOT Gate: A NOT gate, often called an

inverter, is a nice digital logic gate to
start with because it has only a single
input with simple behavior. A NOT gate
performs logical negation on its input.
In other words, if the input is logic 1, 1. AND Gate: An AND gate is a digital
then the output will be logic 0. logic gate with two or more inputs
Similarly, a logic 0 input results in and one output that performs logical
a logic 1 output. conjunction. The output of an AND
A Output gate is logic 1 only when all of the
0 1 inputs are logic 1. If one or more
inputs of an AND gate are logic 0,
1 0
then the output of the AND gate
is logic 0.
Switching Circuit: The truth table for an AND gate with
two inputs appears below.
A B Output
When switch is closed i.e. A=1 bulb will 0 0 0
be OFF i.e. o/p will be 0. 0 1 0
1 0 0
Applications: 1 1 1
a. Astable Multivibrator:
with behavior that is the opposite of an
Switching Circuit AND gate. The output of a NAND gate
is logic 1 when one or more of its inputs
are logic 0. If all inputs of a NAND gate
are logic 1, then the output of the NAND
gate is logic 0.
The truth table for a NAND gate with
two inputs appears below.
2. OR Gate: An OR gate is a digital logic

gate with two or more inputs and
one output that performs logical
disjunction. The output of an OR
A B Output
gate is logic 1 when one or more of 0 0 1
its inputs are logic 1. If all inputs of 0 1 1
an OR gate are logic 0, then the 1 0 1
output of the OR gate is logic 0. 1 1 0
The truth table for an OR gate with
two inputs appears below a. NOT Gate using NAND Gate:
b. AND Gate using NAND Gate:

A B Output
0 0 0
0 1 1
1 0 1
c. OR Gate using NAND Gate:
1 1 1
Switching Circuit:
d. XOR Gate using NAND Gate:
3.3 UNIVERSAL GATES
There are two universal Gates NAND &

NOR Gates. These are called universal gate
e. XNOR Gate using NAND Gate:
because all other logic gates can be
designed using these gates.
1. NAND Gate: A NAND gate (sometimes

referred to by its extended name,
Negated AND gate) is a digital logic gate
with two or more inputs and one output
2. NOR Gate: A NOR gate (sometimes
referred to by its extended name, e. X-NOR Gate using NOR Gate:
Negated OR gate) is a digital logic gate
with two or more inputs and one output
with behavior that is the opposite of an
OR gate. The output of a NOR gate
is logic 1 all of its inputs are logic 0. If
one or more of a NOR gate's inputs
are logic 1, then the output of the NOR
gate is logic 0. The truth table for a NOR No. of NAND No. of NOR
gate with two inputs appears below. Gates
Gates Gates
NOT 1 1
AND 2 3
OR 3 2
XOR 4 5
XNOR 5 4
A B Output
0 0 1 3.4 SPECIAL PURPOSE GATES
0 1 0
1 0 0 1) X-OR Gate: An XOR gate (sometimes
1 1 0 referred to by its extended name,
Exclusive OR gate) is a digital logic gate
a. NOT Gate using NOR Gate: with two or more inputs and one output
that performs exclusive disjunction.
The output of an XOR gate is logic
1 only when exactly one of its inputs
b. AND Gate using NOR Gate: is logic 1. If both of an XOR gate's
inputs are logic 0, or if both of its inputs
are logic 1, then the output of the XOR
gate is logic 0.The truth table for an
XOR gate with two inputs appears
below.
c. OR Gate using NOR Gate:

A B Output
0 0 0
0 1 1
1 0 1
d. X-OR Gate using NOR Gate: 1 1 0
If an XOR gate has more than two 6) X e X = 1
inputs, then its behavior depends on its 7) X ⊕ X = 1
implementation. In the vast majority of
8) X e X = 0
cases, an XOR gate output will be logic
1 if an odd number of its inputs 9) X ⊕ Y ' = X '⊕ Y = (X ⊕ Y) ' = X e Y
are logic 1. However, it's important to 10) X ⊕ Y =e
X Y
note that this behavior differs from the
strict definition of exclusive or, which
insists that exactly one input must Examples: Write the Boolean expression for
be logic 1 for the output to be logic 1. this truth table, then simplify that
expression & draw equivalent logic circuit.
2) X-NOR Gate: An X-NOR gate A B C Output
(sometimes referred to by its extended 0 0 0 1
name, Exclusive NOR gate) is a digital 0 0 1 1
0 1 0 1
logic gate with two or more inputs and 0 1 1 1
one output that performs logical 1 0 0 1
equality. The output of an X-NOR gate 1 0 1 1
is logic 1 when all of its inputs are logic 1 1 0 0
1 or when all of its inputs are logic 0. If 1 1 1 0
one of its inputs is logic 1 and other Solution: The POS expression for the above
is logic 0, then the output of the X-NOR truth table is
gate is logic 0. The truth-table for an X-
NOR gate with two inputs appears
Y = A+B+C A+B+C ( )( )
below. = A+B ( )
A B Output
0 0 1 Example: Find the expression for output.
0 1 0
1 0 0
1 1 1
Example: Prove that ( X ⊕ Y )’ =

Xe Y
Solution:
Xe= Y (XY’ + X’Y)’ Solution:
( XY’)’ ( X’Y )’ =
= ( X’ + Y )( X + Y’)
= ( XY + X’Y’)
= Xe Y
3.4.1 PROPERTIES OF X-OR & X-NOR GATES
1) X⊕0 = X 3.5 IMPLEMENTATION OF SOP & POS

2) Xe 0 = X EXPRESSION
3) X ⊕ 1 =X '
4) Xe 1= X
5) X⊕X = 0
An expression in SOP form can be
implemented using only NAND gates by
following the procedure
Implement the SOP expression using a 2
level AND-OR circuit.
Replace all the gates with NAND gates.
Example: Implement AB + CD using only

NAND gates.
Solution: AB+CD can be implemented
using 2 levels AND-OR circuit as
Now replace all the gates with NAND gates
An expression in POS form can be

implemented using only NOR gates by
following the procedure.
Implement the POS expression using a 2
level OR-AND circuit.
Replace all the gates with NOR gates.
Example: Implement(A + B)(C + D) using

only NAND gates.
Solution: (A + B)(C + D) can be
implemented using 2 level OR-AND circuit
as
Now replace all the gates with NAND gates
GATE QUESTIONS(EC)
Q.1 For the ring oscillator shown in the Q.4 The gates G1 and G 2 in the figure
figure, the propagation delay of each have propagation delays of 10nsec
inverter is 200 pico sec. What is the and 20 nsec respectively .If the input
fundamental frequency of the Vi makes an abrupt change from
oscillator output?
logic 0 to 1at time t = t 0 , then the
output waveform V0 is
a)10MHz b)100MHz
c)1GHz d)2GHz
[GATE -2001]
a)
Q.2 In the figure, the LED
b)
c)
a) emits light when both S1 and S2
are closed
b) emits light when both S1 and S2 d)
are open.
c) emits light when only of S1 and
S2 is closed. [GATE -2002]
d) does not emit light, irrespective
of the switch positions. Q.5 The figure shows the internal
[GATE -2001] schematic of a TTLAND-OR -Invert
(AOI)gate. For the inputs shown in
Q.3 If the input to the digital circuit (in the figure, the output Y is
the figure) consisting of a cascade of
20XOR-gates is X, then the output Y
is equal to
a) 0 b) 1
a) 0 b)1 c) AB d) AB
c) X d)X [GATE -2004]
[GATE -2002]
Q.6 The number of product terms in the a) P-2,Q-4,R-1,S-3 b) P-4,Q-2,R-
minimized sum –of product 1,S-3
expression obtained through the c) P-2,Q-4,R-3,S-1 d) P-4,Q-2,R-
following K-map is (where,”d” 3,S-1
denotes don’t’ care states) [GATE -2010]
Q.10 For the output F to be 1 is the logic
circuit shown the input combination
should be
a) 2 b) 3
c) 4 d) 5
[GATE -2005]
Q.7 The point P in the following figure is

stuck at -1 The output f will be
a) =
A 1,=
B 1,=C 0
b) =
A 1,=
B 0,=C 0
c) =
A 0,=
B 1,=C 0
d)=A 0,=
B 0,=C 1
a) ABC b) A [GATE -2010]
c) ABC d)𝐴𝐴̅
Q.11 The output Y in the circuit below is
[GATE -2006] always “1” when
Q.8 Which of the following Boolean
Expressions correctly represents
the relation between P, Q,R and M1 ?
a) two or more of the inputs, P,Q,R

are “0”
b) two or more of the inputs, P,Q,R
a) M1 = ( PORQ ) XORR
are “1”
b) M1 = ( PANDQ ) XORR c) any odd number of the inputs
c) M1 = ( PNORQ ) XORR P,Q,R is “0”
d) any odd number of the inputs
d) M1 = ( PXORQ ) XORR P,Q,R is “1”
[GATE -2008] [GATE -2011]
Q.9 Match the logic gates in Column A
with their equivalents in Column B Q.12 A bulb in a star case has two
the first floor. The bulb can be
turned ON and also can be turned
OFF by any one of the switch
switch. The logic of switching of the
bulb resembles
a) An AND gate b) An OR gate
c) A XOR gate d) A NAND gate
[GATE -2013]
Q.16 In the circuit shown, diodes D1 , D 2
Q.13 The output F in the digital logic and D3 are ideal, and the inputs
circuit shown in the figure is
E1 , E 2 and E 3
=
a) F XYZ + XYZ =
b) F XYZ + XYZ
=
c) F XYZ + XYZ d)
= F XYZ + XYZ
[GATE-2014] a) 3 input OR gate
b) 3 input NOR gate
Q.14 A 3-input majority gate is defined by c) 3 input AND gate
the logic function d) 3 input XOR gate
M ( a, b, c ) = ab + bc + ca . Which one [GATE-2015]
of the following gates is represented Q.17 The minimum number of 2-input
by the function NAND gates required to implement
M(M(a, b, c), M(a, b, c), c) ? a 2-input XOR gate is
a) 3-input NAND gate a) 4 b) 5
b) 3-input XOR gate c) 6 d) 7
c) 3-input NOR gate [GATE-2016]
d) 3-input XNOR gate
[GATE-2015] Q.18 The output of the combination
circuit given below is
Q.15 In the figure shown, the output Y is
required to be =
Y AB + CD .The gates G1
and G2 must be, respectively,
a) A+B+C b) A(B+C)
c) B(C+A) d) C(A+B)
[GATE-2016]
a)NOR, OR b)OR, NAND
c) NAND, OR d) AND, NAND
[GATE-2015] Q.19 The logic gates shown in the digital
circuit below use strong pull-down
nMOS transistors for LOW logic
level at the outputs. When the
pull-downs are off, high-value
resistors set the output logic levels
to HIGH (I.e. the pull-ups are weak).
Note that some nodes are
intentionally shorted to
implement “wired logic”. Such
shorted nodes will be HIGH only if
the outputs of all the gates whose
outputs are shorted are HIGH.
The number of distinct values of

X 3 X 2 X1X 0 (out of the 16 possible
values) that give Y =1is _______.
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12 13 14
(c) (d) (b) (b) (a) (a) (d) (d) (d) (d) (b) (c) (a) (b)
15 16 17 18 19
(a) (c) (a) (c) 8
EXPLANATIONS
Q.1 (c) Q.5 (a)

t pd of all 5 intervals For TTL logic floating input =1
∴ Y= ( AB + 1) = AB.0= 0
'
= 5 ×100p sec = 500psec
∴ Fundamental frequency of
oscillator Q.6 (a)
1
=
Output = 1GHz
2 × 500ps
Q.2 (d)
For LED to be ON, output of NAND
gate = 0
No condition of S1 and S2 gives
output of NAND gate zero, So LED Q.7 (d)
will never glow.
Q.3 (b)
Output of 1st XOR gate = X
Output of 2nd XOR gate= X ⊕ X
( )
= X • X + X • X = X + X =1
Output of 20 XOR gates is 1
Q.8 (d)
Q.4 (b)
M1  PQ(P + Q)  ⊕ R
= ( P + Q ) (P + Q)  ⊕ R
= (P ⊕ Q) ⊕ R
Q.9 (d)
NOR gate is equivalent to INVERT-
AND gate.
NAND gate is equivalent to INVERT
–OR gate.
It is a XOR gate
Q.13 (a)
Assume dummy variable K as a
output of
XOR gate K = X ⊕ Y = XY + XY
F = K.(K e Z)
Q.10 (d) = (KZ + KZ)

= K.KZ + KKZ
=
0 + K.Z ( ∴ K. | K =
0 and K.K =
K)
Put the value of K in above
expression
=F (XY + XY)Z
= XYZ + XYZ
If A=0, B=0 then
X = AB + AB = 0 Q.14 (b)
Y = AB + AB = 1 M ( a, b, c ) = ab + bc + ac = ∑ ( 3,5, 6, 7 )
F will be ‘1’ if even number of inputs
to XNOR gate is ‘1’; hence option (d)
=
M(a, b, c) ∑
= m ( 0,1, 2, 4 ) X
is the correct answer. (let say for simplicity)
M(a, b, c) = ab + bc + a c = ∑ m ( 2, 4, 6, 7 ) = Y
Q.11 (b) (let)
Take two or three input ‘1’ then we= c ∑ =m (1,3,5, 7 ) z (let)
always get’1’
f  M(a, b, c) , M(a, b, c), c  = f ( x , y, z ]
OR
Take two or three input zero then = xy + yz + zx
we always get ‘0’ hence option ‘b’ is
true and output
=  ∑ m ( 0,1, 2, 4 ) ∑ m ( 2, 4, 6, 7 ) ( )( ) 
Y = PQ + PR + RQ +  ∑ m ( 2, 4, 6, 7 ) ∑ m (1,3,5, 7 ) ( )( ) 
Q.12 (c) + ( ∑ m (1,3,5, 7 ) ) ( ∑ m ( 0,1, 2, 4 ) ) 1
When both switches in on position
bulb is off
= ∑ m ( 2, 4 ) + ∑ m ( 7 ) + ∑ m(1)
S1 Bulb = ∑ M (1, 2, 4, 7 )
S2
0 0 0 ∴ ADN operate is like int er sec tion 
 
0 1 1  OR operator is like union 
1 0 1 = A ⊕ B ⊕ C = A e B e C(s tan dard result)
1 1 0 Both options (d) and (b) are correct
When both switches in off position
bulb is off
Q.15 (a)
Given expression is =
Y AB + CD
The first term can be obtained by
considering G1 as NOR gate, and
second term (CD) is obtained from
another lower NOR-Gate. So, final
expression can be implemented by
considering G2 as OR-Gate.
Q.16 (c)
Case (i): If any input is logic 0 (i.e, 0V) then
the corresponding diode is “ON” and
due to ideal diode output voltage
V0 = 0 as well as if there is any input
logic 1 (i.e.,10V) corresponding
diode will be OFF. From above two circuit, always Y = x3
Case (ii) : If all the inputs are high (i.e., 10V) X3 X2 X1 X0 Y
then all the diodes are R.B (OFF) and 0 0 0 0 0
output voltage V0 = 10V 0 0 0 1 0
So, it is a positive logic 3-inputs AND 0 0 1 0 0
gate. 0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
Q.17 (a) 0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
Q.18 (c) 1 1 1 0 1
1 1 1 1 1
y = ABC ⊕ AB ⊕ BC
The number of distinct values of
=  ABC.AB + ABC.AB ⊕ BC
X 3 X 2 X1X 0 (out of the 16 possible
= ( A + B + C ) .AB + ABC. ( A + B )  ⊕ BC values) that give Y =1 is 8.
= ( ABC ) ⊕ ( BC )
= ABC.BC + ABC.BC
= ( A + B + C ) .BC + ABC. ( B + C )
= ABC + BC + ABC
= BC ( A + 1) + ABC = BC + ABC
= B ( C + AC ) = B ( C + A )
Q.19 8
GATE QUESTIONS(EE)
Q.1 The output of a logic gates is “1”

when all its inputs are at logic “0”.
The gate is either
a) a NAND or an EX-OR gate
b) a NOR or an EX-OR gate a) S is always with zero or odd
c) an AND or an EX-NOR gate b) S is always either zero or even
d) a NOR or an EX-NOR gate c) S=1 only if the sum of A, B, C, and
[GATE-2001] D is even
d) S=1 only if the sum of A, B, C and
Q.2 For the circuit shown in figure the D is odd
Boolean expression for the output Y [GATE-2007]
in terms of inputs P, Q, R and S is
Q.5 The complete set of only those Logic
Gates designated as Universal Gates
is
a) NOT, OR and AND Gates
b) XNOR, NOR and NAND Gates
a) P+Q+R+S c) NOR and NAND Gates
d) XOR, NOR and NAND Gates
b) P+Q+R+S [GATE-2009]
c) ( P+Q ) + ( R+S )
d) ( P+Q ) + ( R+S) Q.6 The output Y of the logic circuit
given below is
[GATE-2002]
Q.3 If 𝑋𝑋1 and 𝑋𝑋2 are the inputs to the

circuit
shown in the figure, the output Q is a) 1 b) 0
c) x d) x
[GATE-2011]
Q.7 A bulb in a stair case has two

a) ¯X1 + X 2 b) X1.X 2 ¯ the first floor. The bulb can be
c) X1.X 2 d) X1.X 2 turned ON and also can be turned
[GATE-2005] OFF by any one of the switch
Q.4 A, B, C and D are input, and Y is the switch. The logic of switching of the
output bit in the XOR gate circuit of bulb resembles
the figure below. Which of the a) An AND gate b) An OR gate
following statements about the sum c) A XOR gate d)A NAND gate
S of A, B, C, D and Y is correct? [GATE-2013]
Q.8 Which of the following logic circuits Q.9 For a 3-input logic circuit shown
is a realization of the function F below, the output Z can be
whose Karnaugh map is shown in expressed as
figure.
a) Q+R
b) PQ + R
c) Q+R
d) P+Q+R
[GATE-2017]
Q.10 In the logic circuit shown in the figure,

Y is given by
a) Y = ABCD
( A + B )( C + D )
b) Y =
c) Y = A + B + C + D
d) =
Y AB + CD
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10
(d) (b) (d) (b) (c) (a) (c) (c) (c) (d)
EXPLANATIONS
Q.1 (d)
We know that sum of any no. of bits
is XOR of all bits.
So S=A ⊕ B ⊕ C ⊕ D ⊕ Y
S=Y ⊕ Y
S=either zero or even because LSB is
Y = AB = A + B → NOR GATE zero (always)
Y=AB+AB → EX-NOR GATE
Q.5 (c)
Q.2 (b) Nor and NAND are designated as
universal logic gates because using
Y=( PgQ )g( R gS ) any one of them we can implement
Q (AgB)=(A+B) all the logic gates.
Y=( PgQ ) + ( R gS ) Q.6 (a)

⇒ Y = (P + Q + R + S) x 𝑥𝑥 Y
1 0 1
Q.3 (d) 0 1 1
Y1 =X1 Y = x x + xx = 1
Output, Q=Y1+X2
Q.7 (c)
=(X1 +X 2 )
Q=X1.X 2
Q.4 (b)
Y = A ⊕ B ⊕ C ⊕ D from the given
diagram.
When both switches in on position

bulb is off When both switches in off
Position bulb is off. It is a XOR gate
Q.8 (c)
Q.9 (c)
Z = PQ.Q.Q.R
= PQ + Q + Q.R
= PQ + Q + QR
= Q ( P + 1) + QR
= Q + QR
=( Q + Q ) . ( Q + R ) =Q + R
Q.10 (d)
= = AB + CD
f AB.CD
= AB + CD
GATE QUESTIONS(IN)
Q.1 The logic gate circuit shown in the TEST which was at logic LOW is
figure realizes the function switched to logic HIGH and
maintained at logic HIGH. The
output
a) XOR b) XNOR
c) Half adder d) Full adder a) stays HIGH throughout
[GATE-2010] b) stays LOW throughout
c) pulses from LOW to HIGH to LOW
Q.2 In the circuit shown, the switch is d) pulses from HIGH to LOWto HIGH
momentarily closed and then [GATE-2015]
opened. Assuming the logic gates to
have equal non-zero delay, at steady Q.5 In the digital circuit given below, F
state, the logic states of X and Y are is:
a) X is latched, Y toggles a) XY+Y𝑍𝑍 b) XY+𝑌𝑌 Z

continuously c) 𝑋𝑋 𝑌𝑌 +Y𝑍𝑍 d) XZ+𝑌𝑌
b) X and Y are both latched [GATE-2016]
c) Y is latched, X toggles
continuously Q.6 The comparators (output = ‘1’ when
d) X and Y both toggle continuously input ≥ 0 and output = ‘0’ when
[GATE-2015] input < 0), exclusive-OR gate and the
unity gain low-pass filter given in
Q.3 The logic evaluated by the circuit at the circuit are ideal. The logic output
the output is voltages of the exclusive-OR gate are
0 V and 5 V. The cutoff frequency of
the low pass filter is 0.1 Hz for
V1=1sin(3000t+36 °)V and V2 = 1
sin (3000t) V, the value of VO in volt
is ____________.
a) XY + YX (
b) X + Y XY )
c) XY + XY d) XY + XY + X + Y
[GATE-2015]
Q.4 Consider the logic circuit with input

signal TEST shown in the figure. All
gates in the figure shown have
identical non-zero delay .The signal [GATE-2016]
Q.7 The Boolean function F(X,Y) realized
by the given circuit is
a) XY + X Y
b) X Y + XY
c) X + Y
d) X Y
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7
(a) (d) (a) (d) (b) 1 (a)
EXPLANATIONS
Q.1 (a) → Assuming the delay of NAND

gate is 0. First draw output
waveform (ideal case) then shift
that by 10 msec. i.e. introduce the
delay.
Z = xy + xy = xy + xy = x ⊕ y
Q.2 (d)
X Y
0 1
1 0
0 1
1 0
Bothe X and Y will toggle
continuously.
So we can clearly say that initial
Q.3 (a) output change from high to low,
Output of upper AND gate is X𝑌𝑌 then it changes from low to high and
Output of lower AND gate is 𝑋𝑋Y then finally at steady state output is 1.
Output of OR gate is X𝑌𝑌 + 𝑋𝑋Y Note: Saying output is high (option
A) will be wrong here. We are not
interested to find steady state output.
Q.4 (d)
For analysis point of view, assume
Q.5 (b)
delay of each gate is 10 msec.
From the circuit
However we can take any value.
→ By referring the circuit the upper = = XY + YZ
F XY.YZ
input to the NAND gate is direct test
signal. The lower input to NAND
gate is TEST but with a delay of 30
nsec.
It is a very well know standard 2
input XOR gate implementation
Q.6 (1)
circuit only by using 2 input NAND
gates. (Directly we can select the
option, without doing above
simplification steps).
Output of low pass filter is the average

value of output of XOR GATE
1 𝜋𝜋� 6𝜋𝜋�
VDC = 2𝜋𝜋 �∫0 5 5𝑑𝑑𝑑𝑑 + ∫𝜋𝜋 5 5𝑑𝑑𝑑𝑑 �
1 𝜋𝜋 6𝜋𝜋
=2𝜋𝜋 �5 �5 � + 5 � 5 − 𝜋𝜋��
1
= 2𝜋𝜋 [𝜋𝜋 + 𝜋𝜋] = 1volt
Q.7 (a)
By referring the circuit
F=
( X + Y )( X + Y )
= X +Y + X +Y
= X Y + XY
= X ⊕Y
4 LOGIC FAMILIES
4.1 INTRODUCTION p and n-channel MOSFETs are employed

and are fabricated on the same silicon chip.
Digital ICs are a collection of resistors,
diodes, and transistors fabricated on a 4.2 CHARACTERISTICS OF DIGITAL IC
single piece of semiconductor material
(usually silicon) called a substrate, which is With the widespread use of ICs in digital
commonly referred to as a chip. systems and with the development of
various technologies for the fabrication of
4.1.1 BIPOLAR LOGIC FAMILIES ICs, it has become necessary to be familiar
The main elements of a bipolar IC are with the characteristics of IC logic families
resistors, diodes (which are also capacitors) and their relative advantages and
and transistors. Basically, there are two disadvantages. Digital ICs are classified
types of operations in bipolar ICs: either according to the complexity of the
1. Saturated circuit, as the relative number of individual
2. Non-saturated. basic gates (2-input NAND gates) it would
In saturated logic, the transistors in the IC require to build the circuit to accomplish
are driven to saturation, whereas in the the same logic function or the number of
case of non-saturated logic, the transistors components fabricated on the chip. The
are not driven into saturation. The saturated classification of digital ICs is given in the
bipolar logic families are: table:
1. Resistor–transistor logic (RTL) Classification of digital ICs
2. Direct–coupled transistor logic (DCTL), IC Classification Equivalent Number of
individual components
3. Integrated–injection logic (𝐼𝐼 2 L) basic gates
4. Diode–transistor logic (DTL) Small-scale Less than 12 Up to 99
5. High–threshold logic (HTL) integration (SSI)
6. Transistor-transistor logic (TTL). Medium-scale 12-99 100-999
integration (MSI)
Large-scale 100-999 1,000-9,999
The non-saturated bipolar logic families integration(LSI)
are: Very large-scale Above 1,000 Above
1. Schottky TTL integration(VLSI) 10,000
2. Emitter-coupled logic (ECL).
The various characteristics of digital ICs
4.1.2 UNIPOLAR LOGIC FAMILIES used to compare their performances are:
1. Speed of operation (propagation delay)
MOS devices are unipolar devices and only 2. Power dissipation
MOSFETs are employed in MOS logic circuits. 3. Figure of merit
The MOS logic families are: 4. Fan-out
1. PMOS 5. Noise immunity
2. NMOS
3. CMOS 4.2.1 PROPAGATION DELAY
In PMOS only p-channel MOSFETs are used
and in NMOS only n-channel MOSFETs are The speed of a digital circuit is specified in
used, in complementary MOS (CMOS), both terms of the propagation delay time. The
input and output waveforms of a logic gate
are shown in Fig. The delay times are increase in the power dissipation and vice-
measured between the 50 percent voltage versa.
levels of input and output waveforms.
There are two delay times: t pHL , when the
output goes from the HIGH state to the
LOW state and tpLH , corresponding to the 4.2.4 FAN-OUT
output making a transition from the LOW
This is the number of similar gates which
state to the HIGH state. The propagation
can be driven by a gate. High fan-out is
delay time of the logic gate is taken as the
advantageous because it reduces the need
average of these two delay times.
for additional drivers to drive more gates.
4.2.5 NOISE IMMUNITY
The input and output voltage levels defined

The propagation delay of a logic gate is
above are shown in Fig.
t pHL + t pLH
defined as: t pd =
2
4.2.2 POWER DISSIPATION
This is the amount of power dissipated in

an IC. It is determined by the current, IC(avg) ,
that it draws from the Vcc supply, and is
given by VCC × IC(avg) .This power is specified VIH : This is the minimum input voltage
in milliwatts. which is recognized by the gate as
logic 1.
4.2.3 FIGURE OF MERIT VIL : This is the maximum input voltage
The figure of merit of a digital IC is defined which is recognized by the gate as
as the product of speed and power. The logic 0.
speed is specified in terms of propagation VOH : This is the minimum voltage available
delay time expressed in nanoseconds. at the output corresponding to logic 1.
VOL : This is the maximum voltage available
Figure of merit = at the output corresponding to logic 0.
propagation delay time(ns) × power(mW)
Note: The logic gates are not able to
It is specified in Pico joules. determine logic ‘1’ or logic ‘0’, if voltage lies
A low value of speed-power product is in the intermediate level. Stray electric and
desirable. In a digital circuit, if it is desired magnetic fields may induce unwanted
to have high speed, i.e. low propagation voltages, known as noise, on the connecting
delay, then there is a corresponding wires between logic circuits. This may
cause the voltage at the input to a logic
circuit to drop below VIH or rise above VIL
and may produce undesired operation. The
circuit’s ability to tolerate noise signals is
referred to as the noise immunity, a
quantitative measure of which is called
noise margin. The high-state noise margin
VNH is defined as
VNH = V0H – VIH
For the operation discussed below, we
Any negative noise spike greater than VNH assume that the load gates are not present
appearing on the signal line may cause the and the voltages for logic 0 and 1 are
voltage to drop in the indeterminate range , VCE sat = 0.2V and VCC = 5V respectively.
where an unpredictable operation may
occur. The low-state noise margin VNL is Condition I: At least one input is LOW
defined as The emitter–base junction of T1
VNL = VIL – VOL corresponding to the input in the LOW
state is forward-biased making voltage at
4.2.6 WIRED LOGIC CAPABILITY B1 , VB1 = 0.2 + 0.7 = 0.9V .For base–collector
junction of T1 to be forward-biased, and
Input Transistors Output for T2 and T3 to be conducting, 𝑉𝑉B1 is
A B T1 T2 T3 Y required to be at least 0.6 + 0.5 + 0.5 = 1.6
0 0 Active Cut-off Cut-off 1 V. Hence, T2 and T3 are OFF.
0 1 Active Cut-off Cut-off 1
Since T3 is OFF, therefore Y = VCC .
1 0 Active Cut-off Cut-off 1
Reverse
1 1 active Saturation Saturation 0 Condition II: All inputs are HIGH
The outputs can be connected together to
perform additional logic without any extra The emitter–base junctions of T1 are
hardware. reverse-biased. If we assume that T2 and
T3 are ON, then VB2 = VC1 = 0.8 + 0.8 = 1.6V .
4.3 TRANSISTOR–TRANSISTOR LOGIC (TTL)
Since B1 is connected to VCC (5V) through
Transistor–transistor logic (TTL) is a
class of digital circuits built from bipolar R B1 , the collector-base junction of T1 is
junction transistors (BJT) and resistors. It forward-biased. The transistor T1 is
is called transistor logic because both the operating in the active inverse mode,
logic gating function (e.g., AND) and the
making IC1 flow in the reverse direction.
amplifying function are performed by
transistors. This current flows into the base of T2
driving T2 and T3 into saturation. Therefore,
4.3.1 Operation of TTL NAND Gate Y = 0.2 V.
Note: The speed of the circuit can be
improved by decreasing RC3 which
decreases the time constant ( R C3 × C0 )
with which the output capacitance charges
from 0 to 1 logic level. Such a reduction,
however, would increase dissipation and
would make it more difficult for T3 to V=
C2 V=
B4 VBE3,sat + VCE 2,sat
saturate. = 0.8 + 0.2 = 1.0V
=
Since VO V= CE3,sat 0.2V, the voltage
Inpu Transistors Out
t put across the base-emitter junction of T4
A B T1 T2 T3 T4 Y and diode D equals 1.0–0.2=0.8V, which
0 0 Active Cut- Cut- Saturati 1 means T4 and D are cut-off.
off off on b) If one of the inputs drops to LOW logic
0 1 Active Cut- Cutoff Saturati 1 level, T2 and T3 go to cut-off. The output
off on voltage cannot change instantaneously
1 0 Active Cut- Cut- Saturati 1
(being the voltage across Co) and
off off on because of T2 going to cut-off, the
1 1 Reverse Satura Satura Cut-off 0
voltage at the base of T4 rises driving it
Active
tion tion to saturation.
4.3.3 WIRED-AND
4.3.2 Active Pull-up
When the output of TTL NAND gate is
connected together it works as if both the
outputs are applied to AND gate. Wired-
AND connection must not be used for
totem-pole output circuits because of the
current spike problem. TTL circuits with
open-collector outputs are available which
can be used for wired-AND connections.
4.3.4 OPEN COLLECTOR OUTPUT

In a circuit with open-collector output is
It is possible in TTL gates to hasten the
the collector resistor R C3 of T3 is missing.
charging of output capacitance without
corresponding increase in power The collector terminal C3 is available
dissipation with the help of an output outside the IC and the passive pull-up is to
circuit arrangement referred to as an be connected externally. Naturally, the
active pull-up or totem-pole output. advantages of active pull-up are not
available in this. Gates with open-collector
a) For output Y to be in LOW state, output can be used for wired -AND
transistor T4 and diode D are cut-off. operation.
When the output makes a transition
from LOW to HIGH corresponding to 4.3.5 UNCONNECTED INPUTS
any input going to LOW, transistor T4 If any input of a TTL gate is left
enters saturation and supplies current disconnected (open or floating) the
for the charging of the output capacitor corresponding E–B junction of T1 will not
with a small time constant. Diode D is be forward-biased. Hence, it acts exactly in
used in the circuit to keep T4 in cut-off the same way as if a logical 1 is applied to
that input. Therefore, in TTL ICs, all
when the output is at logic 0.
unconnected inputs are treated as logical
Corresponding to this, T2 and T3 are in 1s. However, the unused inputs should
saturation, therefore,
either be connected to some used input(s) VIH(min) 2 2 2 2 2 2
or returned to VCC through a resistor. VIL(max) 1 0.8 0.8 0.8 0.8 0.8
Noise Margin 0 0.3 0.3 0.3 0.3 0.3
4.3.6 CLAMPING DIODES
4.4 EMITTER-COUPLED LOGIC (ECL)

Emitter-coupled logic (ECL) is the fastest
of all logic families and therefore is used in
applications where very high speed is
essential. High speeds have become
possible in ECL because the transistors are
Clamping diodes are commonly used in all used in difference amplifier configuration,
TTL gates to suppress the ringing caused in which they are never driven into
from the fast voltage transitions found in saturation and thereby the storage time is
TTL. These diodes shown in Fig. clamp the eliminated. Here, rather than switching the
negative undershoot at approximately– transistors from ON to OFF and vice-versa,
0.7V. they are switched between cut-off and
active regions. Propagation delays of less
4.3.7 VARIOUS TTL SERIES than 1 ns per gate have become possible in
TTL Series Prefix Example IC ECL.
Standard TTL 74 7404(hex
INVERTER)
Schottky TTL 74S 74S04(hex
INVERTER)
Low-power 74LS 74LS04(hex
Schottky TTL INVERTER)
Advanced 74AS 74AS04(hex
Schottky TTL INVERTER)
Advanced low- 74ALS 74ALS04(hex
power Schottky INVERTER)
TTL
4.3.8 TTL SERIES CHARACTERISTICS
Performance 74 74S 74L 74 74ALS74F

ratings S AS Basically, ECL is realized using difference
Propagation 9 3 9.5 1.7 4 3 amplifier in which the emitters of the two
delay (ns)
Power 10 20 2 8 1.2 6
transistors are connected and hence it is
dissipation referred to as emitter-coupled logic. A 3-
(mW) input ECL gate is shown in Fig. above which
Speed-power 90 60 19 13. 4.8 18 has three parts:
product(pJ) 6 1. The middle part is the difference
Max.clock rate 35 125 45 200 70 100 amplifier which performs the logic
(MHz) operation.
Fan-out(same 10 20 20 40 20 33 2. Emitter follower are used for d.c. level
series) shifting of the outputs Note that two
Voltage
parameters
output Y1 and Y2 are available in this
VOH(min) 2 2.7 2.7 2.5 2.5 2.5 circuit which are complementary. Y1
corresponds to OR logic and Y2 to NOR
VOL(max) 0 0.5 0.5 0.5 0.5 0.5
logic and hence it is named as an
OR/NOR gate.
3. Additional transistors are used in
parallel to T1 to get the required fan-in.
There is a fundamental difference
between all other logic families
(including MOS logic) and ECL as far as
the supply voltage is concerned. In ECL,
the positive end of the supply is
connected to ground in contrast to
other logic families in which negative
end of the supply is grounded. This is
done to minimize the effect of noise
induced in the power supply and
protection of the gate from an 4.4.3 OPEN-EMITTER OUTPUT
accidental short circuit developing
between the output of a gate and Similar to open-collector output in TTL,
ground. The symbol of an ECL OR/NOR open-emitter outputs are available in ECL
gate is shown in Fig. which is useful for wired-OR applications.
4.4.4 UNCONNECTED INPUTS

4.4.1 FAN OUT
If any input of an ECL gate is left
If all the inputs are LOW, the input unconnected, the corresponding E-B
transistors are cut-off. Therefore the input junction of the input transistor will not be
resistance is very high. On the other hand, conducting. Hence it acts as if a logical 0
if an input is HIGH, the input resistance is level voltage is applied to that input.
that of an emitter follower which is also Therefore, in ECL ICs, all unconnected
high. Therefore, the input impedance is inputs are treated as logical 0s.
always high. The output resistance is either
that of an emitter follower or the forward 4.5 MOS LOGIC
resistance of a diode ( T3 or T4 act as a
diode) which is always low. Because of the MOSFETs have become very popular for
low output impedance and high input logic circuits due to high density of
impedance, the fan-out is large. fabrication and low power dissipation.
When MOS devices are used in logic
4.4.2 WIRED OR LOGIC circuits, there can be circuits in which
either only p or only n-channel devices are
The outputs of two or more ECL gates can used. Such circuits are referred to as PMOS
be connected to obtain additional logic and NMOS logic respectively.
without using additional hardware. The The basic MOS gate is an inverter as shown
wired-OR configurations are shown in Fig. in Fig. 4.25, in which T1 is an enhancement
MOSFET which acts as driver and T2 is an
enhancement MOSFET, which acts as load.
1. In the NOR gate if both inputs are 0,
both transistors T1 and T2 are OFF
( ID1 =ID2 =0 ) hence the output is 𝑉𝑉DD. If
either one or both of the inputs are V(1)
= VDD, the corresponding FETs will be
ON and the output is 0 V.
2. In the NAND gate if either one or both
the inputs are V(0) =0, the
corresponding FETs will be OFF, the
voltage across the load FET will be 0,
Instead of fabricating diffusion resistor for hence the output is VDD . If both inputs
load, which usually occupies an area about are V(1) = VDD, both T1and T2 are ON
20 times that of a MOS device, MOSFET and the output is 0
itself is used as the load. This makes
possible high density of fabrication and 4.6 CMOS LOGIC
therefore MOS logic made large scale
integration possible. A complementary MOSFET (CMOS) is
The logic levels for the MOS circuits are obtained by connecting a p-channel and an
n-channel MOSFET in series, with drains
V (0) =0 tied together and the output is taken at the
V (1) = 𝑉𝑉DD common drain. Input is applied at the
Although the MOS logic circuits are common gate formed by connecting the
identical in configuration to bipolar DCTL, two gates together. In a CMOS, p-channel
the problem of current hogging is not and n-channel enhancement MOS devices
present. are fabricated on the same chip, which
4.5.1 MOSFET NAND and NOR Gates makes its fabrication more complicated
NOR gates can be obtained by using and reduces the packing density. But
multiple drivers in parallel, whereas for because of negligibly small power
NAND gates the drivers are to be connected consumption, CMOS is ideally suited for
in series. battery operated systems.
4.6.1 CMOS INVERTER
NOR Gate NAND Gate

Inputs Output Inputs Output
A B Y A B Y
0 0 VDD 0 0 VDD
0 VDD 0 0 VDD VDD The basic CMOS logic circuit is an inverter
VDD 0 0 VDD 0 VDD shown in Fig. For this circuit the logic levels
VDD VDD 0 VDD VDD 0 are 0 V (logic 0) and VDD (logic 1). When
VIN = VDD , T1 turns ON and T2 turns OFF.
Therefore VO = 0V , and since the
transistors are connected in series the
current ID is very small. On the other hand,
when VIN = 0V , turns OFF and T2 turns ON
giving an output voltage. In either logic
state, T1 or T2 is OFF and the quiescent
power dissipation which is the product of
the OFF leakage current and is very low.
4.6.2 TRANSMISSION GATE
A CMOS transmission gate controlled by

gate voltages C and C� is shown in Fig.
Assume C = 1.
1) IA= V (1) f, then T1 is OFF and T2
conducts in the ohmic region because
there is no voltage applied at the drain.
Therefore, T2 behaves as a small
resistance connecting the output to the
input and B= A= V (1).
2) Similarly, if A= V (0), then T2 is OFF and
T1 conducts, connecting the output to
the input and B=A= V (0). This means
the signal is transmitted from A to B
when C = 1.
In a similar manner, it can be shown
that if C=0, transmission is not possible.
In this gate the control C is binary;
whereas the input at A may be either
digital or analog [the instantaneous
value must lie betweenV(0) andV(1)].
4.7 COMPARISON BETWEEN LOGIC

FAMILIES
GATE QUESTIONS(EC)
Q.1 The output of the 74 series GATE of voltage of is 0.7 V for a transistor in
TTL gates is taken from a BJT in active region and 0.75 V for a
a) totem pole and common transistor in saturation. If the sink
collector configuration current I=1mA and the output is at
b) either totem pole or open logic 0, then current I R will be
collector configuration equal to
c) common base configuration
d) common collector configuration
[GATE -2003]
Q.2 The DTL, TTL, ECL and CMOS family
GATE of digital ICs are compared in
the following 4 columns
(P) (Q) (R) (S)
a)0.65mA b)0.70mA
Fan out is DTL DTL TTL CMOS
Minimum Power c)0.75mA d)1.00 mA
Consumption is TTL CMOS ECL DTL [GATE -2005]
minimum
Propagation delay CMOS ECL TTL TTL Q.5 Both transistors T1 and T2 shown in
is minimum
the figure , have a threshold voltage
The correct column is
of 1 Volts. The device parameters
a) P b) Q
K1 and K 2 of T1 and T2 are,
c) R d) S
[GATE -2003] respectively, 36μA / V 2 and 9μA / V 2
. The output voltage V0 is
Q.3 Given figure is the voltage transfer
characteristic of
a)1 V b)2V
a) an NMOS inverter with c)3 V d)4V
enhancement mode transistor as [GATE -2005]
load
b) an NMOS inverter with depletion
mode transistor as load
c) a CMOS inverter
d) a BJT inverter
[GATE -2004]
Q.4 The transistors used in a portion of
the TTL gate shown in the figure
have a β=100 .The base-emitter
Q.6 In the circuit shown Q.9 For the circuit shown in the fig. P
and Q are the inputs and Y is the
output.
The logic implementation by the

a) =
Y AB + C b) =
Y ( A + B) C circuit is
c) =
Y ( A + B) C d)=
Y AB + C
a) XNOR b) XOR
[GATE -2012] C) NOR d) OR
Q.7 The output (Y) of the circuit shown
in the figure is [GATE-2017]
Q.10 A 2 x 2 ROM array is built with the

help of diodes as shown in the
circuit below. Here W0 and W1 are
signals that select the word lines
and B0 and B1 are signals that are
output of the sense amps based on
the stored data corresponding to the
bit lines during the read operation.
a) A + B + C b) A + B.C + A.C
c) A + B + C d) A + B + C
[GATE-2014]
Q.8 The logic functionality realized by

the circuit shown below is
During the read operation, the

selected word line goes high and the
other word line is in a high
impedance state. As per the
a) OR b) XOR implementation shown in the circuit
c) NAND d)AND diagram above, what are the bits
[GATE-2016] corresponding to Dij (where i = 0 or
1 and j = 0 or 1) stored in the ROM?
1 0 0 1
a)   b)  
0 1 1 0
1 0  1 1
c)   d)  
1 0  0 0
[GATE-2018]
Q.11 The logic function f (X, Y) realized by

the given circuit is
A)NOR b)AND
c)NAND d) XOR
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10
(b) (b) (c) (c) (c) (a) (a) (d) * (a)
11
(d)
EXPLANATIONS
Q.1 (b) =
So, Y C.(A + B)
Q.2 (b) Y =C + ( A + B )
Y= C + A.B
Q.3 (c)
Q.7 (a)
Q.4 (c)
=
I I=C 1mA
(∴ BJT i s in saturation.)
VBE = 0.75
sat
⇒ 0.75 =
I R.1kΩ
I R = 0.75mA
Q.5 (c)
I D1 = I D2
( ) ( )
2 2
K1 VGS1 − Vt= K 2 VGS2 − Vt
⇒ 36 ( 5 − V0 − 1=
) 9 ( V0 − 0 − 1)
2 2
⇒ V0 =
3V This circuit is CMOS
implementation
If the NMOS is connected in series,
then the output expression is
product of each input with
complement to the final product.
So, Y = A.B.C
Q.6 (a) =A+ B+ C
Series combination of n-mos is
equivalent to AND and parallel
combination is equivalent to OR Q.8 (d)
Q.10 (a)
When W0 = VDD , B0 = VDD ; else B0 = 0

When W1 = VDD , B1 = VDD ; else B1 = 0
So, B0 = W0 and B1 = W1
Hence,
Hence, the correct option is (A).
Q.11 (d)
X Y P1 P2 P3 P4 N1 N2 N3 N4 f(X,Y)
0 0 OFF ON ON OFF ON ON OFF OFF 0
0 1 OFF OFF ON ON ON OFF OFF ON 1
1 0 ON ON OFF OFF OFF ON ON OFF 1
1 1 ON OFF OFF ON OFF OFF ON ON 0
f ( X, Y ) =XY + XY =X⊕Y
GATE QUESTIONS(EE)
Q.1 A memory system has a total of 8 Q.4 The TTL circuit shown in the figure
memory chips, each with 12 address lines is fed with the waveform X (also
and 4 data lines. The total size of the shown). All gates have equal
memory system is propagation delay of 10ns. The
a) 16kbytes b) 32 Kbytes output Y of the circuit
c) 48 Kbytes d) 64kbytes
[GATE-2003]
Q.2 A TTL NOT gate circuit is shown in

figure. Assuming 𝑉𝑉𝐵𝐵𝐵𝐵 =0.7 V of both
the transistors, if 𝑉𝑉𝑖𝑖 = 3.0 𝑉𝑉 then the
sates of the two transistors will be
a) b)
a) Q1 ON and Q 2 OFF
b) Q1 reverse ON and Q 2 OFF
c) d)
c) Q1 reverse ON and Q 2 ON
[GATE-2010]
d) Q1 OFF and Q 2 reverse ON
[GATE-2006] Q.5 In the circuit shown below, Q1 has
negligible collector –to –emitter
Q.3 The increasing order of speed of saturation voltage and the diode
data access for the following devices drops negligible voltage across it
is number forward bias. If I𝑉𝑉𝑐𝑐𝑐𝑐 is +5V,X
i. Cache Memory and Y are digital signals with 0 Vas
ii. CD-ROM logic 0 and 𝑉𝑉𝑐𝑐𝑐𝑐 as logic 1, then the
iii. Dynamic RAM Boolena expression for Z is
iv. Processor Registers
v. Magnetic Tape
a) (v),(ii),(iii)(iv),(i)
b) (v)(ii),(iii),(i),(iv)
c) (ii),(i),(iii),(iv),(v)
d) (v),(ii),(i),(iii),(iv)
[GATE-2009]
a) XY b) XY
c) XY d) XY
[GATE-2013]
Q.6 A hysteresis type TTL inverter is

used to realize an oscillator in the
circuit shown in the figure.
If the lower and upper trigger level

voltages are 0.9 and 1.7 V, the
period (in ms), for which output is
LOW, is…….
[GATE-2014-03]
Q.7 The logical gate implemented using

the circuit shown below where, V1
and V2 are inputs (with 0V as digital
0 and 5V as digital 1) and Voutput is
the output, is
a) NOT
b) NOR
c) NAND
d) XOR
[GATE-2017-01]
ANSWER KEY:
1 2 3 4 5 6 7
(a) (c) (b) (a) (b) 0.63 (b)
EXPLANATIONS
Q.1 (a) Q.4 (a)

Total size of the memory =n×D×2A
= 4 × 8 × 212
=128kbits
=16kbyte
Q.2 (c)
When 𝑉𝑉𝑖𝑖 = 3 𝑉𝑉 then 𝑄𝑄1 will be in
reverse active mode i.e reverse ON
and 𝑄𝑄2 wil be ON.
Q.3 (b)
Access time register is very less than
that from a memory access .So
speed of data access is fastest in
case of processor registers.
Second highest is cache memory Q.5 (b)
because its size is small so searching
of data takes less time.
So option (b) is right option
satisfying above two.
Z=XY
Q.6 0.63
Q.7 (b)
GATE QUESTIONS(IN)
Q.1 A CMOS implementation of a logic negligible voltage across it number

gate is shown in the following forward bias. If I Vcc is +5V, X and Y
figure: are digital signals with 0 Vas logic 0
and Vcc as logic 1, then the Boolena
expression for Z is
The Boolean logic function realized

by the circuit is
a) AND b) NAND
c) NOR d) OR a) X Y b) XY
[GATE-2007] c) XY d) XY
[GATE-2013]
Q.2 The diodes in the circuit shown are
ideal. A voltage of 0V represents Q.4 The figure is a logic circuit with
logic 0 and +5V represents logic 1. inputs A and B and output Y. Vss = +
The function Z realized by the 5 V. The circuit is of type
circuit for inputs X and Y is
a) Z=X+Y b) Z=XY
c) Z=X+Y d) Z=XY
[GATE-2009]
Q.3 In the circuit shown below, Q1 has

a) NOR b) AND
negligible collector –to –emitter c) OR d) NAND
saturation voltage & the diode drops [GATE-2014]
ANSWER KEY:
1 2 3 4
(c) (b) (b) (d)
EXPLANATIONS
Q.1 (c)
NOR Gate A .B and this is the Boolean
expression
Q.2 (b)
When any of X or Y is zero, Z = 0 .
For X=Y=1.Z=1
Q.3 (b)
Z=XY
Q.4 (d)
Given circuit is CMOS
implementation of digital function.
CMOS containing two type of
transistant network, generally
upper network containing PMOS
and lower network containing
NMOS. Irrespective of detail
operation of any individual network
or transistors, by inspection we can
find out the output expression. If the
Nmos transistors are connected in
series, then take the products of
their inputs with overall
complement, OR if the pmos
transistor are connected in parallel,
then take the products of their input
switch overall complement. So, Y
5 COMBINATIONAL CIRCUITS
5.1 INTRODUCTION The input variables of a half adder are A &

B. The output variables are the sum and
Digital circuits are classified into 2 types: carry. The truth table for the half adder is:
1) Combinational circuits
2) Sequential circuits
Combinational logic circuit refers to
circuits whose output is strictly depended A B Sum Carry
on the present value of the inputs. As soon 0 0 0 0
as inputs are changed, the information 0 1 1 0
about the previous inputs is lost, that is, 1 0 1 0
combinational logics circuits have no 1 1 0 1
memory. The examples of combinational
logic circuits are adders, subtractors, Solving for Sum & Carry using K-map we get,
multiplexers, demultiplexers, encoders Sum ( S) =∑m(1, 2) =AB + AB =A ⊕ B
and decoders.
=
Carry(C) ∑=
m(3) AB
The implementation of half adder using X–
OR and an AND gates shown below
5.2 ADDERS
In electronics, an adder or summer is a digital

circuit that performs addition of numbers.
In many computers and other kinds of 5.2.2 FULL ADDER
processors, adders are used not only in the
arithmetic logic unit(s), but also in other A full adder adds three one-bit numbers,
parts of the processor, where they are used often written as A, B, and Cin . A&B are the
to calculate addresses, table indices, and bits to be added and Cin is a carry
similar operations. generated from previous addition.
5.2.1 HALF ADDER
The half adder adds two single binary

digits A and B. It has two outputs, sum (S) The input variables of a full adder are A & B
and carry (C). The carry signal represents and Cin . The output variables are the sum
an overflow into the next digit of a and carry. The truth table for the full adder
multi-digit addition. is:
A B Sum Carry
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0 carry. The carryout of one stage is fed
1 0 1 1 directly to the carry-in of the next stage.
1 1 0 1 A number of full adders may be added to
1 1 1 1 the ripple carry adder or ripple carry
Solving for Sum & Carry using K-map we adders of different sizes may be cascaded
in order to accommodate binary vector
=
get, Sum (S) ∑m (1, 2,=
4, 7 ) ABCin + ABCin
strings of larger sizes. For an n-bit parallel
+ ABCin + ABCin = A ⊕ B ⊕ C adder, it requires n computational elements
Carry ( C ) = ∑m ( 3,5, 6, 7 ) (FA). Figure 4 shows an example of a
parallel adder: a 4-bit ripple-carry adder. It
= ABCin + ABCin + ABCin + ABCin is composed of four full adders.
=AB + ACin + BCin
The implementation of full adder using X–
OR, AND & OR gates shown below
5.2.4 CARRY LOOK AHEAD ADDER
In the ripple-carry adder, its limiting factor

is the time it takes to propagate the carry.
The carry look-ahead adder solves this
Note: problem by calculating the carry signals in
• A full adder can be implemented using 2 advance, based on the input signals. The
half adder as result is a reduced carry propagation time.
To be able to understand how the carry
look-ahead adder works, we have to
manipulate the Boolean expression dealing
with the full adder. The Propagate P and
generate G in a full-adder, is given as:
P=i A i ⊕ Bi Carry propagate
G i = A i e Bi Carry generate
Note that both propagate and generate
signals depend only on the input bits and
thus will be valid after one gate delay.
• A half adder can be implemented using The new expressions for the output sum
5 NAND or 5 NOR gates only. and the carryout are given by:
• A full adder can be implemented using 9 S= i Pi ⊕ Ci −1
NAND or 9 NOR gates only. Ci +1 = G i + Pi Ci
These equations show that a carry signal
5.2.3 PARALLEL ADDER
will be generated in two cases:
1) If both bits Ai and Bi are 1
The ripple carry adder is constructed by
2) If either A i or Bi is 1 and the carry-in Ci
cascading full adders blocks in series. One
full adder is responsible for the addition of is1.
two binary digits at any stage of the ripple Let's apply these equations for a 4-bit adder:
C= 1 G 0 + P0 C0
C=
2 G1 + P1C1 = G1 + P1 (G 0 + P0 C0 ) The input variables of a half subtractor are
=G1 + P1G 0 + P1P0 C0 A & B. The output variables are the
difference and borrow. The truth table for
C=
3 G 2 + P2 C2 the half adder is:
=G 2 + P2 G1 + P2 P1G 0 + P2 P1P0 C0 A B Difference Borrow
C=
4 G 3 + P3C3 0 0 0 0
=G 3 + P3G2 + P3 P2G1 + P3P2 P1G 0 + P3P2 P1P0 C0 0 1 1 1
1 0 1 0
1 1 0 0
These expressions show that C2 , C3 and C4
Solving for Sum & Carry using K-map we
do not depend on its previous carry-in. get,
Therefore C4 does not need to wait for C3 Sum ( S) =∑m(1, 2) =AB + AB =A ⊕ B
to propagate. As soon as C0 is computed,
C4 can reach steady state. The same is also =
Carry(C) ∑=
m(1) AB
true for C2 and C3 .The general expression is The implementation of half adder using X–
Ci +1 = G i + Pi G i − 1 + Pi Pi − 1G i − 2 + ....Pi Pi − 1....P2 P1G 0 OR and an AND gates shown below
+ Pi Pi − 1....P1P0 C0 .
5.3.2 FULL SUBTRACTOR
A logic Circuit which is used for subtracting

3 single bit binary numbers is known as
full subtractor.
The input variables of a full subtractor are

A & B and C (borrow input). The output
5.3 SUBTRACTORS variables are the difference & borrow.
The truth table for the full adder is:
Subtractor is the one which used to
subtract two binary numbers and provides A B Difference Borrow
Difference and Borrow as an output. 0 0 0 0
Basically we have two types of subtractor. 0 0 1 1
0 1 0 1
5.3.1 HALF SUBTRACTOR 0 1 1 1
1 0 0 0
A Half Subtractor is used for subtracting
1 0 1 0
one single bit binary number from another
1 1 0 0
single bit binary number.
1 1 1 1
Solving for Difference & Borrow using K-

map we get,
Sum ( S) = ∑m (1, 2, 4, 7 )
= ABC + ABC + ABC + ABC = A ⊕ B ⊕ C
Carry ( C ) = ∑m (1, 2,3, 7 )
= ABC + ABC + AB C + ABC
= AB + AC + BC
The implementation of full subtractor using
X–OR, AND & OR gates shown below
5.4.1 2 x 1 MULTIPLEXER
A 2×1 multiplexer uses one control switch

(S0 ) to connect one of two input data lines
(I0 or I1 ) to a single output (Y).
S0 Y
Note: 0 I0
• A full subtractor can be implemented 1 I1
using 2 half subtractor as
Truth table 2x1 MUX is shown above

=
Y S0 I0 + S0 I1
• A half subtractor can be implemented

using 5 NAND or 5 NOR gates only.
• A full subtractor can be implemented
using 9 NAND or 9 NOR gates only. 5.4.2 4 x 1 MULTIPLEXER
5.4 MULTIPLEXER
A 4 x 1 multiplexer uses 2 control switch
A Multiplexer is a combinational circuit ( S1 &S0 ) to connect one of two input data
that selects one of the 2n input signals lines (I0 , I1 , I2 orI3 ) to a single output (Y).
(I0 , I1 , I 2 ,...I(2n −1) ) to be passed to the single
output line Y depending on the input S1 S0 Y
applied to the select lines (S0 , S1 , S2 , …Sn ). A 0 0 I0
1 1 I1
multiplexer is also called a data selector.
1 0 I2
1 1 I3
From truth table, the output

Y = S1 S2 I0 + S1S0 I1 + S1 S0 I 2 + S1S0 I3
5.5 DEMULTIPLEXER
A multiplexer takes several inputs and

transmits one of them to the output. A
Example: demultiplexer (DEMUX) performs the
Design an 8 x 1 MUX using 4 x 1 & 2 x 1 reverse operation i.e. it takes a single input
MUX. and distributes it over several outputs. A
Solution: demultiplexer is also called as data
distributor.
5.5.1 1 x 4 DEMULTIPLEXER
A 1 x 4 demultiplexer has 1 input, 4 outputs

and 2 select lines. So depending on the
value of select lines the input is transferred
to the corresponding output port.
S1 S0 Y0 Y1 Y2 Y3
0 0 I 0 0 0
Note: 0 1 0 I 0 0
• MUX is called as a universal logic 1 0 0 0 I 0
because all gates can be designed using 1 1 0 0 0 I
MUX.
• A 2 x 1 MUX & 1 NOT gate can be used
From the truth table,
to implement all the Boolean functions
of 2 variables. y 0 = S1 S0 I
• A 3 x 1 MUX can be used to implement y1 = S1S0 I
all the Boolean functions of 2 variables &
y 2 = S1 S0 I
some functions of 3 variables (not all
functions of 3 variables). y 2 = S1S0 I
• A 3 x 1 MUX & 1 NOT gate can be used to
implement all the Boolean functions of 2 5.6 DECODER
variables & three variables.
As its name indicates, a decoder is a circuit
component that decodes an input code.
Given a binary code of n-bits, a decoder will
tell which code is this out of the 2n possible
codes. A decoder is binary to other codes
convertor e.g. a 3 x 8 decoder converts
binary to octal.
5.6.2 3 x 8 DECODER
A 3x8 decoder has 3 inputs & 8 outputs. It

converts a 3 bit binary number into octal.
5.6.1 2 x 4 DECODER
A 2x4 decoder has two inputs & 4 output

lines.
.
E A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
E A B y0 y1 y2 y3 0 x x x 0 0 0 0 0 0 0 0
0 x X 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0
1 1 0 0 0 1 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0
Solving for y 0 , y1 , y 2 , y3 we get, 1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1
y 0 = AB
y1 = AB
y 2 = AB
y3 = AB
Note:
• A 2x4 decoder can be used to implement
half adder & half subtractor circuits. Note:
Sum= Difference= y1 + y 2 A 3x8 decoder can be used to implement
full adder & full subtractor.
Carry = y3
Sum = difference = y1 + y 2 + y 4 + y 7
Borrow = y1
carry = y3 + y5 + y 6 + y 7
Borrow = y1 + y 2 + y3 + y 7
5.7 ENCODER
The encoder is a combinational circuit that

performs the reverse operation of the
decoder. The encoder has a maximum of 2n
inputs and n outputs. An encoder converts
other codes into binary. It generates a
binary output according to the bit set at the
input side.
Note:
If more than 1 input bits can set
simultaneously then a priority encoder
should be used which gives priority to the
highest input among the set input lines &
generates corresponding binary output.
GATE QUESTIONS(EC)
Q.1 In the TTL circuit in the figure, S2 b) all functions of 3 variables but
and S0 are select lines and X 7 andX 0 none of 4 variables
c) all functions of 3 variables and
are input lines. S0 and X 0 are LSBs. some but not all of 4 variables
The output Y is d) all functions of 4 variables
[GATE -2003]
Q.4 The circuit shown in the figure has 4

boxes each described by inputs
P,Q,R and outputs Y,Z with
Y =P⊕Q⊕R
Z = RQ + PR + QP
a) indeterminate
b) A ⊕ B
c) A ⊕ B
( )
d) C A ⊕ B + C ( A ⊕ B )
[GATE -2001]
Q.2 If the input X 3 , X 2 , X1 , X 0 to the

ROM in the figure are 8 4 2 1 BCD
numbers, then the outputs
Y3 , Y2 , Y1 , Y0 are
The circuit acts as a
a) 4 bit adder giving P+Q
b) 4 bit subtractor giving P-Q
c) 4 bit subtractor giving Q-P
d) 4 bit adder giving P+Q+R
[GATE -2003]
Q.5 The circuit shown in the figure
converts
a) gray code numbers

b) 2 4 2 1 BCD numbers
c) excess-3 code numbers
d) none of the above
[EC-GATE -2002]
a) BCD to binary code
Q.3 Without any additional circuitry, b) Binary to excess-3 code
an 8:1 MUX can be used to obtain c) Excess-3 to Gray code
a) some but not all Boolean d) Gray to Binary code
functions of 3 variables [GATE -2003]
Q.6 The Boolean function f implemented Q.9 For the circuit shown in the
in the figure using two input following figure, l0 − l3 are inputs to
multiplexers is the 4:1 multiplexer. R(MSB) and S
are control bits.
a) ABC + ABC b) ABC + ABC

The output Z can be represented by
c) ABC + A BC d) AB C + A B C a) PQ + PQS + QRS
[GATE -2005]
b) PQ + PQR + PQS
Q.7 An I/O peripheral device shown in c) PQR + PQR + PQRS + QRS
the figure below is to be interfaced d) PQR + PQRS + PQRS + QRS
to an 8085 microprocessor. To
[GATE -2008]
select the I/O device in the I/O
address range D4 H-D7 H, its chip
Statement for Linked Answer Q.10 &
select ( CS ) should be connected to Q.11:
the output of the decoder shown in Two products are sold from a vending
the figure machine, which has two push buttons P1
and P2 .When a button is pressed, the price
of the corresponding products is displayed
in 7-segment display.
If no buttons are pressed,’0’ is displayed,
signifying ‘Rs. 0’
If only P1 is pressed, ‘2’ is displayed
,signifying ‘Rs.2’
If only P2 is pressed, ‘5’is displayed,
a)output 7 b)output5
signifying ‘Rs.5’
c)output 2 d)output 0
[GATE -2006] If both P1 and P2 are pressed, ’E’ is
displayed, signifying ‘Error’
Q.8 In the following circuit, X is given by The names of the segments in the 7-
segment display, and the glow of the
display for ‘0’,’2’,’5’ and ‘E’ are shown
below.
Consider
a) X = ABC + ABC + ABC + ABC i) push button pressed /not pressed in
b) X = ABC + ABC + ABC + ABC equivalent to logic 1/0 respectively.
c) X = A B + B C + A C ii) a segment glowing /not glowing in the
display is equivalent to logic 1/0
d) X = AB + BC + AC
respectively
[GATE -2007]
Q.10 If segments a to g are considered as
functions of 𝑃𝑃1 and 𝑃𝑃2 then which of
the following is correct?
a) g = P1 +P2 ,d = c+e
b) g =+P1 P2 , d = c+e
c) g =+
P1 P2 , e =b+c
d) g =+
P1 P2 , e =
b+c
a) F = AND ( P, Q ) b) F = OR ( P, Q )
[GATE -2009]
c) F = XNOR ( P, Q ) d) F = XOR ( P, Q )
Q.11 What are the minimum numbers of [GATE -2011]
NOT gates and 2-input OR gates
required to design the logic of the Q.15 The output Y of a 2-bit comparator
diver for this 7-segment display? is logic 1 whenever the 2- bit input A
a) 3 NOT and 4 OR is greater than the 2-bit input B.
b) 2 NOT and 4 OR The number of combinations for
c) 1 NOT and 3 OR which the output is logic 1, is
d) 2 NOT and 3 OR a)4 b)6
[GATE -2009] c)8 d)10
[GATE -2012]
Q.12 What are the minimum number of
2-to-1 multiplexers required to Q.16 In a half-subtractor circuit with X
generate a 2-input AND gate and a and Y as inputs, the Borrow (M)
2-input Ex-OR gate? and Difference ( N= X − Y )
a)1 and 2 b) 1 and 3 are given by
c)1 and 1 d)2 and 2 a) M = X ⊕ Y, N = XY
[GATE -2009]
b) M= XY, N= X ⊕ Y
Q.13 The Boolean function realized by the c) M= XY, N= X ⊕ Y
logic circuit shown is d) M= XY , N= X ⊕ Y
[GATE-2014]
Q.17 Consider the multiplexer based logic

circuit shown in the figure.
a) F = ∑m(0,1,3,5,9,10,14)
b) F = ∑m(2,3,5, 7,8,12,13)
c) F = ∑m (1, 2, 4,5,11,14,15 ) Which one of the following Boolean
d) F = ∑m ( 2,3,5, 7,8,9,12 ) functions is realized by the circuit?
a) F = WS1 S2
[GATE -2010]
b) F = WS1 + WS2 + S1S2
Q.14 The logic function implemented by c) F = W + S1 + S2
the circuit below is (ground implies d) F = W ⊕ S1 ⊕ S2
a logic “0”)
[GATE-2014]
Q.18 In the circuit shown, W and Y are d)
MSBs of the control inputs. The
output F is given by
[GATE-2014]
a) F = WX + WX + YZ
b) F = WX + WX + YZ
=
c) F WXY + WXY Q.20 An 8-to-1 multiplexer is used to
d)= F (W + X)YZ implement a logical function Y as
[GATE-2014] shown in the figure. The output Y is
given by
Q.19 If X and Y are inputs and the
Difference (D = X ‒Y) and the
Borrow (B) are the outputs, which
one of the following diagrams
implements a half-subtractor?
a)
=
a) Y ABC + ACD
=
b) Y ABC + ABD
=
c) Y ABC + ACD
=
d) Y ABD + ABC
[GATE-2014]
b) Q.21 A 16-bit ripple carry adder is

realized using 16 identical full
adders (FA) as shown in the figure.
The carry-propagation delay of each
FA is 12 ns and the sum-propagation
delay of each FA is 15 ns. The worst
case delay (in ns) of this 16-bit
adder will be ________.
c)
[GATE-2014]
Q.22 A four-variable Boolean function is

realized using 4×1 multiplexers as
shown in the figure.
The minimized expression for
F ( U, V, W, X )
(
a) UV + UV W )
b) ( UV + UV )( WX + WX )
c) ( UV + UV ) W
d) ( UV + UV )( WX + WX )
[GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12 13 14
(b) (b) (c) (b) (d) (a) (b) (a) (a) (b) (d) (a) (d) (d)
15 16 17 18 19 20 21 22
(b) (c) (d) (c) (a) (c) 195 (c)
EXPLANATIONS
Q.1 (b) Q.3 (c)

Floating input is accepted by TTL
logic gate as logic 1 Q.4 (b)
Hence S2 = 1 Y =D =P⊗Q⊗R
Z = Borrow = RQ + PR + QP
Q.5 (d)
Y= A ⊕ B
Q.2 (b)
2 4 2 1
x3 x3 x3 x3 y3 y3 y3 y3
0 0 0 0 0 0 0 0 →0 w=a
0 0 0 1 0 0 0 1 →1 x= a ⊕ b
0 0 1 0 0 0 1 0 →2 y =⊕c x(a + b)
0 0 1 1 0 0 1 1 →3 z = d ⊕ y(a + b + c)
0 1 0 0 0 1 0 0 →4 By substituting given options in the
0 1 0 1 0 1 0 1 →5 Boolean equations of two circuits, it
0 1 1 0 1 1 0 0 →6 shows Gray to binary code
0 1 1 1 1 1 0 1 →7 converter. The input=1010 and
1 0 0 0 1 1 1 0 →8 output =1100. The circuit is
1 0 0 1 1 1 1 1 →9 converting Gray code number to
∴ It is 8 4 2 1 BCD to 2 4 2 1 BCD Binary code number.
Q.6 (a) b = P2 …1(NOT)
f = E.A
c = P1 …1(NOT)
=
E BC + BC
d = 1= c + e
∴ f= ABC + ABC
e= P1 + P2 …1(OR)
A B Cf
f= P1 + P2 …1(OR)
1 0 11
g= P1 + P2 …1(OR)
1 1 01
⇒ g= P1 + P2
Q.7 (b) d = 1= C + e
Q.11 (d)
2-NOTgates
3-OR gates
Q.12 (a)
∴ O/P taken from 5th
Q.8 (a)
Let the output of first MUX is Y
So, Y =AB + AB =A ⊕ B
X =YC + YC =Y ⊕ C =
Y S.I0 + S1I1
So X = A ⊕ B ⊕ C = A.0 + AB
= ABC + ABC + ABC + ABC =AB
AND GATE
Q.9 (a) Similarly EX OR gate required 2
Z= PRS + PQRS + PRS + ( P + Q ) RS MUX of 2 ×1
Mapping above terms in Karnaugh
map Q.13 (d)
F ( A, B, C, D ) = ABC + ABD + ABC + AB(CD)
= ABC(D + D) + AB(C + C)D + ABC(D + D) + ABCD
Placing above minterms in
Karnaugh map,
Q.10 (b)
So, F = ∑m(2,3,5, 7,8,9,12)
a=1
Q.14 (d) Hence, N =
X ⊕ Y and m =
XY
Q.17 (d)
Output of first MUX =

WS1 + WS1 = w ⊕ S1
Let Y= w S⊕ 1
F= P ⊕ Q
Output of second MUX = Ys1 + Ys 2
= Y ⊕ s2
Q.15 (b) = w ⊕S1 + S2
A A B B Y
Q.18 (c)
1 0 1 0
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1 The output of the first MUX
1 0 0 1 1 = W × VCC + WX.VCC
1 0 1 0 0
1 0 1 1 0 WX + WX (∴ VCC = log ic1)
1 1 0 0 1 = W⊕X
1 1 0 1 1 = W⊕X
Let Q
1 1 1 0 1 The output of the second MUX
1 1 1 1 0 = Q.YZ + Q. YZ
= Q.Y(Z + Z)
From the truth table we see that the
number of times ‘Y’ becomes 1 is 6 = Q.Y.1
= Q. Y
Put the value of Q in above
Q.16 (c) expression
Function table for Half –Substractor = (WX + WX).Y
is = WX.Y + WX.Y
X Y Difference Borrow
(N) (M) Q.19 (a)
0 0 0 0 X Y D B
0 1 1 1 0 0 0 0
1 0 1 0 0 1 1 1
1 1 0 0 1 0 1 0
1 01 0 So, last stage carry ( C15 ) will be
So, produced after 16 x12ns = 192ns
D = X ⊕ Y = XY + XY and B = X.Y Second last stage carry ( C14 ) will be
produced after 180 ns.
For last stage sum result ( S15 ) total
delay = 180ns + 15ns = 195ns
So, worst case delay = 195 ns
Q.22 (c)
Q.20 (c)
Y = A BCD + ABCD + AB C
Remaining combinations of the
f1 ( U, V ) = S3S2 I0 + S3S2 I1 + S3S2 I 2 + S3S2 I3
select lines will produce output 0.
= UV.0 + UV.1 + UV.1 + UV.0
= UV + UV
F ( U, V, W, X ) = S1S0 I0 + S1S0 I1 + S1S0 I 2 + S1S0 I3
= WX.f1 + WX.f1 + WX.0 + WX.0

= Wf1 + 0 + 0= W ( UV + UV )
So,=
Y ACD(B + B) + AB C
= ACD + AB C
= AB C + ACD
Q.21 (195)
This is 16-bit ripple carry adder

circuit, in their operation carry
signal is propagating from 1st stage
FA0 to last state FA15, so their
propagation delay is added together
but sum result is not propagating.
We can say that next stage sum
result depends upon previous carry.
GATE QUESTIONS(EE)
Q.1 The output F of the 4-to -1 MUX in figure. The Boolean function
shown in figure is F(A,B,C) implemented is
a) xy+x b) x+y a) F ( A, B, C ) = ∑(1, 2, 4, 6)

c) x+y d) xy+x b) F ( A, B, C ) = ∑(1, 2, 6)
[GATE-2001]
c) F ( A, B, C ) = ∑ ( 2, 4,5, 6 )
Q.2 Figure shows a 4 to 1 MUX to be d) F ( A, B, C ) = ∑ (1,5, 6 )
used to implement the sum S of a 1- [GATE-2006]
bit full adder with input bits P and Q
and the carry input 𝐶𝐶𝑖𝑖𝑖𝑖 . Which of the Q.4 A 3 line to 8 line decoder, with
following combinations of inputs to active low outputs is used to
l0 ,l1 ,l2 and𝑙𝑙3 of the MUX will realize implement a 3-variable Boolean
the sum S? function as shown in the figure
The simplified form of Boolean

function F(A,B,C) implemented in
‘Product of Sum’ form will be
a) ( X + Z ) .( X + Y + Z ) .(Y + Z )
b) ( X + Z ) .( X + Y + Z ) .(Y + Z )
a) l0 =l1 =Cin ;l2 =l3 =Cin
c) ( X + Y + Z ) .( X + Y + Z ) .( X + Y + Z ) .( X + Y + Z )
b) l0 =l1 =Cin ;l2 =l3 =Cin
d) ( X + Y + Z ) .( X + Y + Z ) .( X + Y + Z ) .( X + Y + Z )
c) l0 =l3 =Cin ;l1 =l2 =Cin
[GATE-2008]
d) l0 =l3 =Cin ;l1 =l2 =Cin
[GATE-2003] Q.5 The output Y of a 2-bit comparator
is logic 1 whenever the 2- bit input A
Q.3 A(4×1) MUX is used to implement a is greater than the 2-bit input B.
3–input Boolean function as shown The number of combinations for
which the output is logic 1, is
a) 4 b) 6
c) 8 d) 10 Q.8 A Boolean function
[GATE-2012] f ( A, B, C, D ) = Π (1,5,12,15 ) is to be
implemented using an 8 × 1
Q.6 A 3-bit gray counter is used to multiplexer (A is MSB). The inputs
control the output of the multiplexer ABC are connected to the select
as shown in the figure. The initial
inputs S2S1S0 of the multiplexer
state of the counter is 0002 . The
respectively.
output is pulled high. The output of
the circuit follows the sequence
Which one of the following options

gives the correct inputs to pins 0,
a) I0 ,1,1, I1 , I31,1, I 2 1,2,3,4,5,6,7 in order?
b) I0 ,1, I1 ,1, I 2 ,1, I3 ,1 a) D, 0, D, 0, 0, 0, D, D
c) 1, I0 ,1, I1 , I 2 ,1, I3 ,1 b) D,1, D,1,1,1, D, D
d) I0 , I1 , I 2 , I3 , I0 , I1 , I 2 , I3 c) D,1, D,1,1,1, D, D
[GATE-2014-02] d) D, 0, D, 0, 0, 0D, D
[GATE-2015-02]
Q.7 In the 4 × 1 multiplexer, the output F
is given by F= A ⊕ B . Find the Q.9 Consider the following circuit which
required input I3 I 2 I1 , I0 uses a 2-to-1 multiplexer as shown
in the figure below. The Boolean
expression for output Fin terms of A
and B is
a) A ⊕ B b) A + B
c) A + B d) A ⊕ B
[GATE-2016-01]
a) 1010 b) 0110
c) 1000 d) 1110
[GATE-2015-01]
ANSWER KEY:
1 2 3 4 5 6 7 8 9
(b) (c) (a) (a) (b) (a) (b) (b) (d)
EXPLANATIONS
Q.1 (b)
Q F = ∑ min(1, 2,3)
∴ F=xy+xy+xy
=x+xy=x+y
Q.2 (c)
For a 4:1 mux
Q.3 (a)
F=l0 AB+l1AB+l2 AB+l3 AB
F ( A,B,C ) =ABC+ABC+BC
= ∑(1, 2, 4, 6)
Q.4 (a)
Let us consider active high input
Where sum of full adder is
= A ⊕ B⊕C
=F ∑=(1,3,5, 6 ) ∏M (0, 2, 4, 7)
= ( Y+Z ) . ( X+Z ) . ( X+Y+Z )
Q.5 (b) S0 ( A1 ) and S2 ( A 2 ) will produce the
output and when A 0 ( E ) will be high
A A B B Y
1 0 1 0 then 4 :1MUX will be disabled and
disabled output will be 1.
0 0 0 0 0
0 0 0 1 0 Q.7 (b)
0 0 1 0 0 F = A ⊕ B = AB’ + A’B
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1 Q.8 (b)
1 1 0 1 1 Given max term
1 1 1 0 1 f ( A, B, C, D ) = π (1,5,12,15 )
1 1 1 1 0 so min term
From the truth table we see that the f ( A, B, C, D ) = Σm ( 0, 2,3, 4, 6, 7,8,9,10,11,13,14 )
number of times ‘Y’ becomes 1 is 6
I0 I1 I2 I3 I4 I5 I 6 I 7
Q.6 (a) D(0) 0 2 4 6 8 10 12 14
D(1) 1 3 5 7 9 11 13 15
D 1 D 1 1 1 D D
Q.9 (d)
We can redraw the max circuit as
follows
So the Boolean expression of

F(A, B) =BA + BA =A e B =A ⊕ B
A is mapped to E of 4 :1 MUX it
means when A 0 ( E ) E will be low
then MUX will be enabled and as per
GATE QUESTIONS(IN)
Q.1 A combinational circuit using a 8-to-

1 multiplexer shown in the
following figure. The minimized
expression for the output (Z) is
a) b)
a) C(A+B) b) C(A+B)
c) C+(AB) d) C+AB c) d)
[GATE-2007]
[GATE-2006]
Q.3 A MUX circuit shown in the figure
Q.2 Two square waves of equal period T,
below implements a logic function
but with a time delay τ are applied
F1
to a digital circuit whose truth table
is shown in the following figure.
(
a) X ⊕ Y ⊕ Z ) ( )
b) X ⊕ Y ⊕ Z
c) ( X ⊕ Y ) ⊕ Z d) ( X ⊕ Y ) ⊕ Z
[GATE-2007]
The high and the low level of the Q.4 The output F of the multiplexer
output of the digital circuit are 5V circuit shown below expressed in
and 0V, respectively. Which one of terms of the inputs P,Q and R is
the following figures shows the
correct variation of the average
value of the output voltage as
T
function of τfor0 ≤ t ≤   ?
2
a) F = P ⊕ Q ⊕ R
b) F=PQ+QR+RP
c) F=(P ⊕ Q)R
d) F=(P ⊕ Q)R
[GATE-2008]
Q.5 A 4 to 1 multiplexer to realize a

Boolean function F (X, Y, Z) is shown
in the figure below. The inputs Y
and Z are connected to the selectors of
the MUX (Y is more significant). The
canonical sum-of product expression
for F (X, Y, Z) is
a) ∑m(2,3, 4, 7) b) ∑m(1,3,5, 7)
c) ∑m(0, 2, 4, 6 d)
∑m(2,3,5, 6)
[GATE-2016]
ANSWER KEY:
1 2 3 4 5
(c) (c) (b) (a) (a)
EXPLANATIONS
Q.1 (c)
Y=ABC+ABC+ABC+ABC
(
F1 = ZS + ZS = Z ⊕ S = Z X ⊕ Y )
Z=Y+C
Q.4 (a)
Y=ABC+ABC+ABC+ABC + C
F = PQR + PQR + PQR + PQR
(
=C 1+AB+AB+AB +ABC ) =P(QR+QR)+P(QR+QR)
=C+ABC
= ( C+C ) (C+AB) =C+AB
( )
=P Q ⊕ R + P(Q ⊕ R)
=P⊕Q⊕R
Q.2 (c) Q.5 (a)

When τ = 0X and Y will be same and
F = (x)yz + (o)yz + (x)yz + (1).yz
out-put will be equal to dc of 5V.
= xyz + xyz + yz
T
When τ = X and Y will be (4) (2) (3, 7)
2
complement of each other and F(x, y, z) = ∑m(2,3, 4, 7)
output will be equal to dc 0 When τ
T
increase from 0 to ,O/P will
2
decrease from 5V to 0V linearly.
Q.3 (b)
F0 =XY + XY =X⊕Y
6 SEQUENTIAL CIRCUITS
6.1 INTRODUCTION
asynchronous logic is that it can be faster
In many applications, information than synchronous logic, because the circuit
regarding input values at a certain instant doesn't have to wait for a clock signal to
of time is required at some future time. process inputs. The speed of the device is
Although every digital system is likely to potentially limited only by the propagation
have combinational circuits, most systems delays of the logic gates used.
encountered in practice also include
memory elements, which require that the 6.2 FLIP FLOPS
system be described in terms of sequential
logic. Circuits whose output depends not Basic latch is a feedback connection of two
only on the present input value but also the NOR gates or two NAND gates, which can
past input value are known as sequential store one bit of information. It can be set to
logic circuits. There are two types of 1 using the S input and reset to 0 using the
sequential circuits R input.
Gated latch is a basic latch that includes
input gating and a control input signal. The
latch retains its existing state when the
control input is equal to 0. Its state may be
changed when the control signal is equal to
1. In our discussion we referred to the
control input as the clock. We considered
two types of gated latches:
1. Synchronous: • Gated SR latch uses the S and R inputs
to set the latch to 1 or reset it to 0,
In a synchronous circuit, an electronic respectively.
oscillator called a clock (or clock generator) • Gated D latch uses the D input to force
generates a sequence of repetitive pulses the latch into a state that has the same
called the clock signal which is distributed logic value as the D input.
to all the memory elements in the circuit. A flip-flop is a storage element based
The basic memory element in sequential on the gated latch principle, which can
logic is the flip-flop. The output of each flip- have its output state changed only on
flop only changes when triggered by the the edge of the controlling clock signal.
clock pulse, so changes to the logic signals We considered two types:
throughout the circuit all begin at the • Edge-triggered flip-flop is affected only
same time, at regular intervals, by the input values present when the
synchronized by the clock. active edge of the clock occurs.
• Master-slave flip-flop is built with two
2. Asynchronous: gated latches. The master stage is active
during half of the clock cycle, and the
Asynchronous sequential logic is not slave stage is active during the other
synchronized by a clock signal; the outputs half. The output value of the flip-flop
of the circuit change directly in response to changes on the edge of the clock that
changes in inputs. The advantage of activates the transfer into the slave
stage. Master-slave flip-flops can be 6.2.2 SR NAND LATCH
edge-triggered or level sensitive. If the
master stage is a gated D latch, then it
behaves as an edge-triggered flip-flop. If
the master stage is a gated SR latch,
then the flip-flop is level sensitive (see
problem 7.19).
6.2.1 SR NOR LATCH
S R Qa Qb 6.2.3 SR FLIP FLOP

0 0 0/1 1/0(No
change) It includes two AND gates that provide the
0 1 0 1 desired control. When the control signal
1 0 1 0 clk is equal to 0, the S and R inputs to the
1 1 0 0 latch will be 0, regardless of the values of
signals S and R. Hence the latch will
The circuit is referred to as a basic latch. Its maintain its existing state as long as clk = 0.
behavior is described by the truth table in
Fig.
1. When both inputs, R and S, are equal to Clk S R Qn+1
0 the latch maintains its existing state. 0 x X Qn
This state may be either Qa = 0 and Qb = 1 0 0 Qn
1 0 1 0
1, or Qa =1 and Qb =0, which is indicated 1 1 0 1
in the truth table by stating that the Qa 1 1 1 x
and Q b outputs have values 0/1 and

1/0, respectively. Observe that Qa and
It defines the state of the Q output at time
Qb are complements of each other in
n + 1 , namely, Q n+1 as a function of the
this case.
2. When S=0 and R=1, the latch is set into inputs S, R, and Clk.
a state where Qa = 0 and Qb = 1. 1. When Clk = 0, the latch will remain in
3. When S=1 and R=0, the latch is reset the state it is in at time t, that is, Q n ,
into a state where Qa =1 and Qb = 0. regardless of the values of inputs S and
4. The fourth possibility is to have R = S = R. This is indicated by specifying S = x
1. In this case both Qa and Qb will be 0. and R= x, where x means that the signal
Note: The truth table of NOR latch can be value can be either 0 or 1.
verified by following the statement that for 2. When Clk = 1, the circuit behaves as the
NOR gate whenever any input is 1 output is basic latch. It is set by S = 1 and reset by
zero. R = 1. The last row of the truth table,
where S = R = 1, shows that the state
𝑄𝑄𝑛𝑛+1 is undefined because we don’t
know whether it will be 0 or 1. At this
time both S and R inputs go from 1 to 0,
which causes the oscillatory behavior. If
S = R = 1, this situation will occur as
soon as Clk goes from 0 to 1. To ensure
a meaningful operation of the gated SR
latch, it is essential to avoid the
possibility of having both the S and R
inputs equal to 1 when clk changes
from 0 to 1 Clk D Qn+1
The SR flip flop using NAND gates is 0 x Qn
shown in the figure below 1 0 0
1 1 1
Characteristics table:
D Qn Qn+1
0 0 0
0 1 0
1 0 1
Characteristics table: 1 1 1
Solving for Q n +1 , the characteristics
S R Qn Qn+1
equation for D flip flop is Q n +1 = D
0 0 0 0
0 0 1 1
0 1 0 0 Excitation table:
0 1 1 0
1 0 0 1 Qn Qn+1 D
1 0 1 1 0 0 0
1 1 0 x 0 1 0
1 1 1 x 1 0 1
Solving for Q n +1 , the characteristics 1 1 1
equation for SR flip flop is Q n +1= S + RQ n 6.2.5 JK FLIP FLOP
Excitation table: An excitation table shows The JK flip-flop augments the behavior of
the minimum inputs that are necessary to the SR flip-flop (J=Set, K=Reset) by
generate a particular next state when the interpreting the S = R = 1 condition as a
current state is known. "flip" or “toggle” command. Specifically,
Qn Qn+1 S R 1. The combination J = 1, K = 0 is a
0 0 0 x command to set the flip-flop
2. The combination J = 0, K = 1 is a
0 1 1 0
command to reset the flip-flop
1 0 0 1 3. The combination J = K = 1 is a command
1 1 x 0 to toggle the flip-flop, i.e., change its
output to the logical complement of its
6.2.4 D FLIP FLOP current value.
4. Setting J = K = 0 it will hold the current
It is based on the SR flip flop, but instead of state.
using the S and R inputs separately, it has J K Qn+
just one data input D. If D=1, then S=1 and 1
R = 0, which forces the latch into the state Q 0 0 Qn
= 1. If D = 0, then S = 0 and R=1, which 0 1 0
causes Q = 0. Of course, the changes in state 1 0 1
occur only when Clk = 1. 1 1 Q
n
Characteristics table: 1. By keeping +ve level period of clock less
than propagation delays of the flip-flop
J K Qn Qn+1 i.e. t p < ∆t < T .
0 0 0 0 2. By using master-slave JK flip-flop.
0 0 1 1 3. By using edge triggered flip-flop.
0 1 0 0
0 1 1 0 6.2.7 T FLIP FLOP
1 0 0 1
1 0 1 1 The T flip-flop has one input in addition to
1 1 0 1 the clock. T stands for toggle for the
1 1 1 0 obvious reason. A T flip flop can be
Solving for Q n +1 , the characteristics considered as a JK flip flop with both the
equation for JK flip flop is Q= JQ n + KQ n inputs shorted & named as T input.
n +1
1) If T= 0, then = J K= 0 and the state will
Excitation table:
remain the same i.e. Q n +1 = Q n .
Qn Qn+1 S R 2) If T = 1, then = J K= 1 and the new
0 0 0 x state will be Q n +1 = Q n .
0 1 1 x Therefore, the overall operation of the
1 0 x 1 circuit is that it retains its present state if T
1 1 X 0 = 0, and it reverses its present state if T = 1.
6.2.6 RACE AROUND CONDITION T Qn+1

0 Qn
Consider that the inputs are =J K= 1 and 1 Qn
Q = 1 , and a pulse as shown in Figure is
applied at the clock input. After a time
interval ∆t equal to the propagation delay
through 2 NAND gates in series, the Characteristics table:
outputs will change to Q=0. So now we
have =J K= 1 and Q = O T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
Solving for Q n +1 , the characteristics
After another time interval of ∆t the output equation for JK flip flop is Q=
n +1 TQ n + TQ n
will change back to Q=1. Hence, we
conclude that for the time duration of t p of Excitation table:
the clock pulse, the output will oscillate
between 0 and 1. Hence, at the end of the Qn Qn+1 T
clock pulse, the value of the output is not 0 0 0
certain. This situation is referred to as a 0 1 1
race-around condition. 1 0 1
The race-around condition can be avoided as: 1 1 0
6.2.8 FLIP FLOP CONVERSION
For the conversion of one flip flop to

another, a combinational circuit has to be
designed first. If a JK Flip Flop is required,
the inputs are given to the combinational
circuit and the output of the combinational
circuit is connected to the inputs of the
actual flip flop. Thus, the output of the 6.3 REGISTERS
actual flip flop is the output of the required
flip flop. A flip-flop stores one bit of information.
When a set of n flip-flops is used to store n
bits of information, such as an n-bit
Example: Convert SR flip flop to JK flip number, we refer to these flip-flops as a
flop. register. A common clock is used for each
Solution: SR flip flop can be converted into flip-flop in a register.
JK flip flop by following the procedure
6.3.1 SHIFT REGISTERS
1. Write the characteristics equation
for required flip flop (i.e. for JK flip A register that provides the ability to shift
flop). its contents is called a shift register. A given
number is multiplied by 2 if its bits are
J K Qn Qn+1 shifted one bit position to the left and a 0 is
0 0 0 0 inserted as the new least-significant bit.
0 0 1 1 Similarly, the number is divided by 2 if the
0 1 0 0 bits are shifted one bit-position to the right.
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
2. Now, write the excitation table for
available flip flop (i.e. for SR flip flop). Figure shows a four-bit shift register that is
used to shift its contents one bit bit-
J K Qn Qn+1 S R position to the right. The data bits are
0 0 0 0 0 x loaded into the shift register in a serial
0 0 1 1 x 0 fashion using the Ininput. The contents of
0 1 0 0 0 x each flip-flop are transferred to the next
0 1 1 0 0 1 flip-flop at each positive edge of the clock.
1 0 0 1 1 0 To implement a shift register, it is
1 0 1 1 x 0 necessary to use either edge-triggered or
1 1 0 1 1 0 master-slave flip-flops. The level-sensitive
1 1 1 0 0 1 gated latches are not suitable, because a
change in the value of In would propagate
3. Solving for S & R we get through more than one latch during the
time when the clock is equal to 1.
S = JQ n And R = KQ n
4. Implementation
6.3.2 SERIAL IN SERIAL OUT SHIFT
REGISTER
A basic four-bit shift register can be

constructed using four D flip-flops, as
shown below. The operation of the circuit
is as follows. The register is first cleared, 6.3.4 PARALLEL IN SERIAL OUT SHIFT
forcing all four outputs to zero. The input REGISTER
data is then applied sequentially to the D
input of the first flip-flop on the A four-bit parallel in - serial out shift
left. During each clock pulse, one bit is register is shown below. The circuit uses D
transmitted from left to right. An flip-flops and a combinational circuit for
illustration of the transfer is given in Figure entering data to the register. D0, D1, D2
below, which shows what happens when and D3 are the parallel inputs, where D0 is
the signal values at In during eight the most significant bit and D3 is the least
consecutive clock cycles are 1, 0, 1, 1, 1, 0, significant bit. The control input Shift/Load
0, and 0, assuming that the initial state of is used to select the mode of operation. If
all flip-flops is 0. Shift/Load = 0, then the circuit operates as
a shift register. If Shift/Load = 1, then the
parallel input data are loaded into the
register. In both cases the action takes
place on the positive edge of the clock.
In Q0 Q2 Q3 Q4= out
t0 1 0 0 0 0
t1 0 1 0 0 0
t2 1 0 1 0 0
t3 1 1 0 1 0
t4 1 1 1 0 1
t5 0 1 1 1 0
t6 0 0 1 1 1
t7 0 0 0 1 1
6.3.3 SERIAL IN PARALLEL OUT SHIFT

REGISTER 6.3.5 PARALLEL IN PARALLEL OUT
SHIFT REGISTER
For this kind of register, data bits are
entered serially in the same manner as For parallel in - parallel out shift registers,
discussed in the last section. The all data bits appear on the parallel outputs
difference is the way in which the data bits immediately following the simultaneous
are taken out of the register. Once the data entry of the data bits. The following circuit
are stored, each bit appears on its is a four-bit parallel in - parallel out shift
respective output line, and all bits are register constructed by D flip-flops. The D's
available simultaneously. A construction of are the parallel inputs and the Q's are the
a four-bit serial in-parallel out register is parallel outputs. Once the register is
shown below. clocked, all the data at the D inputs appear
at the corresponding Q outputs
simultaneously.
1. Flip flops are –ve edge triggered & Q is
applied as clock to the next flip flops.
2. Flip flops are +ve edge triggered & Q � is
applied as clock to the next flip flops
6.4 COUNTERS
Counter circuits are used in digital systems

for many purposes. They may count the
number of occurrences of certain events, We are assuming that the purpose of this
generate timing intervals for control of circuit is to count the number of pulses
various tasks in a system, keep track of that occur on the primary input called
time elapsed between specific events, and Clock. Thus the clock input of the first flip-
so on. flop is connected to the Clock line. The
There are 2 types of counters; synchronous other two flip-flops have their clock inputs
& asynchronous. driven by the Q output (because +ve edge
Synchronous counter Asynchronous counter triggering is used) of the preceding flip-
1. All the flip flop are 1. Each flip flop is flop. Therefore, they toggle their state
applied with same clock applied with different whenever the preceding flip-flop changes
clock.
its state from Q=1 to Q=0 (i.e.
2. Faster 2. Slower
3. All counting sequence 3. Only up & down = Q 0= to Q 1 ), which results in a positive
is possible. sequences are possible. edge of the Q signal.
6.4.1 ASYNCHRONOUS COUNTERS
The simplest counter circuits can be built

using T flip-flops because the toggle feature
is naturally suited for the implementation
of the counting operation.
6.4.1.1 UP-COUNTER WITH T FLIP-FLOPS
Figure gives a three-bit counter capable of Figure above shows a timing diagram for
counting from 0 to 7. The clock inputs of the counter.
the three flip-flops are connected in • The value of Q0 toggles once in each
cascade. The T input of each flip-flop is clock cycle. The change takes place at
connected to a constant 1, which means the positive edge of the Clock signal.
that the state of the flip-flop will be • The value of Q1 toggles at the positive
reversed (toggled) at each positive edge of
edge of the Q0 i.e. when Q0 changes
its clock.
Note: The counting sequence of the ripple from 0 to 1.
counter depends on the triggering of flip • The value of Q 2 toggles at the positive
flops and the clock applied to the flip flops. edge of the Q1 i.e. when Q1 changes
The counter will count in UP sequence (0 to from 0 to 1.
7) if
If we look at the values Q 2 Q1Q0 as the 6.4.2 SYNCHRONOUS COUNTERS
count, then the timing diagram indicates
that the counting sequence is 0, 1, 2, 3, 4, 5, The asynchronous counters are simple, but
6, 7, 0, 1, and so on. This circuit has total 8 not very fast. If a counter with a larger
counts hence it is called as a modulo-8 or number of bits is constructed in this
MOD-8 counter. manner, then the delays caused by the
Note: There will be some propagation cascaded clocking scheme may become too
delay through each flip-flop. If 3 flip flops long to meet the desired performance
there will be 3 propagation delays (tpdFF) requirements. We can build a faster counter
so we must apply next clock pulse only by clocking all flip-flops at the same time,
after 3tpdFF delays. If n number of flip flops using the approach described below.
are used the clock must be applied after
ntpdFF delays. 6.4.2.1 UP COUNTER WITH T FLIP-FLOPS
i.e. Tclk ≥ nt pdFF
Therefore the maximum frequency of clock
pulses is
1
f max =
nt pdFF
6.4.1.2 DOWN-COUNTER WITH T FLIP-

FLOPS
A slight modification in circuit of UP

counter will change it into a DOWN
counter. The counter will count in DOWN
sequence (7 to 0) if
1. Flip flops are –ve edge triggered &�� Q is
2. Flip flops are +ve edge triggered & Q is
Figure shows a 3 bit synchronous counter

& the contents of a 3 bit UP-counter for
eight consecutive clock cycles, assuming
that the count is initially 0. Observing the
pattern of bits in each row of the table, it is
apparent that
• Bit Q0 changes on each clock cycle
• Bit Q1 changes only when Q0 = 1.
• Bit Q2 changes only when both Q1 and
Q0 are equal to 1.
In general, for an n-bit up-counter, a given
flip-flop changes its state only when all the
preceding flip-flops are in the state Q = 1.
Therefore, if we use T flip-flops to realize
the counter, then the T inputs are defined as
T0 = 1 The total number of counts of this
T1 = Q0 counter is equal to twice the number of
flip-flops.
T2 = Q0 Q1
T3 = Q0 Q1Q 2
・・・Tn = Q0 Q1・・・Q n −1
Note: If MOD-2 & MOD-5 counters are

cascaded then the resultant counter will be
MOD-10 counter.
6.4.2.2 RING COUNTERS
A ring counter is a type of counter

composed of a type circular shift register.
There are two types of ring counters:
1. A straight ring counter or over back
counter connects the output of the last
flip flop to the first flip flop input and
circulates a single one (or zero) bit
around the ring.
The total number of counts of this

counter is equal to the number of flip-
flops.
2. A twisted ring counter, also called
Johnson counter , the complement of
the output of the last shift register to
the input of the first register and
circulates a stream of one’s followed by
zeros around the ring. For example, in a
4-register counter, with initial register
values of 0000, the repeating pattern is:
0000, 1000, 1100, 1110, 1111, 0111,
0011, 0001, 0000... .
GATE QUESTIONS(EC)
Q.1 The digital block in the figure is = = 40ns =

a) R 10ns,S = 10ns
b) R 10ns,S
realized using two positive edge = = 30ns =
c) R 10ns,S = 10ns
d) R 30ns,S
triggered D-flip-flops. Assume that [GATE -2003]
for t < t 0 , Q1 =
Q2 = 0. The circuit in
the digital block is given by: Q.4 A master–slave flip-flop has the
characteristic that
a) change in the input immediately
reflected in the output
a) b) change in the output occurs
when the state of the master is
affected
c) change in the output occurs
b) when the state of the slave is
affected
d) both the master & the slave
states are affected at the same
c) time
[GATE -2004]
Q.5 Choose the correct one from among

d) the alternatives A,B,C,D after
matching an item from Group 1 with
most appropriate item in Group 2
Group 1
P. Shift register
[GATE -2001]
Q. Counter
R. Decoder
Q.2 A 0 to 6 counter consists of 3 flip
Group 2
flops and a combination circuit of 2
1. Frequency division
input gate(s). The combination
2. Addressing in memory chips
circuit consists of
a) one AND gate 3. Serial to parallel data conversion
a) P-3, Q-2, R-1 b) P-3, Q-1, R-2
b) one OR gate
c) one AND gate and one OR gate c) P-2, Q-1, R-3 d) P-1, Q-2, R-2
d) two AND gates [GATE -2004]
[GATE -2003]
Q.6 In the modulo -6 ripple counter
Q.3 A 4 bit ripple counter and a 4 bit shown in the figure, the output of
synchronous counter are made the 2-input gate is used to clear the
using flip flops having a propagation J-K flip-flops.
delay of 10ns each. If the worst case
delay in the ripple counter and the
synchronous counter be R and S
respectively, then
The 2-input gate is
a)a NAND gate b)a NOR gate =
a) S 0=
C0 0 =
b) S 0=
C0 1
c)an OR gate d)an AND gate
=
c) S 1=
C0 0 d)=S 1=
C0 1
[GATE -2004]
[GATE -2006]
Q.7 The present output Q n of an edge
Q.10 Two D-flip-flops, as shown below,
triggered JK flip-flop is logic 0.If J=1,
are to be connected as a
then Q n +1
synchronous counter that goes
a) cannot be determined through the following Q1Q0
b) will be logic 0
sequence
c) will be logic 1
00 → 01 → 11 → 10 → 00 → … The
d) will race around
[GATE -2005] inputs D0 and D1 respectively
should be connected as
Q.8 The given figure shows a ripple
counter using positive edge
triggered flip-flops. If the present
state of the counter is Q 2 Q1Q0 = 011,
then its next state ( Q 2 Q1Q0 ) will be
a) Q1andQ0 b) Q0 andQ1
c) Q1Q0 andQ1Q0 d) Q1 Q0 andQ1Q0
[GATE -2006]
a)010 b)100 Q.11 The following binary values were

c)111 d)101 applied to the X and Y inputs of the
[GATE -2005] NAND latch shown in the figure in
the sequence indicated below:
Q.9 For the circuit shown in the figure X=0, Y=1;
below, two 4-bit parallel–in serial– X=0, Y=0;
out shift registers loaded with the X=1, Y=1.
data shown are used to feed the data The corresponding stable P,Q
to a full adder. Initially, all the flip- outputs will be
flops are in clear state. After
applying two clock pulses, the
outputs of the full adder should be
a) =
P 1,=
Q 0;=
P 1,=
Q 0;
=
P 1,= = 0,=
Q 0orP Q 1
b) =
P 1,=Q 0;=P 0,=Q 1or
=P 0,= =
Q 1; P 0,=Q 1
c) =
P 1,=Q 0;=P 1,=
Q 1; d)
=
P 1,= = 0,=
Q 0orP Q 1
d) =
P = 0;=
1,Q = 1;=
P 1,Q = 1
P 1,Q
[GATE -2007]
[GATE -2008]
Q.12 For the circuit shown, the counter
state ( Q1Q0 ) following the sequence Q.14 For the circuit shown in the figure, D
has a transition from 0 to 1 after
CLK changes from 1 to 0.Assume
gate delays to be negligible.
a) 00,01,10,11,00…
b) 00,01,10,00,01…
c)00,01,11,00,01…
d)00,10,11,00,10… Which of the following statements is
[GATE -2007] true?
a) Q goes to 1 at the CLK transition
Q.13 For each of the positive edge- and stays at 1.
triggered J-K flip flop used in the b) Q goes to 0 at the CLK transition
following figure, the propagation and stays at 0.
delay is ∆T . c) Q goes to 1 at the CLK transition
and goes to 0 when D goes to 1.
d) Q goes to 0 at the CLK transition
and goes to 1 when D goes to 1.
[GATE -2008]
Q.15 Refer to the NAND and NOR latches

shown in the figure. The inputs (
Which of the following waveforms P1 ,P2 ) for both the latches are first
correctly represents the output at made (0,1) and then ,after a few
Q1? seconds, made (1,1) .The
a) corresponding stable outputs
( Q1 ,Q 2 ) are
b)
a) NAND: First (0,1) then (0,1)

NOR: first (1,0) then (0,0)
c) b) NAND: First (1,0) then (1,0)
NOR: first (1,0) then (1,0)
c) NAND: First (1,0) then (1,0)
NOR: first (1,0) then (0,0) Q.19 The output of a 3 –stage Johnson
d) NAND: First (1,0) then (1,1) NOR: (twisted-ring) counter is fed to a
first (0,1) then (0,1) digital-to-analog (D/A) converter as
[GATE -2009] shown in the figure below. Assume
all states of the counter to be unset
Q.16 What are the counting states initially. The waveform which
(Q1 , Q 2 ) for the counter shown in the represents the D/A converter
figure below? output V0 is
a)11,10,00,11,10, …
b) 01,10,11,00,01 ….
c) 00,11,01,10,00, … a)
d) 01,10,00,01,10, …
[GATE -2009]
Q.17 Assuming that all flip-flops are in

reset conditions initially, the count
b)
sequence observed at Q A in the
circuit shown is
c)
a)0010111… b)0001011…
c)0101111… d)0110100…
[GATE -2010]
d)
Q.18 When the output Y in the circuit
below is “1”, it implies that data has
[GATE -2011]
Q.20 Two D flip-flops are connected as a

a) changed from “0” to “1” synchronous counter that goes
b) changed from “1” to “0” through the following Q BQ A
c) changed in either direction
sequence
d) not changed
[GATE -2011]
00 → 11 → 01 → 10 → 00 → …
The connections to the inputs D A c)
and D B are
=
a) D A Q=
B , DB QA
=
b) D A Q=
A , DB QB
( QA QB + QA QB ) , DB =
c) D A = QA
d)
( QA QB + QA QB ) , DB =
d) D A = QB
[GATE -2011]
Q.21 Consider the given circuit
[GATE -2012]
Q.23 Five JK flip-flops are cascaded to

form the circuit shown in Figure.
Clock pulses at a frequency of 1
In this circuit the race around MHz are applied as shown. The
a) Does not occur frequency (in kHz) of the waveform
b) Occurs when CLK =0 at Q3 is __________.
c) Occurs when CLK =1 and A=B=1
d) Occurs when clk =1 and A=B =0
[GATE -2012]
Q.22 The state transition diagram for the

circuit shown is
[GATE-2014]
Q.24 The digital logic shown in the figure

a) satisfies the given state diagram
when Q1 is connected to input A of
the XOR gate.
b)
1 Suppose the XOR gate is replaced

by an XNOR gate. Which one of the
following options preserves 1the
state diagram?
a) Input A is connected to Q2 B and C, and binary inputs X,Y and
b) Input A is connected to Q2 Z, is shown in the figure.
c) Input A is connected to Q1 and S
is complemented
d) Input A is connected to Q1
[GATE-2014]
Q.25 In the circuit shown, choose the
correct timing diagram of the output
(y) from the given waveforms W1,
W2, W3 and W4.
Which one of the following
statements is correct
a) Transitions from State A are
ambiguously
b) Transitions from State B are
ambiguously
c) Transitions from State C are
ambiguously
d) All of the state transitions are
defined unambiguously.
[GATE-2016]
Q.28 Assume that all the digital gates in

the circuit shown in the figure are
ideal, the resistor R = 10kΩ and the
supply voltage is 5V. The D flip-flops
D1, D 2, D3, D 4, and D5, are initialized
with Iogic values 0,1,0,1 and 0,
respectively. The clock has a 30%
duty cycle.
a) W1 b) W2
c) W3 d) W4
[GATE-2014]
Q.26 The circuit shown in the figure is a
The average power dissipated (in

mW) in the resistor R is
[GATE-2016]
a) Toggle Flip Flop Q.29 For the circuit shown in the figure,
b) JK Flip Flop the delay of the bubbled NAND gate
c) SR Latch is 2 ns and that of the counter is
d) Master-Slave D Flip Flop assumed to be zero. If the clock (clk)
[GATE-2014] frequency is 1 GHz, then the counter
behaves as a
Q.27 The state transition diagram for a
finite state machine with states A,
accurate to two decimal places)
of the voltage at node X, is ___________.
[GATE-2018]
a) mod-5counter b) mod-6 counter

c)mod-7counter d)mod-8 counter
[GATE-2016]
Q.28 A traffic signal cycles from Green to

Yellow, Yellow to Red and Red to
Green. In each cycle, Green is turned
on for 70 seconds. Yellow is turned
on for 5 seconds and the Red is
turned on for 75 seconds. This
traffic light has to be implemented
using a finite state machine (FSM).
The only input to this FSM is a clock
of 5 seconds period. The minimum
number of flip-flops required to
implement this FSM is________.
[GATE-2018]
Q.29 In the circuit shown below, a

positive edge-triggered D flip-flop is
used for sampling input data Din
using clock CK. The XOR gate
outputs 3.3 volts for logic HIGH and
0 volts for logic LOW levels. The
data bit and clock periods are equal
and the value of ∆T / TCK = 0.15 ,
where the parameters ∆T and TCK
are shown in the figure. Assume that
the flip-flop and the XOR gate are
ideal.
If the probability of input data bit (

Din ) transition in each clock period
is 0.3, the average value (in volts,
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12 13 14
(c) (d) (b) (c) (b) (c) (c) (b) (d) (a) (c) (b) (b) (d)
15 16 17 18 19 20 21 22 23 24 25 26 27 28
(c) (a) (d) (a) (a) (d) (a) (d) 62.5 (d) (c) (d) * 5
29
0.8415
EXPLANATIONS
Q.1 (c) Q.6(c)

It is given that clock is positive edge At the end of 6th pulse all states
triggered than only option (a) and should be cleared.
(c) are possible. Out of which only =
CBA 110 = CBX 00X
option (c) gives the required result. Output of desired gate should be
zero as clear is given active low. So
Q.2 (d) given gate should be OR as OR gate
output is zero if both inputs are 0.
Q.7 (c)
Since J = 1 and Q n = 0 So Q n +1 = 1
As even if K = 0 , Q n +1 = 1(set)
And if K = 1 , Q n=
+1 Q=
n 1(toggle)
Q.8 (b)
Q 2 Q1Q0 = 011
Q.3 (b) 1stClk → Q 2 Q1Q0 =
100
Prop. delay of 4 bit ripple counter
Q0 = 1( triggersT1)
R =4 × t pd =40ns
Q1 = 1( triggersT2 )
In synchronous counter all flip-flops
are given clock simultaneously so
S = 10ns Q.9 (d)
A B Ci S C0
Q.4 (c) After 1st CP1 1 0 0 1
After 2nd CP1 1 1 1 1
Q.5 (b)
Q.10 (a) 2 0 0 0 1 1 0
Q1 Q0 D1 (Q0 ) D0 (Q1 ) 3
0 0 0 1 So the sequence is
0 1 1 1 11,10,00,11,10,00 …
1 1 1 0
1 0 0 0 Q.17 (d)
Initially, Q=
A Q= B Q= C 0
Q.11 (c) D=A Q B e Q= C 1, D=B Q= A 0
D= Q= 0c
Q.12 (b)
C B
After one clock pulse,

=
Q A 1,= Q B 0,= QC 0
Q.13 (b)
Time period of waveform of output = D A Q= B e QC 1
at D=B Q= A 1, D= C Q=B 0
Q1 = 2 × 2 × T = 4T After two clock pulse,
Delay time at output =
Q A 1,= Q B 1,= QC 0
Q1 = 2∆T = D A Q= B e QC 0
Note : D= Q= 1, D= Q= 1
i) In case of n flip-flops in such B A C B
case, time period of last output After three clock pulses,

=
Q A 0,= Q B 1,= QC 1
waveform = 2n T
Where =D A Q= B e QC 1
T= Time period for clock pulse D=B Q=A 0, D=C Q=
B 1
ii) Delay time = n∆T After four clock pulse,
Where =Q A 1,= Q B 0,= QC 1
∆T = Propagation dealy
provided by one flip-flop =D A Q= B e QC 0
D=B Q=A 1, D=
C Q=B 0
Q.14 (d) After five clock pulse,
=Q A 0,= Q B 1,= QC 0
Q.15 (c)
=D A Q= B e QC 0
For NAND gates : Inputs [(0,1);(1,1)]
⇒ Output [(1,0);(1,0)] D=B Q=A 0, D=C Q=
B 1
For NOR gates : Inputs [(0,1);(1,1)] After six clock pulse,
⇒ Output [(1,0);(0,0)] =Q A 0,= Q B 0,= QC 1
Therefore, the count sequence
Q.16 (a) observed at Q A is 0110100…
Q.18 (a)
Y=1 ,it is possible only when both
flip-flop outputs are ‘1’ . It means
before applying clock both flip-flop
input should be ‘1’. Before applying
clock output of 1st flip-flop should be
Clock J1 K1 J2 K 2 Q1 Q 2 ‘0’. (Because input of 2nd flip-flop is
0 1 1 1 1 0 0 connected to Q ) and after applying
1 1 1 1 1 1 1 clock output of 1st flip-flop should be
‘1’ . And it depends only upon input
data when it changes from ‘0’ to ‘1’. Q.22 (d)
State table
Q.19 (a) Qt A D Qt + 1
Sequence of Johnson counter is 0 0 1 1
Q 2 Q1 Q0 D 2 D1 D0 V0 0 1 0 0
00 00 0 0 0 1 0 0 0
10 01 0 0 4 1 1 1 1
11 01 1 0 6 From State table
11 11 1 1 7
01 10 1 1 3
00 10 0 1 1
00 00 0 0 0
Q.20 (d) Q.23 (62.5)

Present State Next State Given circuit is a Ripple
QB QA QB QA (Asynchrnous) counter. In
0 0 1 1 Ripple counter, o/p frequency of
1 1 0 1 each flip- flop is half of the
0 1 1 0 input frequency if their all the
1 0 0 0 states are used otherwise o/p
0 0 1 1 frequency of the counter is
Now using excitation table of D flip- input frequency
=
flop mod ulus of the counter
= D A (Q A Q B + Q A Q B ) So, the frequency at
DB = QB Q3 =
input frequency
16
Q.21 (a) 1× 10 6
Hz = 62.5kHz
16
Q.24 (d)
The input of D 2 flip-flop is
D 2 = Q1s + Q1 s(∴ A = Q1 )
The alternate expression for EX-
Qn ext = A.CLK.Q
NOR gate is
= A.CLK + Q
= A⊕B= A⊕B= A⊕B
=
Q next A.CLK + Q So, if the Ex-OR gate is substituted
If CLK=1 and A and B =1 by Ex-NOR gate then input A should
Q next = 1| M  be connected to Q1
Then  Noracearound
Q next =1  D 2 = Q1 s + Q1S= Q1 s + Q1S(∴ A = Q1 )
If CLK =1 and A=B=0
= Q1 S + Q1.S
Q next = Q 
 Noracearound
Q next = Q  Q.25 (c)
Thus race around does not occur in This circuit has used negative edge
the circuit triggered, so output of the D-flip flop
will changed only when CLK signal Let ‘n’ be the number of flip-flops
is going from HIGH to LOW (1 to 0) required.
So,
2n ≥ 30
n ≥ 4.90
Minimum number of required flip-

flops is 5.
This is a synchronous circuit, so

both the flip flops will trigger at the Q.29 0.8415
same time and will respond on
falling edge of the Clock. So, the
correct output (Y) waveform is
associated to w3 waveform.
Q.26 (d)
Latches are used to construct Flip-
Flop. Latches are level triggered,
so if you use two latches in cascaded
with inverted clock, then one latch
will behave as master and another
latch which is having inverted clock  ∆T   ∆T 
will be used as a slave and combined Vavg = p × VHIGH 1 −  + (1 − p ) × VLOW  
it will behave as a flip-flop. So given  TCK 
   TCK 
circuit is implementing Master- Case1 Case2
Slave D flip-flop
Where, p = Probability of input data
Q.27 (c) bit ( Din ) transition in each clock
period
Q.28 5 VHIGH = Output voltage at logic high =
3.3V
VLOW = Output voltage at logic low = 0V
Green is turned ON for 70 seconds ∆T
= 0.15 (Given)
Yellow is turned ON for 5 seconds. TCK
Red is turned ON for 75 seconds = 0.3 × 3.3 (1 − 0.15 ) + (1 − 0.3) × 0 ( 0.15 )
Vavg
Total time to complete one cycle for
all 3 lights = (70 + 5 +75) seconds = Vavg = 0.3 × 3.3 × 0.85 = 0.8415
150 seconds
Time period of available clock = 5
seconds
Number of clock cycles in one

150 seconds
=
complete cycle = 30
5 seconds
GATE QUESTIONS(EE)
Q.1 The frequency of the clock signal a) J=X,K=Y b) J=X,K=Y

applied to the rising edge triggered c) J=Y,K=X d) J=Y,K=X
D flip –flop shown in figure is 10
[GATE-2003]
kHz. The frequency of the signal
available at Q is
Q.4 The digital circuit using two
inverters shown in figure will act as
a) a bistable multi-vibrator
a) 10kHz b) 2.5kHz b) an astable multi-vibrator
c) 20kHz d) 5kHz c) a monostable multi –vibrator
[GATE-2002] d) an oscillator
[GATE-2004]
Q.2 The shift register shown in figure is
initially loaded with the bit pattern Q.5 A digital circuit which compares two
1010. Subsequently the shift
numbers A 3 A 2 A1A 0 ,B3 B2 B1B0 is
register is clocked, and with each
clock pulse the pattern gets shifted shown in figure. To get output Y=0,
by one bit position to the right. With choose one pair of correct input
each shift, the bit at the serial input numbers.
is pushed to the left most position
(msb). After how many clock pulses
will the content of the shift register
become 1010 again?
a) 1010, 1010 b) 0101, 0101

c) 0010, 0010 d) 1010, 1011
a) 3 b) 7 [GATE-2004]
c) 11 d) 15
[GATE-2003] Q.6 The digital circuit shown in figure
generates a modified clock pulse at
Q.3 An X-Y flip flop whose Characteristic output. Choose the correct output
Table is given below is to be waveform from the options given
implemented using a J-K flop below.
This can be done by making
b)
a) b) c)
c) d)
[GATE-2004]
Q.7 The digital circuit shown in the

figure work d)
as.
a) JK flip-flop [GATE-2005]
b) Clocked RS flip-flop
c) T flip-flop Q.9 In the figure as long as X1 =1 and
d) Ring counter
[GATE-2005] X 2 =1, the output Q remains
Q.8 Select the circuit which will produce

the given output Q for the input
signals X1 and X 2 given in the figure
a) at 1 b) at 0
c) at its initial value d) unstable
[GATE-2005]
Q.10 The truth table of monoshot shown

a) in the figures is given in the table
below:
Two monoshots, one positive edge
triggered and other negative edge
triggered, are connected shown n
the figure. The pulse widths of the
two monoshot outputs, 𝑄𝑄1 and 𝑄𝑄2 c) Occurs when CLK =1 and A=B=1
are and 𝑇𝑇𝑂𝑂𝑂𝑂1 and 𝑇𝑇𝑂𝑂𝑂𝑂2 respectivel d) Occurs when clk =1 and A=B =0
[GATE-2012]

circuit shown is
The frequency and the duty cycle of

the signal at 𝑄𝑄1 will respectively be
1 TON1
a) f= ,D=
TON1 +TON2 TON1 +TON2
b) f=
1
,D=
TON2 a)
TON1 +TON2 TON1 +TON2
1 TON1
c) f= ,D=
TON1 TON1 +TON2
1 TON1
d) f= ,D=
TON2 TON1 +TON2
[GATE-2008] b)
Q.11 A two –bit counter circuit is shown

below
c)
If the state 𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 of the counter at

the clock time 𝑡𝑡𝑛𝑛 is “10” then the
state 𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 of the counter at 𝑡𝑡𝑛𝑛 + 3
(after three cycles) will be
a) 00 b) 01 d)
c) 10 d) 11
[GATE-2011]
Q.12 Consider the given circuit
[GATE-2012]
Q.14 The clock frequency applied to the
digital circuit shown in figure below
is 1kHz. If the initial state of the
In this circuit the race around output Q of the flip-flop is ‘0’, then
a) Does not occur the frequency of the output
b) Occurs when CLK =0 waveform Q in kHz is
Q.16 A state diagram of a logic gate which
exhibits a delay in the output is
shown in the figure, where X is the
don't care condition, and Q is the
output representing the state.
a) 0.25 b) 0.5
c) 1 d) 2
[GATE-2013]
Q.15 A JK flip flop can be implemented by

T flip-flops. Identify the correct
implementation. The logic gate represented by the
a) state diagram is
a) XOR b) OR
c) AND d) NAND
[GATE-2014-02]
Q.17 Two monoshot multivibrators, one

positive edge triggered ( M1 ) and
b) another negative edge triggered
( M 2 ) , are connected as shown in
figure
c)
The monoshots M1 and M 2 when

triggered produce pulses of width
T1 and T2 respectively, where
T1 > T2 . The steady state output
d) voltage V0 of the circuit is
a)
[GATE-2014-01] b)
a) 00 b) 01
c) 10 d) 11
[GATE-2015-02]
c) Q.20 The current state Q A Q B of a two JK

flip-flop system is 00. Assume that
the clock rise-time is much smaller
than the delay of the JK flip-flop. The
next state of the system is 5V
d)
[GATE-2014-02]
Q.18 The figure shows a digital circuit
constructed using negative edge
triggered J -K flip flops. Assume a a) 00 b) 01
starting state of Q 2 Q1Q0 = 000 . c) 11 d) 10
This state Q 2 Q1Q0 = 000 will repeat [GATE-2016-01]
after _____ number of cycles of the
clock CLK. Q.21 For the synchronous sequential
circuit shown below, the output Z is
0 for the initial conditions.
Q=
A QBQC Q=
' ' '
A QBQC 100
[GATE-2015-01]
Q.19 In the following sequential circuit,

the initial state (before the first
clock pulse) of the circuit is
Q1Q0 = 00 . The state ( Q1Q0 ) ,
immediately after the 333rd clock The minimum number of clock
pulse is cycles after which the output Z
would again becomes zero is …..
[GATE 2017-02]
Q.22 Which one of the following statements

is true about the digital circuit shown
in the figure?
a) It can be used for dividing the
input frequency by 3.
b) It can be used for dividing the
c) It can be used for dividing the
d) It cannot be reliably used as a
frequency divider due to disjoint
internal cycles.
[GATE 2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12 13 14
(d) (b) (d) (a) (d) (b) (c) (a) (d) (a) (c) (a) (d) (b)
15 16 17 18 19 20 21 22
(b) (d) (c) 6 (b) (c) (6) (b)
EXPLANATIONS
Q.1 (d)
In toggle mode
f 10kHz
f out = in = =5kHz
2 2
Q.2 (b)
Excitation table
Q3 ( t + 1=
) Q0 ( t ) ⊕ Q1 ( t ) ⊕ Q2 ( t )
To make (X-Y) FF using (J-K) FF, (J)

should be ( 𝑌𝑌) and (K) should be (X).
Q.4 (a)
For the both states (0, 1) our system
is stable
∴ It is disable multi vibrator
Q.5 (d)
Q.3 (d) For a 4-input X-NOR gate output will
X-Y truth table J-K truth table be zero if number of 1’s will be odd.
We also know that output of XOR
gate will be ‘1’ it number of 1’s will
be odd.
Q A Q Batt n +3 is ‘1 0’
If the inputs will be same then
output of XOR gate will be 0 so all Q.12 (a)
inputs to XNOR will be zero so
output Y will be ‘1’.
So only in option (d) the inputs are
different so Y will be zero.
Q.6 (b)
Qn ext = A.CLK.Q
=A.CLK+Q
Q next =A.CLK+Q
Q.7 (c) If CLK=1 and A and B =1
Q =1|M 
Then next  Noracearound
Q next=1 
If CLK =1 and A=B=0
Q next =Q 
 Noracearound
Q next =Q 
Thus race around does not occur in
Q.8 (a) the circuit
Q.13 (d)
State table
Qt A D Q t +1
0 0 1 1
0 1 0 0
Q.9 (d) 1 0 0 0
As no combination of ‘Q’ with 1 1 1 1
( X1andX 2 ) =1 output is stable From State table
It always switches its state from ‘1’
to ‘0’ and from ‘0’ to ‘1’.
Q.10 (a)
1 TON1 Q.14 (b)
f= ,D=
TON1 +TON2 TON1 +TON2 =
x ( Q ⊕ Q )( Q e Q )¯
Q.11 (c)
=1.0=1(always)
∵ 𝑋𝑋 = 1 = 𝑇𝑇
⇒ Q always toggles whenever clock
triggers.
Q.16 (d)
True Table
f clk 1kHz
∴ fQ = = = 0.5kHz
2 2
Q.15 (b)
Qn J K Qn+1 T
0 0 0 0 0 If you will observe this true table
0 0 1 0 0 corresponding to state diagram,
0 1 0 1 1 then if any input is 0 output is 1 and
0 1 1 1 1 if all the inputs are one output is
1 0 0 1 0 zero it means it corresponds to
1 0 1 0 1 NAND gate.
1 1 0 1 0
1 1 1 0 1 Q.17 (c)
Analysis:
If you will observe the
combinational circuit output
Given M1 mono-stable multivibrator
expression which is the input for T
flip flop is not matching directly, so generates pulse width T1 .
you should go through the option. If
you will solve the combinational
circuit of option (B) then
T= ( J + Qn ) . ( K + Qn )
= J.K + JQ n + KQ n + Q n Q n
= J.K + JQ n + K.Q n + 0 (Q Q n .Q n = 0 ) M 2 mono-stable multivibrator
= J.K + JQ n + K.Q n generates public width T2
Now, according to consensus
theorem J-K will become redundant
term, so it should be eliminated.
Hence = T JQ n + K.Q n which in
matching with our desired result
and option-(B) is correct answer.
(1) Assume Initially if Q 2 = 1 (high
state), then Q 2 = 0 (low state) Then
output of AND gate is low, M1 (multi ∴ overall modulus = mod – 6 counter
vibrator) it does not generates pulse
Q.19 (b)
width T1 (Because it is positive edge
triggered),
J 0 (Q1 ) K1 (Q0 ) J1 (Q0 ) K 0 (Q1 ) Q1 Q0
(2) Output ( Q 2 ) , after T2 duration, it
- - - - 0 0
is low (comes to stable state then 02 0 1 1 0 0 1
is high, the output of And gate is 1 0 1 0 1 1
high now, then M1 multivibrator 1 0 0 1 1 0
generates pulse width T1 (Because it 0 1 0 1 0 0
positive edge triggered), At this time If is a Johnson (MOD-4) counter.
Q 2 does not generates pulse width Divide 333 by 4, so it will complete
83 cycle and remainder clock is 1, at
T2 (Because it negative edge the completion of cycles output’s in
Triggered) then, at the end of T1 at Q1Q0=00 so, next at 333rd clock
pulse output is at Q1Q0=01
pulse, M 2 multi vibrator generates
T2 pulse width (Because it is Q.20 (c)
negative edge triggered)
(1)
It is given initially Q A Q B = 0
Since it is a synchronous counter,
when clock is applied both flip flop
will change there state
simultaneously based on JK FF state
table
→ [ J A =1, K A =1] , [ Q A =0] → Q A + =1
Then again Q 2 (t) is high at the end [ B =1, K B =1] , [ QB =0] → QB+ =1
J
of T1 pulse So next state (c) Q A + Q B + is 11
Q.21 6
Q.22 (b)
Given:
Overall output wave form
Q.18 (6)
Second 2 flip flops from mod (2n-1)
Johnson counter = mod counter
From the above sequential circuit,
State diagram:
GATE QUESTIONS(IN)
Q.1 Given that the initial state (Q1 Q0 ) is Identify the INCORRECT statement.
00, the counting sequence of the a)01→00 b) 11→01
counter shown in the following c)01→11 d) 01→10
figure is Q1 Q0 = [GATE-2007]
Statement for linked Answer

Questions 4 & 5
Consider the circuit shown below
a) 00-11-01-10-00
b) 00-01-11-10-00
c) 00-11-10-01-00
d) 00-10-01-11-00
[GATE-2006] Q.4 In the above figure, Y can be
expressed as
Q.2 All the logic gates in the circuit
a) Q3 (Q 2 +Q1 ) b) Q3 +Q 2 Q1
shown below have finite
propagation delay. The circuit can c) Q3 (Q 2 + Q1 ) d) Q3 + Q 2 Q1
be used as a clock generator, if [GATE-2008]
Q.5 The above circuit is a

a) Mod-8 Counter
b) Mod -9 Counter
a) X=0 b) X=1 c) Mod -10 Counter
c) X=0 or 1 d) X=Y d) Mod -11 Counter
[GATE-2006] [GATE-2008]
Q.3 A sequential circuit is shown in the Q.6 In the figure shown, the initial state
figure below. Let the state of the of Q is 0. The output is observed
circuit be encoded as Q A , Q B . The after the application of each clock
pulse. The output sequence at Q is
notation X → Y implies that state Y
is reachable from state X in a finite
number of clock transition.
a) 0000…. b) 1010…
c) 1111… d) 1000…
[GATE-2009]
Q.7 The figure below shows a 3- bit

ripple counter, with Q2 as the MSB.
The flip-flops are rising –edge
triggered. The countiong direction is Q.10 The digital circuit shown below uses
two negative edge- triggered D flip-
flops assuming initial condition of
Q1 and Q0 as zero, the output Q1 Q0
of this circuit is
a) Always down
b) always up
c) up or down depending on the
initial state of Q0 only
d) up or down depending on the
initial states of Q 2 ,Q1 and Q0
[GATE-2009 ] a) 00,01,10,11,00…
b) 00,01,11,10,00…
Q.8 Consider the given circuit c) 00,11,10,01,00…
d) 00,01,11,11,00…
[GATE-2013]
Q.11 The number of clock cycles for the

duration of an input pulse is counted
In this circuit the race around using a cascade of N decade counters
a) Does not occur (DC 1 to DC N) as shown in the
b) Occurs when CLK =0 figure. If the clock frequency in
c) Occurs when CLK =1 and A=B=1 mega hertz is f, the resolution and
d) Occurs when clk =1 and A=B =0 range of measurement of input
[GATE-2012] pulse width, both in μ s, are
respectively,
circuit shown is
a) b) 1
a) and
( 2 N − 1) 1
b) and
(10 N − 1)
f f f f
c)
10 N
and
(10 − 1) d) 2 and ( 2 − 1)
N N N
f f f f
[GATE-2015]
c) d)
[GATE-2012]
Q.12 A synchronous counter using two J -
K flip flops that goes through the
sequence of states
Q1Q 2 =00 → 10 → 01 → 11 → 00... is
required. To achieve this, the inputs
to the flip flops are: a) 00 → 11 → 10 → 01 → 00...
b) 00 → 01 → 10 → 11 → 00...
c) 00 → 01 → 11 → 10 → 00...
d) 00 → 10 → 11 → 01 → 00...
[GATE-2018]
a) J1 =Q 2 ,K1 =0;J 2 =Q1 ;K 2 =Q1

b) J1 =1,K1 =1;J 2 =Q1 ;K 2 =Q1
c) J1 =Q 2 ,K1 =Q 2 ;J 2 =1;K 2 =1
d) J1 =Q 2 ,K1 =Q 2 ;J 2 =Q1 ,K 2 =Q1'
[GATE-2016]
Q.13 The two inputs and A and B are

connected to an R-S latch via two
AND gates as shown in the figure. If
A=1 and B=0, the output QQ is
a) 00 b) 10
c) 01 d) 11
Q.14 A 2-bit synchronous counter using

two J-K flip flops is shown. The
expressions for the inputs to the J-K
flip flops are also shown in the
figure. The output sequence of the
counter starting from Q1Q2 = 00 is A
2-bit synchronous counter using
two J-K flip flops is shown. The
expressions for the inputs to the J-K
flip flops are also shown in the
figure. The output sequence of the
counter starting from Q1Q2 = 00 is
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12 13 14
(a) (b) (C) (a) (c) (c) (d) (a) (d) (b) (b) (b) (b) (c)
EXPLANATIONS
Q.1 (a) Q.5 (c)
J0=K0= Q1 and J1=K1=1 Whenever Y=1, then clear input of
all the FFs receives ‘0’ and outputs
So Q1 will change state at each clock
of the counter will be reset. When
edge and Q0 will change its state
count =1010, Y=1 and counter will
when Q1 = 0 So
be reset
Q1Q0 ⇒ 00 − 11 − 01 − 10 − 00 − 11
Q3 Q2 Q1 Q0
Q.2 (b)
1 0 1 0
When X=1, equivalent circuit is
1 1 0 0
1 1 1 0
This circuit act as clock generator. Q.6 (c)

J K(𝑄𝑄� ) Qn+1
Q.3 (c) 1 1 0
Here, TB=QA+QB 1 0 1
TA=QA+QB 1 0 1
And we know that output of T flip-
1
flop= (Q ⊕ T)
So, started with QAQB=01 Q.7 (d)
TA ,TB = 1 Up or down depending on the initial
Then, QAQB=10 states of Q 2 ,Q1 and Q0 .
Now, TB=0 & TA=1
so Q A Q B = 01
So sequence is repeated as 01, 10,01 Q.8 (a)
So it will never reach to 11.
Q.4 (a)
Y= (Q 2 Q3 ) (Q3Q1 )
Q 2 Q3 +Q1Q3 Qn ext =A.CLK.Q
=Q3 (Q1 +Q 2 ) =A.CLK + Q
Q next =A.CLK+Q
If CLK=1 and A and B =1 Range of measurement of input
Q next =1|M  width = T
Then
Q next=1 
 No race around T= (10 N − 1) TCLK
If CLK =1 and A=B=0
T=
(10 N
− 1)
Q next =Q  f
 No race around
Q next =Q  Q.12 (b)
Thus race around does not occur in Present Next Flip-flop
the circuit State State input
Q1 Q2 Q1 Q2 J1 K1 J2 K2
Q.9 (d) 0 0 1 0 1 x 0 x
State table 0 1 1 1 1 x x 0
Qt A D Qt + 1 1 0 0 1 x 1 1 x
0 0 1 1 1 1 0 0 x 1 x 1
0 1 0 0
1 0 0 0 From the column of J1 K1 J2 K2
1 1 1 1 We can say J1 = 1
From State table K1 = 1
And T2 = Q1
K2 = Q1
Q.13 (b)
Q.10 (b) Q.14 (c)

State table Prese Flipflop Next
nt State
State
Q Q J1 K1 J2 K Q1+ Q2
1 2 (Q1 + Q (Q1 + Q (Q1 + Q 2
(Q1 + Q
0 0 0 1 1 1 0 1
0 1 1 1 1 0 1 1
1 0 1 1 0 1 0 0
1 1 1 0 1 1 1 0
Q.11 (b)
→By using J1, k1, Q1 we get Q1+
J2, K2, Q2 we get Q2+ with the

help of state table of JK flipflop
→By observing the table we can say,

the counting pattern of the counter
The Resolution (R) is the smallest is
change that is detectable.
=
∴R
1
= TCLK 00 → 01 → 11 → 10 → 00...
f (MHz)
7 CONVERTERS
7.1 INTRODUCTION Where, Vref is the analog voltage value for

logic 1.
There are two basic type of converters, Note:
digital-to-analog (DACs or D/As) and • The resolution of R-2R ladder type DAC
analog-to-digital (ADCs or A/Ds). Their with the range of output from 0 to V
purpose is fairly straight forward. In the 1
case of DACs, output of DACs is an analog volts is given by n x100
voltage that is a proportion of a reference ( 2 − 1)
voltage; the proportion is based on the • If resolution of a DAC is known, its
digital word applied. In the case of the output for any digital input can be
ADCs, a digital representation of the analog calculated as
voltage that is applied to the ADCs input;
the representation is proportional to a Analog output = resolution × decimal
reference voltage. equivalent of input binary
7.2 DIGITAL TO ANALOG CONVERTER Example: If the reference voltage for 8 bit
ADC is 5 V calculate its resolution.
A digital-to-analog converter or simply DAC Solution:
is a semiconductor device that is used to Vref 5
Re solution = n = = 19.61mV
convert a digital code into an analog signal.
A typical digital-to-analog converter
( 2 − 1) 2 − 1
8
outputs an analog signal, which is

usually voltage or current, which Example: Resolution for DAC is 0.2; find
is proportional to the value of the digital the output voltage for the input 11001.
code provided to its inputs. There are 2 Solution:
Analog output =
types of DACs, which we will study in this
chapter resolution × decimal equivalent of input binary
1. Binary-weighted DAC Analog output= 0.2 × (1× 24 + 1× 23 + 1× 20 )= 5V
2. R-2R ladder DAC
Example: A five-bit D/A converter
7.2.1 RESOLUTION
Produces
VOUT = 0.2 V for a digital input of 00001.
It is defined as the smallest change in the
Find the value of VOUT for an input of
analog output voltage corresponding to
11111.
change in 1 bit of the input (or it is analog
Solution:
value of 1 LSB bit).
Obviously, 0.2 V is the weight of the LSB.
V
Resolution(or step size) = n ref For a digital input of 11111, the value of
( 2 − 1) VOUT will be
step size V= 0.2 (1× 24 + 1× 23 + 1× 22 + 1× 22 + 1× 2=
0
) 6.2V
=
%Resolution ×100% out
Vref
1
= ×100%
( 2 − 1)
n
7.2.2 ACCURACY when connected to ground i.e. b=0 & logic
‘0’ when connected to +5 V i.e. b = 1 × 5.
Accuracy is a comparison of the actual From fig.
output of a DAC with the expected output. I1 + I 2 + I3 + I 4 = IF
It is expressed as a percentage of a full- b0 b b b
scale or maximum output voltage. For ∴ + 1 + 2 + 3 = IF
R R /2 R /4 R /8
example, if a converter has a full- scale
1
output of 10V and the accuracy is ±0.1 %, ∴ I F= (b 0 + 2b1 + 4b 2 + 8b3 )
then the maximum error for any output R
voltage is (10 V)(0.001) =10 mV. Ideally, Now,
the accuracy should be, at most, ±1/2 of R
V0 = −IF R F = − F (b 0 + 2b1 + 4b 2 + 8b3 )
an LSB (resolution). For an 8-bit converter, R
1 LSB is 1/256 = 0.0039 (0.39% of full
scale). The accuracy should be 7.4 R-2R LADDER DAC
approximately ±0.2%
R-2R weighted resistor ladder network
7.2.3 LINEARITY uses only 2 set of resistors R & 2R. If a very
precise DAC is to be build, the values of
A D/A converter is said to be linear, if it resistors should be exactly in R-2R ratio.
gives equal increments in the analog output
for equal increment in the numerical value
of digital input.
7.3 BINARY-WEIGHTED DAC
A D/A converter using binary-weighted

resistors are shown in the figure below. In
the circuit, the op-amp is connected in the
inverting mode. The op-amp can also be The voltage 𝑉𝑉𝑟𝑟 shown in the ladder below
connected in the non-inverting mode. The can be calculated as
circuit diagram represents a 4-digit
converter. Thus, the number of binary
inputs is four.
=Vr resolution × decimal equivalent of digital input
Output voltage V0 of R-2R DAC is

 RF 
V0 =1 +  × Vr
 R 
7.5 ANALOG TO DIGITAL CONVERTERS
The basic function of an A/D converter is to

The switches are denoted by b0, b1, b2, b3 convert an analog value (typically
(MSB) & each of which takes value logic ‘0’ represented by a voltage) into binary bits
that give a “good” approximation to that The analog voltage Vs is applied to one
analog value. Conceptually (if not terminal of a comparator and the output of
physically), this process can be viewed as D/A convertor is applied to other terminal
forming a ratio between the input signal of comparator. When input 𝑉𝑉𝑠𝑠 is greater
and a known reference voltage Vref , and than output of DAC, the AND gate will be
then rounding the result to the nearest n- enabled & clock pulses will be allowed to
bit binary integer the counter which will be counted. When
the output of ADC becomes greater than 𝑉𝑉𝑠𝑠 ,
the clock pulses to the counter will be
7.5.1 RESOLUTION OF ADC stopped & at that point, the counter holds
the digital value corresponding to the
It is defined as the change in the voltage analog voltage.
required for a one bit change in the output Note: For n bit conversion maximum
i.e. resolution is the analog value of 1 LSB number of clock pulses required is 2n − 1 .
bit. For n bit conversion of analog voltage Therefore the maximum conversion
in the range –V/2 to +V/2, the resolution = (2n − 1)Tclock .
time
V
is Resolution = n
2 −1 7.7 SUCCESSIVE APPROXIMATION ADC
The quantization error has a range of ±½
LSB (least significant bit), where A successive-approximation converter is
V composed of a digital-to-analog converter
one LSB = n .
2 −1 (DAC), a single comparator, and some
control logic and registers.
7.5.2 TYPES OF A/D CONVERTERS
1. Counter ADC
2. Successive Approximation ADC
3. Flash type ADC
4. Dual slope ADC
7.6 COUNTER TYPE ADC
Conversion from analog to digital using

counter type ADC involves comparator The logic sets the DAC to zero and starts
where the value of the analog voltage at counting up, setting each following bit until
some point in time is compared with some it reaches the value of the measured input
standard. voltage. The conversion is then finished
and the final number is stored in the
register
1. When the analog voltage to be
measured is present at the input to the
comparator, the system control logic
initially sets all bits to zero. Then the
DAC’s most significant bit (MSB) is set
to 1, which forces the DAC output to 1/2
of full scale (in the case of a 10-V full-
scale system, the DAC outputs 5.0 V).
The comparator then compares the
analog output of the DAC to the input
signal, and if the DAC output is lower introduced by a component value during
than the input signal (the signal is the integrate cycle will be cancelled out
greater than 1/2 full scale), the MSB during the de-integrate phase.
remains set at 1.
2. If the DAC output is higher than the
input signal, the MSB resets to zero.
Next, the second MSB with a weight of
1/4 of full scale turns on (sets to 1) and
forces the output of the DAC to either
3/4 full scale (if the MSB remained at 1)
or 1/4 full scale (if the MSB reset to There are two half cycles, referred to here
zero). The comparator once more as the up slope and the down slope. The
compares the DAC output to the input input signal is integrated during the up
signal and the second bit either remains slope for a fixed time. Then a reference of
on (sets to 1) if the DAC output is lower opposite sign is integrated during the down
than the input signal or resets to zero if slope to return the integrator output to
the DAC output is higher than the input zero.
signal.
3. The third MSB is then compared the
same way and the process continues in
order of descending bit weight until the
LSB is compared. At the end of the
process, the output register contains
the digital code representing the analog
input signal.
The up slope cycle can be described
Note: Successive approximation ADCs are mathematically as follows:
relatively slow because the comparisons −Tup Vin
run serially, and the ADC must pause at Vp = … (1)
each step to set the DAC and wait for its RC
output to settle. A 4 bit Successive Where, Vp is the peak value reached at the
approximation ADC always take four clock integrator output during the up slope, Tup is
pulses for conversion & an n bit Successive the known up slope integration time, Vin is
approximation ADC always take n clock
pulses for conversion. the input signal, and R and C are the
Conversion time= n × Tclock integrator component values.
The down slope can be similarly described
by
7.8 DUAL SLOPE ADC T V
Vp = dn ref … (2)
The dual slope ADC is the most commonly RC
used integrating ADC. A dual-slope ADC Where, Tdn is the unknown time for the
integrates an unknown input voltage (Vin ) down slope, and Vref is the known
for a fixed amount of time (Tup ), then "de-
reference.
integrates" (Tdn ) using a known reference
Equating 1 and 2 and solving for Tdn , the
voltage (Vref ) for a variable amount of time.
The advantage of this architecture over the output of the ADC:
single-slope is that the final conversion −Tup Vin
Tdn = … (3)
result is insensitive to errors in the Vref
component values. That is, any error
It should be noted here that Vin and Vref will
always be of opposite sign (to assure a
return to zero in the integrator), so that Tdn
will always be positive. It can be
immediately seen in Eq. 3that the values of
R and C do not appear inTdn , so that their
values are not critical. This is a result of the
same components having been used for
both the up and down slopes. Similarly, if
the times Tup and Tdn are defined by
counting periods of a single clock, the exact
period of that clock will not affect the
accuracy of the ADC. Restating the output
in terms of the number of periods of the
clock:
− N up Vin
N dn =
Vref
Where, Nup is the fixed number of clock
periods used in the up slope and Ndn is the If the input voltage Vin is 5.1 V then after
number of clock periods required to return comparison at each comparator bits
the integrator output to zero. I5 , I 4 , I3 , I 2 , I1 , I0 will set & the priority
encoder will generate the binary output
Note:
corresponding to highest set bit i.e. I5 &
= 22n × Tclock
Maximum conversion time
the conversion will be 101.
7.9 FLASH TYPE ADC Note: Flash type ADC is fastest of all ADCs.
It is also called the parallel A/D converter. Example: What is the largest value of
This circuit is the simplest to understand. It output voltage from an eight-bit DAC that
is formed of a series of comparators, produces 1.0V for a digital input of
each one comparing the input signal to a 00110010?
unique reference voltage. The comparator
outputs connect to the inputs of a priority Solution:
encoder circuit, which then produces a
binary output. ( 00110010 )2 = ( 50 )10
The following illustration shows a 3-bit 1.0V= K × 50
flash ADC circuit: Therefore,
K = 20 mV
The largest output will occur for an input of
(1111111)2 = ( 255)10
= 20mV × 255
VOUT (max)
= 5.10
GATE QUESTIONS(EC)
Q.1 The number of comparators required Q.5 A 4 –bit D/A converter is connected
in a 3-bit comparator type ADC is to a free-running 3-bit UP counter,
a) 2 b) 3 as shown in the following figure.
c) 7 d) 8 Which of the following waveforms
[GATE -2002] will be observed at VO ?
Q.2 The minimum number of

comparators required to build an 8-
bit flash ADC is
a) 8 b) 63
c) 255 d) 256
[GATE -2003]
Q.3 The circuit shown in the figure is a 4 In the figure shown above, the
bit DAC ground has been shown by the
symbol
a) b)
c) d)
The input bits 0 and 1 are
represented by 0 and 5 V
respectively. The OP AMP is ideal
but all the resistances and the 5 V [GATE -2006]
inputs have a tolerance of ±10% .The
specification (rounded to the nearest Statement for linked Answer Questions
multiple of 5%) for the tolerance of Q.6 & Q.7
the DAC is In the Digital-to-Analog converter circuit
a) ±35% . b) ±20% . shown in the figure below, VR = 10V and
c) ±10% . d) ±5%
R = 10kΩ
[GATE -2003]
Q.4 A digital system is required to

amplify a binary –encoded audio
signal. The user should be able to
control the gain of the amplifier
from a minimum to a maximum in
100 increments. The minimum Q.6 The current is
number of bits required to encode, a) 31.25μA b) 62.5μA
in straight binary is c) 125μA d) 250μA
a) 8 b) 6 [GATE -2007]
c) 5 d) 7
[GATE -2004]
Q.7 The voltage V0 is Q.10 In an N bit flash ADC, the analog
a) −0.781V b) −1.562V voltage is fed simultaneously to
c) −3.125V d) −6.250V 2 N − 1 comparators. The output of
[GATE -2007] the comparators is then encoded to
a binary format using digital circuits.
Statement for linked Answer Questions Assume that the analog voltage
Q.8 & Q.9 source Vin (whose output is being
In the following circuit, the comparator converted to digital format) has a
output is logic “1” if V1 > V2 and is logic “0” source resistance of 75Ω as shown
otherwise. The D/A conversion is done as in the circuit diagram below and the
per the relation input capacitance of each
3 comparator is 8 pF. The input must
VDAC = ∑2n −1 b n Volts, whereb3 ( MSB ) , b 2 , settle to an accuracy of 1/2LSB even
n =0
for a full scale input change for
b1andb 0 (LSB) are the counter outputs. proper conversion. Assume that the
The counter starts from the clear state. time taken by the thermometer to
binary encoder is negligible.
Q.8 The stable reading of the LED

displays is
a) 06 b) 07
c) 12 d) 13
[GATE -2008] If the flash ADC has 8 bit resolution,
which one of the following
Q.9 The magnitude of the error between alternatives is closest to the maxi
VDAC and Vin at steady state in volts mum sampling rate?
a) 1mega samples per second
is
b) 6 mega samples per second
a) 0.2 b) 0.3
c) 64 mega samples per second
c) 0.5 d) 1.0
d) 256 mega samples per second
[GATE -2008]
[GATE-2016]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10
(c) (c) (a) (d) (b) (b) (c) (d) (b) (a)
EXPLANATIONS
Q.1 (c) Q.6 (b)

2 n − 1 = 23 − 1
Q.2 (c)
2n − 1 = 28 − 1 = 255
Q.3 (a)
Last both 2R resistor are in parallel and
 R R R R series with R then after
V0 =
−VR . d 3 + d 2 + d1 + d0  a
 R 2R 4R 8R 
R
⇒ V0 = −VR . [ cons tan t ]
R
Worst case tolerance in
1.1×1.1 Then again similar condition last
=V0 = 35%
0.9 both 2R are in parallel and series
with R similarly after solving
Q.4 (d) equivalent circuit is
2n ≥ 100
∴ n≥7
Q.5 (b)
VR 10
=I = = 1mA
R 10kΩ
D 2 is connected to ground and Q 2 to

D3
I 1×10−3
Then=
i = = 62.5µA
16 16
Q.7 (c) Q.10 (a)
Net current in inverting terminal of
I I 5I The total capacitance = (2n-1) x C =
op-amp = + = (28-1) x 8
4 16 16
5I pF = 2.04 nF
V0 =−R ×
16
10 ×103 × 5 ×1×10−3
= − = −3.125V
16
Q.8 (d)
VDAC = 2−1 b 0 + 2o b1 + 21 b 2 + 22 b3
= 0.5b 0 + b1 + 2b 2 + 4b3 The time constant = RC = 153 ns
Counter output will start from 0000 Setting Time = 5RC = 765 ns
and will increase by 1 at every clock Sampling Rate = 1/Setting Time
pulse. Table for VDAC is shown = 1 M Samples/sec
below
b3 b2 b1 b0 VDAC
0 0 0 0 0
0 0 0 1 0.5
0 0 1 0 1
0 0 1 1 1.5
0 1 0 0 2
0 1 0 1 2.5
0 1 1 0 3
0 1 1 1 3.5
1 0 0 0 4
1 0 0 1 4.5
1 0 1 0 5
1 0 1 1 5.5
1 1 0 0 6
1 1 0 1 6.5
1 1 1 0 7
1 1 1 1 7.5
Counter will increase till Vin > VDAC .

So, when VDAC = 6.5V, the
comparator output will be zero and
the counter will be stable at that
reading. The corresponding reading
of LED display is 13.
Q.9 (b)
Magnitude of the error between
VDAC and Vin at steady state
= 6.5 − 6.2 = 0.3V
GATE QUESTIONS(EE)
Q.1 Among the following four, the b) The counter is not working
slowest ADC (analog-to digital properly
converter) is c) The connection from the counter
a) parallel–comparator (i.e flash) type to DAC is not proper
b) successive approximation type d) The R and 2R resistances are in
c) integrating type interchanged.
d) counting type [GATE-2006]
[GATE-2001]
Q.4 The Octal equivalent of the HEX
Q.2 The voltage comparator shown in number AB.CD is
figure can be used in the analog –to a) 253.314 b) 253.632
digital conversion as. c) 526.314 d) 526.632
[GATE-2007]
Q.5 An 8-bit, unipolar Successive
Approximation Register type ADC is
a) a 1-bit quantizer used to convert 3.5 V to digital
b) a 2-bit quantizer equivalent output. The reference
c) a 4-quntizer voltage is +5 V. The output of the
d) a 8 –bit quantizer ADC, at the end of 3rd clock pulse
[GATE-2004] after the start of conversion, is
a) 1010 0000 b) 1000 0000
Q.3 A student has made a 3-bit binary c) 0000 0001 d) 0000 0011
down counter and connected to the [GATE-2015-01]
R-2R ladder type DAC [Gain=(-
1KΩ/2R) as shown in figure to Q.6 A 2-bit flash Analog to Digital
generate a staircase waveform. The Converter (ADC) is given below. The
output achieved is different as input is 0 ≤ VIN ≤ 3 Volts. The
shown in figure. What could be the expression for the LSB of the output
possible cause of this error? B0 as a Boolean function of X 2 , X1 ,
and X 0 is
a) The resistance values are

incorrect
a) X 0  X 2 ⊕ X1  b) X 0  X 2 ⊕ X1 
c) X 0 [ X 2 ⊕ X1 ] d) X 0 [ X 2 ⊕ X1 ]
[GATE-2016-02]
ANSWER KEY:
1 2 3 4 5 6
(c) (a) (c) (b) (a) (a)
EXPLANATIONS
Q.1 (c) For finding its octal number, we can

add one zero in both extreme and
Q.2 (a) grouping
Even when V1 >V2 the (o/p) ‘ Vo ’ is
high and for the next case (V1 <V2 )
(o/p) is low it is 1 bit quantizer.
Since it has two states which can be ∴ equivalent octal number: 253.6328
represented by 1 bit.
Q.5 (a)
Q.3 (c) The block diagram of SAR type ADC
Initial stage of the counter = (111)2 is as follows
= (7)10
So output will be equal to 7 V.
Next state of counter = (110) 2 = (6)10
So output should be =6V
But output is 3V that means LSB of
counter is connected to MSB of DAC
and MSB of counter is connected to
LSB of DAC.
Similarly next state of counter
= (101) 2 =(5)10 Unipolar means all the voltages will
Input to DAC=(101)2 = (5)10 be +ve i.e. nothing is –ve.
So output =5V The functionality of SAR type DAC is,
When counter goes to (100)2 then it will load a value to output register
input to DAC = (001) 2 =(1)10 with MSB=1 and remaining bit=0,
and it will cross check a logic as
So output =1 V
follows.
So connections are not proper.
If Vin > VDAC ⇒ maintain the loaded
Q.4 (b) bit Vin < VDAC ⇒ clear the loaded
Hex number (AB.CD) bit.
This process continues upto 8
number of clock pulses The output
of
DAC = (Resolution)×(Decimal
equivalent of applied binary).
From the given information
5
Resolution = 8 ; 20mV
2 −1
When SOC is applied on 1st clock
the value located to output register
is ' (10000000 ) 2 = (128 )10
'
then VDAC = 128 × 20mV = 2.56V

So, 3.5 > 2.56 V ⇒ maintain the bit
So at the end of 1st clock pulse the
output is 10000000.
On second clock pulse the value
loaded to output register is in
(10100000 ) 2 = (192 )10 then
VDAC = 195 × 20mV = 3.84V
So 3.5 < 3.84 ⇒ clear the loaded bit
So at the end of 2nd clock pulse
output is (10000000 ) 2
On third clock pulse the value
loaded to output register is
(10100000 ) 2 = (160 )10
then VDAC = 160 × 20mv =3.2V
So 3.5 > 3.2 ⇒ maintain the loaded
bit.
So, at the end of 3rd clock pulse
output is (10100000 ) 2
Q.6 (a)
GATE QUESTIONS(IN)
Common Data for Question Q.1 & Q.2 a) X1 b) X 2

An R-2R ladder type DAC is shown below. If c) X 3 d) X1 +X 2
a switch status is ‘0’, 0V is applied and if a
switch status is ‘1’, 5V is applied to the [GATE-2007]
corresponding terminal of the DAC. Statement for Linked Answer Questions
Q.4 & Q.5
Consider the circuit shown in the following
figure.
Q.1 What is the output voltage (V0) for

the switch status S0 =0,S1 =1,S2 =1? Q.4 The correct input –output
5 15 relationship between Y and (X1 , X 2 )
a) V b) V is
4 4
17.5 22.5 a) Y=X1 +X 2 b) Y=X1X 2
c) V d)
4 4 c) Y=X1 ⊕ X 2 d) Y=X1 ⊕ X 2
[GATE-2006] [GATE-2007]
Q.2 What is the step size of the DAC? Q.5 The D flip-flops are initialized to
a) 0.125 V b) 0.525 V Q1 ,Q 2 ,Q3 =000 After 1 clock cycle,
c) 0.625v d) 0.75V
[GATE-2006] Q1 ,Q 2 ,Q3 is equal to
a) 011 b) 010
Q.3 The circuit shown in the figure c) 100 d) 101
below works as a 2-bit analog to [GATE-2007]
digital converter for 0 ≤ Vin ≤ 3V
Q.6 The inverters in the ring oscillator
circuit shown below are identical. If
the output waveform has a
frequency of 10 MHz, the propagation
delay of each inverter is
a) 5ns b) 10ns
The MSB of the output 𝑌𝑌1 expressed c) 20ns d) 50ns
as a Boolean function of the inputs [GATE-2008]
X1 ,X 2 ,X 3 is given by
Q.7 A 4-bit successive approximation comparator switches from logic 0to
type ADC has a full scale value of 15 logic 1, disabling the clock and
v .The sequence of the states, the enabling the output buffer by
SAR will traverse, for the conversion asserting EOC. Assuming all
of an input of 8.15V is components to be ideal, V ref , DAC
a) output and input to be positive, the
maximum error in conversion of the
analog sample value is:
b)
c)
d)
[GATE-2010]
a) directly proportional to Vref
Q.8 The circuit in the figure represents a
b) inversely proportional to ref V ref
counter-based unipolar ADC. When
c) independent of ref Vref
SOC is asserted the counter is reset
d) directly proportional to clock
and clock is enabled so that the
frequency
counter counts up and the DAC
[GATE-2014]
output grows. When the DAC output
exceeds the input sample value, the
ANSWER KEY:
1 2 3 4 5 6 7 8
(b) (c) (b) (b) (b) (b) (a) (a)
EXPLANATIONS
Q.1 (b)
S2= 1,S1= 1,S0= 0 ⇒ 6 = X2 + (X1 + X2)
15 = X2 ⋅ (X1 + X2) =
∴ O=/ P ste size=
×6 V X2X1
4 The output of right side NOR gate is
Q.2 (c) Y=
X1X2 + X1X2 =
X1 ⊕ X 2
supply voltage 5
Step size= = = 0.625V Q.5 (b)
2n − 1 8
D1 =Q3 , D=
2 Q1 ⊕ Q3 and D3 =Q 2
Q.3 (b) So initially Q1Q 2 Q3 =000 it means
Truth table of ADC is
D1D 2 D3 =010 so, after one clock
X3 X2 X1 Y1 Y0
cycle Q1Q 2 Q3 will be 010
0 0 0 0 0
0 0 1 0 1 Q.6 (b)
0 1 1 1 0 f=
1
1 1 1 1 1 2Nt p
Where N-no. of inverters and tp -
⇒ Y1 =X 2
propagation delay of each , so
t p = 10n sec
Q.4 (d)
The output of NOR gate start from
left side to the right side. Q.7 (a)
The output of first NOR gate By characteristics of SAR- ADC.
= X1 + X2 Q.8 (a)
The output of upper NOR gate in Shoulder, So, the maximum error is
second stage directly proportional to V ref of R-2R
= X1 + (X1 + X2) ladder type DAC
= X1 ⋅ (X1 + X2) =
X1X2
The output of lower NOR gate in
second stage
8 SEMICONDUCTOR MEMORIES
8.1 INTRODUCTION 1. DRAM: Dynamic RAM is a form of

random access memory. DRAM uses a
Modern digital systems require the capacitor to store each bit of data, and
capability of storing and retrieving large the level of charge on each capacitor
amounts of information at high speeds. determines whether that bit is a logical
Memories are circuits or systems that store 1 or 0. However these capacitors do not
digital information in large quantity. This hold their charge indefinitely, and
chapter addresses the analysis and design therefore the data needs to be refreshed
of VLSI memories, commonly known as periodically. As a result of this dynamic
semiconductor memories. Today, memory refreshing, it gains its name of being a
circuits come in different forms including dynamic RAM. DRAM is the form of
SRAM, DRAM, ROM, EPROM, EEPROM, semiconductor memory that is often
Flash, and FRAM. While each form has a used in equipment including personal
different cell design, the basic structure, computers and work stations where it
organization, and access mechanisms are forms the main RAM for the computer.
largely the same. 2. SRAM: Static Random Access Memory.
This form of semiconductor memory
gains its name from the fact that, unlike
DRAM, the data does not need to be
refreshed dynamically. It is able to
support faster read and write times
than DRAM (typically 10 ns against 60
ns for DRAM), and in addition its cycle
time is much shorter because it does
Electronic semiconductor memory not need to pause between accesses.
technology can be split into two main types However it consumes more power, is
or categories, according to the way in less dense and more expensive than
which the memory operates: DRAM. As a result of this it is normally
used for caches, while DRAM is used as
8.2 RAM-RANDOM ACCESS MEMORY the main semiconductor memory
technology.
As the names suggest, the RAM or random
access memory is a form of semiconductor SRAM DRAM
memory technology that is used for reading
1) Consume more 1) Consume less
and writing data in any order as required. power power
It is used for such applications as the 2)Faster 2) Slower
computer or processor memory where 3)Packing density 3) Packing
variables and other stored and are required is low density is high
on a random basis. Data is stored and read 4)Hardware 4) Hardware
many times to and from this type of required is less required is more
memory.
There is a large variety of types of RAM that 8.3 ROM - READ ONLY MEMORY
are available. These arise from the variety
of applications and also the number of A ROM is a form of semiconductor memory
technologies available. technology used where the data is written
once and then not changed. In view of this However it is found that after many
it is used where data needs to be stored years the charge may leak away and the
permanently, even when the power is data may be lost. Nevertheless, this type
removed. As a result, this type of of semiconductor memory used to be
semiconductor memory technology is widely used in applications where a
widely used for storing programs and data form of ROM was required, but where
that must survive when a computer or the data needed to be changed
processor is powered down. For example periodically, as in a development
the BIOS of a computer will be stored in environment, or where quantities were
ROM. low.
As the name implies, data cannot be easily 1. EEPROM: This is an Electrically
written to ROM. Depending on the Erasable Programmable Read Only
technology used in the ROM, writing the Memory. Data can be written to it
data into the ROM initially may require and it can be erased using an
special hardware. Although it is often electrical voltage. This is typically
possible to change the data, this gain applied to an erase pin on the chip.
requires special hardware to erase the data Like other types of PROM, EEPROM
ready for new data to be written in. There retains the contents of the memory
is a large variety of types of ROM are even when the power is turned off.
available. Also like other types of ROM,
1. PROM: This stands for Programmable EEPROM is not as fast as RAM.
Rea Only Memory. It is a semiconductor 2. Flash memory: Flash memory may
memory which can only have data be considered as a development of
written to it once - the data written to it EEPROM technology. Data can be
is permanent. These memories are written to it and it can be erased,
bought in a blank format and they are although only in blocks, but data can
programmed using a special PROM be read on an individual cell basis.
programmer. Typically a PROM will To erase and re-programmed areas
consist of an array of useable links of the chip, programming voltages at
some of which are "blown" during the levels that are available within
programming process to provide the electronic equipment are used. It is
required data pattern. also non-volatile, and this makes it
2. EPROM: This is an Erasable particularly useful. As a result Flash
Programmable Read Only Memory. This memory is widely used in many
form of semiconductor memory can be applications including memory
programmed and then erased at a later cards for digital cameras, mobile
time. This is normally achieved by phones, computer memory sticks
exposing the silicon to ultraviolet light. and many other applications.
To enable this to happen there is a
circular window in the package of the 8.4 PROGRAMMABLE LOGIC DEVICES
EPROM to enable the light to reach the (PLDs)
silicon of the chip. When the PROM is in
use, this window is normally covered by An IC that contains large numbers of gates,
a label, especially when the data may flip-flops, etc. that can be configured by the
need to be preserved for an extended user to perform different functions is called
period. The PROM stores its data as a a Programmable Logic Device (PLD). The
charge on a capacitor. There is a charge internal logic gates and/or connections of
storage capacitor for each cell and this PLDs can be changed/configured by a
can be read repeatedly as required. programming process.
PLDs are typically built with an array of
AND gates (AND-array) and an array of OR
gates (OR-array).
The three fundamental types of PLDs differ
in the placement of programmable
connections in the AND-OR arrays. Figure
shows the locations of the programmable
connections for the three types.
1. The PROM (Programmable Read Only

Memory) has a fixed AND array
(constructed as a decoder) and
programmable connections for the
output OR gates array. The PROM
implements Boolean functions in sum-
of-minterms form.
2. The PAL (Programmable Array Logic)
device has a programmable AND array
and fixed connections for the OR array.
3. The PLA (Programmable Logic Array)
has programmable connections for both
AND and OR arrays. So it is the most
flexible type of PLD.
GATE QUESTIONS(EC)
Q.1 In the circuit shown in the figure, A

is parallel-in, parallel-out 4 bit
register, which loads at the rising
edge of the clock C. The input lines
are connected to a 4 bit bus, W. Its
output acts as the input to a 16×4
ROM whose output is floating when
the enable input E is 0. A partial
table of the contents of the ROM is
as follows:
a)0100-02 FF b)1500-16 FF
c)F900-FAFF d)F800-F9FF
[GATE -2005]
Q.3 There are four chips each of 1024

bytes connected to a 16 big address
bus as shown in the figure below.
RAMs 1,2,3 and 4 respectively are
mapped to address
The clock to the register is shown, a) 0C00H-0FFFH,1C00H-

and the data on the W bus at time t 2 1FFFH,2C00H-2FFFH,3C00H-
is 0110. The data on the bus at time 3FFFH
t 2 is b) 1800H-1FFFH,2800H-
a) 1111 b) 1011 2FFFH,3800H-3FFFH,4800H-
c) 1000 d) 0010 4FFFH
[GATE -2003] c) 0500H-08FFH,1500
H-18FFH,3500H-38FFH,5500H-
Q.2 What memory address range is NOT 58FFH
represented by chip#1 and chip#2 d) 0800H-0BFFH,1800H-
in the figure. A 0 toA15 in this figure 1BFFH,2800H-2BFFH,3800H-
are the address lines and CS means 3BFFH
Chip select. [GATE -2013]
Q.4 A 16kB (=16,384 bit) memory array
is designed as a square with an
aspect ratio of one (number of rows
is equal to the number of columns).
The minimum number of address
lines needed for the row decoder is
…………….. [GATE -2015]
Q.5 In a DRAM,
a) periodic refreshing is not required

b) information is stored in a
capacitor
c) information is stored in a latch
d) both, read and write operations

can be performed simultaneously
[GATE -2017]
ANSWER KEY:
1 2 3 4 5
(c) (d) (d) (7) (b)
EXPLANATIONS
Q.1 (c) =
S1 A= 13 0
When W has data 0110 i.e. 6 in Now the RAM # 1 will be enable
decimal its data value at that add. is when the input of MUX is 1, or the
1010. output of AND gate is 1.
Now 1010 i.e. 10 is acting as add. at So, A10 = 0
time t 2 and data at that moment is
A11 = 1
1000.
A14 = 0
Q.2 (d) A15 = 0
Chip 1
A15 …
… A12 A11A10 A9 A8 A 7 … … A 0
x x x x x x x 0 1 0 0 0 0
x x x x x x x 0 1 1 1 1 1
So, range of RAM # 1 is
Chip2
0800H to 0BFFH
A15 …
… A12 A11A10 A 9 A8 A 7 … … A 0
x x x x x x 1 0 0 0 0 0 Q.4 7
x x x x x x 1 1 1 1 1 1
∴ F800 –F9FF cannot be the Memory size = 16kB = 214 bits
memory range for Chip#1 & No. of address lines = No. of data
Chip#2. lines
2n.2n = 214
Q.3 (d) n=7
Since the range of RAM # 1 is
different in all the four options. So Q.5 (b)
we will check for RAM 1 only and
then the same procedure can be In a DRAM, data is stored in the
followed for RAM 2, 3 and 4. form of charge on capacitor and
So, RAM # 1 will be selected when periodic refreshing is needed to
S0 = 0 restore the charge on capacitor
S1 = 0
=
S0 A= 12 0
GATE QUESTIONS(IN)
Q.1 A 2k×8 bit Ram is interfaced to an 8- Q.4 A 1 Kbyte memory module has to be
bit microprocessor .If the address of interfaced with an 8-bit
the first memory location in the Ram microprocessor that has 16 address
is 0800H, the address of the last lines. The address lines A0 to A9 of
memory location will be the processor are connected to the
a) 1000H b) 0FFFH corresponding address lines of the
c) 4800H d) 47FFH memory module. The active low
[GATE-2008] chip select CS of the memory
module is connected to the y5
Q.2 An 8- bit DAC is interfaced with a output of a 3 to 8 decoder with
microprocessor having 16 address active low outputs. S0, S1, and S2
lines (A0…A15) as shown in the are the input lines to the decoder,
adjoining figure. A possible valid with S2 as the MSB. The decoder has
address for this DAC is one active low EN 1 and one active
high EN2 enable lines as shown
below.
The address range(s) that gets
mapped onto this memory module
is (are)
a)3000H b)4FFFH
c)AFFFH d)C000H
[GATE-2010]
Q.3 An ADC is interfaced with a

microprocessor as shown in the
figure. All signals have been
indicated with typical notations.
Acquisition of one new sample of a) 3000H to 33FFH and E000H to
the analog input signal by the E3FFH
microprocessor involves. b) 1400H to 17FFH
c) 5300H to 53FFH and A300H to
A3FFH
d) 5800H to 5BFFH and D800H to
DBFFH
[GATE-2016]
a) one READ cycle only

b) one WRITE cycle only
c) one WRITE cycle followed by
one READ cycle
d) one READ cycle followed by
one WRITE cycle
[GATE-2015]
ANSWER KEY:
1 2 3 4
(b) (a) (c) (d)
EXPLANATIONS
Q.1 (b) Q.4 (d)

Starting address 0800H, so last → 1kB memory means 10 address
address =0800 +7FF=0FFFH lines A9 to A0
→ Since A15 line is missing it should
Q.2 (a) be taken as don’t care.
To select 2-4 line decoder, A15 = 0 → 5th output of decoder should be
activated means A14 =1,A13 =0,A12 =1
To select the DAC, b 2 should be → A11 = 1 since active high enable
active, i.e., A14 = 0 and A13 = 1 A10 = 0 since active low enable z
Reset all address lines can be either
0 or 1.
So, address can be
001x xxxx xxxx xxxx
Out of four choices this is satisfied
by 3000H only. → If A15 = 0 then the range is 5800
to 5BFF
Q.3 (c) → If A15 = 1 then the range is D800
to DBFF.
9 MICROPROCESSOR
9.1 INTRODUCTION They are used as the low order address

bus as well as the data bus. In executing
A microprocessor is a programmable an instruction, during the earlier part of
digital electronic the cycle, these lines are used as the low
circuit that incorporates the functions order address bus. During the later part
of a central processing unit on a single of the cycle, these lines are used as the
semiconducting integrated circuit. It data bus. (This is also known
can communicate with peripherals multiplexing the bus) However, the low
provide timing signals; direct data flow order address bus can be separated
and perform computing tasks as from these signals by using a latch.
specified by the instructions in
memory. The main features of 8085
are:
1) The 8085 is an 8-bit general purpose
microprocessor capable of addressing
64K of memory.
2) The device has forty pins, requires a +5
V single power supply, and can operate
with a 3– MHz single phase clock.
3) The 8085 A-2 version can operate at
the maximum frequency of 5 MHz.
4) The 8085 is an enhanced version of its
predecessor, the 8080 A; its instruction
set is upward compatible with that of
the 8080A, meaning that the 8085
instruction set includes all the 8080A
instruction plus some additional ones. 3) Control And Status Signals :
5) Operating Voltage of 8085 is+5V. This group of signals includes two
6) 8085 is Accumulator based CPU. ( )
control signals R D &WR , three status
signals (IO/M� , S1 &S0 ) to identify the
9.2 PIN DIAGRAM
nature of the operation and one special
signal (ALE) to indicate the beginning
1) Address Bus:
of the operation. These signals are as
The 8085 has eight signal lines,
follows:
A15 – A8 which are unidirectional and
used as the high order address bus. • ALE - Address Latch Enable: This is a
positive going pulse generated every
2) Multiplexed Address / Data Bus: time the 8085 begins an operation
The signal lines AD7 – AD0 are (machine cycle); it indicates that the
bidirectional, they serve a dual bits on AD7 – AD0 are address bits.
purpose. This signal is used primarily to latch the
low order address from the
multiplexed bus and generate a
separate set of eight address
lines, A7 – A0 .
• ��
𝐑𝐑 𝐃𝐃 -Read: This is a Read control signal 5) Externally Initiated Signals,
(active low). This signal indicates that Including Interrupts:
the selected I/O or memory device is to • INTR (Input) Interrupt Request: This
be read and data are available on the is used as a general purpose interrupt;
data bus. it is similar to the INT signal of the
• ��
𝐖𝐖𝐑𝐑 -Write: This is a Write control 8080A.
signal ��
• 𝐈𝐈𝐈𝐈𝐈𝐈𝐈𝐈 (Output) Interrupt
(active low). This signal indicates that Acknowledge: This is used to
the data on the data bus are to be acknowledge an interrupt.
written into a selected memory or I/O
• RST 7.5, RST 6.5, RST 5.5 (Inputs):
location.
These are used as restart interrupts.
• IO/M: This is a status signal used to • TRAP (Input): This is a non-maskable
differentiate between I/O and memory interrupt and has the highest priority.
operations. When it is high, it indicates • HOLD (Input): This signal indicates that
an I/O operation; when it is low, it a peripheral such as a DMA (Direct
indicates a memory operation. This Memory Access) controller is
signal is combined with �� R D (Read) and requesting the use of the address and
��
WR (Write) to generate I/O and data buses.
memory control signals. • HLDA (Output) Hold Acknowledge:
• 𝐒𝐒𝟏𝟏 &𝐒𝐒𝟎𝟎 : These status signals, similar to This signal acknowledges the HOLD
𝐈𝐈𝐈𝐈/𝐌𝐌� , can identify various operations,
request.
but they are rarely used in small • READY (Input): This signal is used to
systems. (All the operations and their delay the microprocessor Read or
associated status signals are listed in Write cycles until a slow responding
table for reference.) peripheral is ready to send or accept
𝐈𝐈𝐈𝐈/𝐌𝐌� 𝐒𝐒𝟏𝟏 𝐒𝐒𝟎𝟎 Data bus Output data. When this signal goes low, the
0 0 0 Halt microprocessor waits for an integral
0 0 1 Memory WRITE number of clock cycles until it goes
0 1 0 Memory READ high. The RESET is described below,
1 0 1 IO WRITE and others are listed in Table for
1 1 0 IO READ reference.
0 1 1 Opcode Fetch • ��
𝐑𝐑𝐑𝐑𝐑𝐑𝐑𝐑𝐑𝐑𝐑𝐑𝐑𝐑 : When the signal on this pin
Interrupt goes low, the program counter is set to
1 1 1
Acknowledge zero, the buses are tri-stated, and the
4) Power Supply And Clock Frequency: MPU is reset.
The power supply and frequency • RESET OUT: This signal indicates that
signals are as follows: the MPU is being reset. The signal can
• VCC : +5V power supply. be used to reset other devices.
• VSS : Ground Reference. 6) Serial I/O Ports :
• X1, X2: A crystal (or RC, LC network) is The 8085 has two signals to implement
connected at these two pins. The the serial transmission:
frequency is internally divided by two; • SID (Serial Input Data)
therefore, to operate a system at 3 MHz, • SOD (Serial Output Data).
the crystal should have a frequency of 6
MHz. 9.3 INTERNAL ARCHITECTURE OF
• CLK (OUT) – Clock Output: This signal 8085
can be used as the system clock for
other devices.
• PSW stands for Program Status word. It
includes Acc and Flag register. A set of
five flip-flops, one bit registers, serve as
flags. These registers indicate certain
conditions (e.g. overflow, carry) that
arise during arithmetic and logical
operations.
2) Flags:
1) Register in the 8085 :

• There is one 8-bit register known as the The ALU includes five flip-flops, which
accumulator (abbreviated as ACC). It are set or reset after an operation
is used in various arithmetic and logical according to data conditions of the
operations. For example, during the result in the accumulator and other
addition of two 8-bit registers, one of registers. They are called Zero (Z),
the operands must be in the ACC. The Carry (CY), Sign (S), Parity (P), and
other may be either in the memory or Auxiliary Carry (AC) flags; they are
in one of the other registers. listed in Table and their bit positions in
• There are six general purpose 8-bit the flag register are shown in Figure.
registers that can be used by a The most commonly used flags are
programmer for a variety of purposes. Zero, Carry, and Sign. The
These registers are labeled as B, C, D, E, microprocessor uses these flags to test
H and L. They can be used individually data conditions.
(e.g. when operation on 8-bit data is e.g. After an addition of two numbers, if
desired) or in pairs (e.g. when a 16-bit the sum in the accumulator is larger
address is to be stored). When used in than eight bits, the flip-flop used to
pairs, only the combination shown in indicate a carry- called the Carry flag
the table is permitted. The codes (CY)
mentioned in this table are used to 3) Arithmetic and Logic Unit (ALU):
refer to a register pair in an instruction. It is the core of the MPU. It consists of
• PC is a 16-bit register which is used by 1) A binary adder
the 8085 to keep track of the address of 2) A complementer for 1’s complement
the instruction (in the memory) that 3) A shift registers to shift the data to right
has to be executed next. This register is or left.
called the program counter It performs the function of Add,
(abbreviated as PC). The contents of Subtract, AND, OR, XOR (modulo 2
this program counter are automatically addition). Complement, Shift right,
updated by the 8085 during the Shift left, Increment, Decrement, Clear,
execution of an instruction so that at Preset on specific instruction. The size
the end of execution of this instruction of the ALU conforms to the word length
it points to the address of the next of the MPU. i.e. 8 bit MPU will have 8 bit
instruction in the memory. ALU. For example, if an Add operation
• There is another 16-bit register, known is to be done, one operand (8-bit data
as the stack pointer (abbreviated as word) is kept in temporary register and
SP). It is used by the programmer to added to another operand (8-bit data
maintain a stack in the memory. word) in the Accumulator register and
the result placed in the Accumulator
after the add operation replacing the f) Reset.
original operand. 2) Timing: Timing signals coordinate the
Note: An operand is defined as the functioning of the systems. Timing
number or character which is to be the signals originate from a pulse
subject of an arithmetic operation. generator. The pulses have fixed ON
If y = a + b, a, b are operands. time, a 1 and OFF time, a0. Total
duration of a 1 and 0 is a clock cycle and
There is another important register in
all events start at the beginning of a
ALU called Status Register also called
clock cycle. Most events occupy a single
CCR (Condition Code Register). It is also
clock cycle. There are two types of
called flags and they are a group of FFs
timing signal, synchronous timing and
which can be set and reset as per the
asynchronous timing.
last arithmetic or logic operation.
4) Instruction Register (IR): 9.4 ADDRESSING MODES
It functions on the instruction cycle of Addressing mode indicates a way of
fetch/execute. An instruction is first locating data or operands. Depending
fetched from the memory through the upon the data types used in the
data bus and stored in the instruction instruction and the memory addressing
register. It is then decoded by the modes, any instruction may belong to
internal decoder and fed to the control one or more addressing modes or some
logic for execution. The Length of the instruction may not belong to any of the
instruction register is generally the addressing modes. Thus the addressing
same as data word. The first word of modes describe the types of operands
the instruction is the operation code for and the way they are accessed for
that instruction. The instruction of the executing an instruction. Here, we will
microprocessor may vary from 8 to present the addressing modes of the
200. This is decided by the instructions depending upon their
manufacturer and is called the types.
Instruction Set.
9.4.1 DIRECT ADDRESSING
5) Timing and Control Unit:
The control unit is the nerve centre of In this mode, the address of the open
the MPU. It coordinates and and is explicitly specified within the
controls all hardware operations i.e. instruction itself. All such instructions
of the peripheral devices such as I/O and are three bytes long as shown in the
CPU itself. The fetch decode execute figure above. Examples of direct
instruction sequence is fundamental to addressing are: LDA (Load ACC) and
MPU’s operation. The control signals STA (Store ACC).
are of two types Example: It is desired to transfer the contents
1) Command :The command signals are of
a) Memory read and writes by which data memory location 08A2 H to memory
is put on the data bus or written into location 12FA H. Assuming that the
the memory’s specified location. symbolic addresses of these locations
b) I/O read and write and are HERE and THERE respectively, we
acknowledgement. may use the following sequence of
c) Interrupt Request and instructions to transfer the data.
acknowledgement. Solution: LDA HERE; Get contents of HERE
d) Transferring the control of the bus, bus into ACC.
request (BR) and bus grant (BG). STA THERE; Transfer contents of ACC
e) Clock. to THERE.
The first of these two instructions, Instruction Set the MOV and ADD,
when executed, will cause the contents besides others, can be used in register
of HERE (08A2) to be brought to indirect addressing mode. These
ACC. Then, the execution of the second instructions fit in a single-byte.
instruction will cause the contents of
the ACC to be transferred to memory Example: The contents of register pair HL
location THERE (12FA) refer to a certain memory location.
The contents of these memory
9.4.2 REGISTER ADDRESSING locations are to be added to the
contents of register B and the sum
When the operands for any operation stored in memory location OAFF. The
are in the general purpose registers, following sequence of instruction
only the registers need to be specified performs this task. We have assumed
as the address of the operands. Such that the symbolic address of location
instructions are said to use the register OAFF is X.
addressing mode. These are one-byte Solution: MOV A, M;
instructions. For example, the MOV Move contents of memory location
and ADD instructions permit register pointed by H-L
addressing. To the ACC
Example: It is desired to add the contents of ADD B;
register B to the contents of register C Add contents of register B to ACC
and transfer the result into register D. STAX; Store the sum in memory location X.
The following sequence of instructions Note that the first instruction uses
can be used to perform this task. register indirect addressing, the next
Solution: MOV A, B; one uses register addressing and the
Move contents of register B to ACC last instruction uses direct addressing.
ADD C; 9.4.4 IMMEDIATE ADDRESSING
Add contents of register C to ACC
MOV D, A; When the operand is specified within
Move contents of ACC to register D the instruction itself, we say that
The two MOV instructions above immediate addressing mode has been
specify the two register names each as used. In this mode of addressing, to the
addresses of operands. The ADD operand address is not specified
instruction specifies only one register explicitly as in all the other modes.
as the operand register, the other Instead one or two bytes within the
operand is assumed to be in the ACC. All instructions are used for specifying the
the three instructions use register data itself. The MVI, LXI and ADI are
addressing. examples of instructions using the
immediate mode.
9.4.3 REGISTER INDIRECT ADDRESSING Example: It is desired to add the number S to
In register indirect addressing mode, the contents of the memory location
the contents of the specified register(s) AB12 and store the result in the
are assumed to be the address of the location FA0F. Assuming that the
symbolic address for AB12 is Z, we may
operand. Contrast this with the register
addressing mode where the contents of use the following instruction sequence
the register constitute the operand. In to perform this task
this mode, instead of specifying a Solution: LXI H, 0FFAH ;
register, a register-pair is specified to Load Register pair H-L with 0FFA
contain the 16-bit address of the LDA Z;
operand. As can be seen from the 8085 Get value of Z in ACC
ADI 5; Add 5 to it CMA fall into this category. All these are
MOV M, A; Store ACC in memory one byte instructions.
location pointed by register pair
H-L (i.e. to location FA0F) Example: It is desired to complement the
We first use an LXI instruction to put contents of memory location 5992. This
the address FA0F in register pair H-L. may be done by the following
Note that we have written the address instruction sequence.
as 0FFA in the LXI instruction because Solution:
the low order byte (0F) is moved to the LXI H, 9259; Set H-L to point to
second register of the pair (L) and the location 5992
high order byte (FA) to the first register MOV A, M; Get contents of 5992 in
of the pair (H). The next three ACC
instructions fetch the desired contents, CMA; Complement ACC
MOV M, A; Store the complement back in
add 5 to it and store the sum in location
location 5992.
FA0F using the MOV instruction. Note
that the MOV instruction uses register 9.5 INSTRUCTION SET OF 8085
indirect addressing
Note: Instructions using immediate An Instruction is a command given to
addressing may be 2 or 3 the computer to perform a specified
bytes long. operation on given data. The instruction
set of a microprocessor is the collection
9.4.5 IMPLICIT ADDRESSING of the instructions that the microprocessor is
designed to execute. The programmer
There are certain instructions that
can write a program in assembly
operate only on one operand. Such
language using these instructions. These
instructions assume that the operand is
instructions have been classified into
in the ACC and therefore need not
the following groups.
specify any address. Many instructions
in the logical group like RLC, RRC and
9.5.1 DATA TRANSFER INSTRUCTION
OPCODE OPERAND DESCRIPTION

Copy from source to destination This instruction copies the contents of the source
register into the destination register; the contents of
RD , RS the source register are not altered. If one of the
operands is a memory location, its location is
MOV M, RS
specified by the contents of the HL registers.
RD , M Example: MOV B, C or MOV B, M
Move immediate 8-bit The 8-bit data is stored in the destination register or
RD , data memory. If the operand is a memory location, its
location is specified by the contents of the HL
MVI
M, data registers.
Example: MVI B, 57 or MVI M, 57
Load accumulator The contents of a memory location, specified by a 16-
bit address in the operand, are copied to the
accumulator. The contents of the source are not
LDA 16 − bitaddress
altered.
Example: LDA 2034 or LDA XYZ
Load accumulator indirect The contents of the designated register pair point to a
LDAX B/Dregisterpair memory location. This instruction copies the contents
of that memory location into the accumulator. The
contents of either the register pair or the memory
location are not altered. Example: LDAX B
Load register pair immediate The instruction loads 16-bit data in the register pair
designated in the operand.
LXI Reg. pair, 16 − bitdata
Example: LXI H, 2034
Load H and L registers direct The instruction copies the contents of the memory
location pointed out by the 16-bit address into
register L and copies the contents of the next memory
LHLD 16 − bitaddress location into register H. The contents of source
memory locations are not altered.
Example: LHLD 2040
Store accumulator direct The contents of the accumulator are copied into the
memory location specified by the operand. This is a 3-
byte instruction, the second byte specifies the low-
STA 16 − bitaddress order address and the third byte specifies the high-
order address.
Example: STA 4350 or STA XYZ
Store accumulator indirect The contents of the accumulator are copied into the
memory location specified by the contents of the
operand (register pair). The contents of the
STAX Reg. pair
accumulator are not altered.
Example: STAX B
Store H and L registers direct The contents of register L are stored into the memory
location specified by the 16-bit address in the
operand and the contents of H register are stored into
the next memory location by incrementing the
SHLD 16 − bitaddress operand. The contents of registers HL are not altered.
This is a 3-byte instruction, the second byte specifies
the low-order address and the third byte specifies the
high-order address. Example: SHLD 2470
Exchange H and L with D and E The contents of register H are exchanged with the
contents of register D, and the contents of register L
XCHG none are exchanged with the contents of register E.
Example: XCHG
Copy H and L registers to the The instruction loads the contents of the H and L
stack pointer registers into the stack pointer register, the contents
of the H register provide the high-order address and
the contents of the L register provide the low-order
SPHL none address. The contents of the H and L registers are not
altered.
Example: SPHL
Exchange H and L with top of The contents of the L register are exchanged with the
stack stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
exchanged with the next stack location (SP+1);
XTHL none however, the contents of the stack pointer register are
not altered.
Example: XTHL
Push register pair onto stack
The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence. The stack pointer register is decremented
and the contents of the high order register (B, D, H, A)
PUSH Reg. pair are copied into that location. The stack pointer
register is decremented again and the contents of the
low-order register (C, E, L, flags) are copied to that
location.
Example: PUSH B or PUSH A
Pop off stack to register pair The contents of the memory location pointed out by
the stack pointer register are copied to the low-order
register (C, E, L, status flags) of the operand. The stack
pointer is incremented by 1 and the contents of that
POP Reg. pair memory location are copied to the high-order register
(B, D, H, A) of the operand. The stack pointer register
is again incremented by 1.
Example: POP H or POP A
Output data from accumulator to The contents of the accumulator are copied into the
a port with 8-bit address I/O port specified by the operand.
OUT 8 − bitportaddress Example: OUT 87
Input data to accumulator from a The contents of the input port designated in the
port with 8-bit address operand are read and loaded into the accumulator.
IN 8 − bitportaddress Example: IN 82
9.5.2 ARITHMETIC INSTRUCTION

Add register or memory to The contents of the operand (register or memory)
accumulator are M added to the contents of the accumulator and
the result is stored in the accumulator. If the
R operand is a memory location, its location is
specified by the contents of the HL registers. All
ADD
flags are modified to reflect the result of the
M addition.
Example: ADD B or ADD M
Add register to accumulator The contents of the operand (register or memory)
with carry and M the Carry flag are added to the contents of
the accumulator and the result is stored in the
R accumulator. If the operand is a memory location,
ADC its location is specified by the contents of the HL
M registers. All flags are modified to reflect the result
of the addition. Example: ADC B or ADC M
Add immediate to accumulator The 8-bit data (operand) is added to the contents of
the accumulator and the result is stored in the
ADI 8 − bitdata accumulator. All flags are modified to reflect the
result of the addition. Example: ADI 45
Add immediate to accumulator The 8-bit data (operand) and the Carry flag are
with carry added to the contents of the accumulator and the
ACI 8 − bitdata result is stored in the accumulator. All flags are
modified to reflect the result of the addition.
Example: ACI 45
Add register pair to H and L The 16-bit contents of the specified register pair are
registers added to the contents of the HL register and the
sum is stored in the HL register. The contents of the
source register pair are not altered. If the result is
DAD Reg. pair larger than 16 bits, the CY flag is set. No other flags
are affected.
Example: DAD H
Subtract register or memory The contents of the operand (register or memory)
from accumulator are M subtracted from the contents of the
accumulator, and the result is stored in the
its location is specified by the contents of the HL
SUB
registers. All flags are modified to reflect the result
M of the subtraction.
Example: SUB B or SUB M
Subtract source and borrow The contents of the operand (register or memory)
from accumulator and the Borrow flag are subtracted from the
contents of the accumulator and the result is placed
R in the accumulator. If the operand is a memory
location, its location is specified by the contents of
SBB
the HL registers. All flags are modified to reflect the
M result of the subtraction.
Example: SBB B or SBB M
Subtract immediate from The 8-bit data (operand) is subtracted from the
accumulator contents of the accumulator and the result is stored
in the accumulator. All flags are modified to reflect
SUI 8 − bitdata
the result of the subtraction. Example: SUI 45
Subtract immediate from The 8-bit data (operand) and the Borrow flag are
accumulator with borrow subtracted from the contents of the accumulator
and the result is stored in the accumulator. All flags
SBI 8 − bitdata are modified to reflect the result of the subtraction.
Example: SBI 45
Increment register or memory The contents of the designated register or memory)
by 1 are M incremented by 1 and the result is stored in
the same place. If the operand is a memory location,
R
its location is specified by the contents of the HL
INR registers.
M Example: INR B or INR M
Increment register pair by 1 The contents of the designated register pair are
incremented by 1 and the result is stored in the
INX R
same place. Example: INX H
Decrement register or memory The contents of the designated register or memory
by 1 are decremented by 1 and the result is stored in the
same place. If the operand is a memory location, its
R
location is specified by the contents of the HL
DCR registers.
M Example: DCR B or DCR M
Decrement register pair by 1
The contents of the designated register pair are
decremented by 1 and the result is stored in the
DCX R
same place.
Example: DCX H
Decimal adjust accumulator The contents of the accumulator are changed from
a binary value to two 4-bit binary coded decimal
(BCD) digits. This is the only instruction that uses
the auxiliary flag to perform the binary to BCD
conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are altered to
reflect the results of the operation. If the value of
DAA none the low-order 4-bits in the accumulator is greater
than 9 or if AC flag is set, the instruction adds 6 to
the low-order four bits. If the value of the high-
order 4-bits in the accumulator is greater than 9 or
if the Carry flag is set, the instruction adds 6 to the
high-order four bits.
Example: DAA
9.5.3 BRANCHING INSTRUCTIONS

Jump unconditionally The program sequence is transferred to the memory location
specified by the 16-bit address given in the operand. Example:
JMP 16-bitaddress JMP 2034 or JMP XYZ
Flag
Jump conditionally Description Status
JC 16-bit address Jump on Carry CY= 1
JNC 16-bit address Jump on no Carry CY = 0
JP 16-bit address Jump on positive S = 0
JM 16-bit address Jump on minusThe program sequence is
S = 1
JZ 16-bit address Jump on zerotransferred to the memory
Z = 1
location specified by the 16-bit
JNZ 16-bit address Jump on no zero Z = 0 address given in the operand
based on the specified flag of
JPE 16-bit address Jump on parity even P = 1
the PSW as described below.
JPO 16-bit address Jump on parity odd P = 0 Example: JZ 2034 or JZ XYZ
Unconditional subroutine The program sequence is transferred to the memory location
call specified by the 16-bit address given in the operand. Before the
transfer, the address of the next instruction after CALL (the
contents of the program counter) is pushed onto the stack.
CALL 16 − bitaddress Example: CALL 2034 or CALL XYZ
Flag
Call conditionally Description Status The program sequence is
transferred to the memory
location specified by the 16-bit
CC 16 − bit address Call on Carry CY = 1 address given in the operand
based on the specified flag of the
PSW as described below. Before
CNC 16 − bit address Call on no Carry CY = 0
the transfer, the address of the
next instruction after the call
CP 16 − bit address Call on positive S = 0 (the contents of the program
counter) is pushed onto the
stack.
CM 16 − bit address Call on minus S = 1 Example: CZ 2034 or CZ XYZ
CZ 16 − bit address Call on zero Z = 1
CNZ 16 − bit address Call on no zero Z = 0
CPE 16 − bit address Call on parity even P = 1
CPO 16 − bit address Call on parity odd P = 0

Return from subroutine The program sequence is transferred from the subroutine to the
unconditionally calling program. The two bytes from the top of the stack are
copied into the program counter, and program execution begins
RET none at the new address. Example: RET
Return from subroutine Flag
conditionally Description Status
RC none Return on Carry CY = 1
RNC none Return on no Carry CY = 0

The program sequence is
RP none Return on positive
transferred from S = 0
the
subroutine to the calling
RM none Return on minus S = 1 program based on the
specified flag of the PSW as
RZ none Return on zero Z = 1 described below. The two
bytes from the top of the
RNZ none Return on no zero Z = 0 stack are copied into the
program counter, and
RPE none Return on parity even P = 1 program execution begins at
the new address.
RPO none Return on parity odd P = 0 Example: RZ
Load program counter with The contents of registers H and L are copied into the program
HL contents counter. The contents of H are placed as the high-order byte and
PCHL none the contents of L as the low-order byte. Example: PCHL
Restart Restart Address
The RST instruction is equivalent to a 1-byte
RST 0 0000 H call instruction to one of eight memory
locations depending upon the number. The
RST 1 0008 H
instructions are generally used in
RST 2 0010 H conjunction with interrupts and inserted
using external hardware. However these can
RST 3 0018 H
be used as software instructions in a
RST 4 0020 H program to transfer program execution to
one of the eight locations.
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H
Interrupt Restart Address
TRAP none 0024 H
The 8085 has four additional interrupts and
RST 5.5 002C H these interrupts generate RST instructions
RST 6.5 0034 H internally and thus do not require any
RST 7.5 003C H external hardware.
9.5.4 LOGICAL INSTRUCTIONS

Compare register or memory The contents of the operand (register or memory)
with accumulator are compared with the contents of the accumulator.
Both contents are preserved. The result of the
R comparison is
shown by setting the flags of the PSW as follows:
CMP if (A) < (reg/mem): carry flag is set, Cy=1
if (A) = (reg/mem): zero flag is set, Z=1
M
if (A) > (reg/mem): carry and zero flags are reset,
Cy=0 Z=0 Example: CMP B or CMP M
Compare immediate with The second byte (8-bit data) is compared with the
accumulator contents of the accumulator. The values being
compared remain unchanged. The result of the
comparison is shown by setting the flags of the
PSW as follows:
if (A) < data: carry flag is set, Cy=1
CPI 8 − bitdata
if (A) = data: zero flag is set, Z=1
if (A) > data: carry and zero flags are reset, Cy=0
Z=0
Example: CPI 89
Logical AND register or memory The contents of the accumulator are logically
with accumulator ANDed with M the contents of the operand
(register or memory), and the result is placed in the
its address is specified by the contents of HL
ANA
registers. S, Z, P are modified to reflect the result of
M the operation. CY is reset. AC is set.
Example: ANA B or ANA M
Logical AND immediate with The contents of the accumulator are logically
accumulator ANDed with the 8-bit data (operand) and the result
is placed in the accumulator. S, Z, P are modified to
ANI 8 − bitdata reflect the result of the operation. CY is reset. AC is
set.
Example: ANI 86
Exclusive OR register or memory The contents of the accumulator are Exclusive

with accumulator ORed with the contents of the operand (register or
memory), and the result is placed in the
XRA
M the operation. CY and AC are reset.
Example: XRA B or XRA M
Exclusive OR immediate with The contents of the accumulator are Exclusive
accumulator ORed with the 8-bit data (operand) and the result
is placed in the accumulator. S, Z, P are modified to
reflect the result of the operation. CY and AC are
XRI 8 − bitdata reset.
Example: XRI 86
Logical OR register or memory The contents of the accumulator are logically ORed
with accumulator with M the contents of the operand (register or
ORA memory), and the result is placed in the
M the operation. CY and AC are reset.
Example: ORA B or ORA M
Logical OR immediate with The contents of the accumulator are logically ORed
accumulator with the 8-bit data (operand) and the result is
placed in the accumulator. S, Z, P are modified to
reflect the result of the operation. CY and AC are
ORI 8 − bitdata reset.
Example: ORI 86
Rotate accumulator left Each binary bit of the accumulator is rotated left by
one position. Bit D7 is placed in the position of D0
RLC none as well as in the Carry flag. CY is modified according
to bit D7. S, Z, P, AC are not affected. Example: RLC
Rotate accumulator right Each binary bit of the accumulator is rotated right
by one position. Bit D0 is placed in the position of
D7 as well as in the Carry flag. CY is modified
RRC none
according to bit D0. S, Z, P, AC are not affected.
Example: RRC
Rotate accumulator left through Each binary bit of the accumulator is rotated left by
carry one position through the Carry flag. Bit D7 is placed
in the Carry flag, and the Carry flag is placed in the
least significant position D0. CY is modified
RAL none
Example: RAL
Rotate accumulator right Each binary bit of the accumulator is rotated right
through carry by one position through the Carry flag. Bit D0 is
RAR none placed in the Carry flag, and the Carry flag is placed
in the most significant position D7. CY is modified
Example: RAR
Complement accumulator The contents of the accumulator are
complemented. No flags are affected. Example:
CMA none
CMA
Complement carry The Carry flag is complemented. No other flags are
CMC none affected. Example: CMC
Set Carry The Carry flag is set to 1. No other flags are affected.
STC none Example: STC
9.5.5 CONTROL INSTRUCTIONS

No operation No operation is performed. The instruction is
fetched and decoded. However no operation is
NOP none
executed.
Halt and enter wait state The CPU finishes executing the current instruction
and halts any further execution. An interrupt or
HLT none
reset is necessary to exit from the halt state.
Disable interrupts The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled. No flags
DI none
are affected.
Enable interrupts The interrupt enable flip-flop is set and all
interrupts are enabled. No flags are affected. After
a system reset or the acknowledgement of an
interrupt, the interrupt enable flip flop is reset, thus
EI none
disabling the interrupts. This instruction is
necessary to re enable the interrupts (except
TRAP).
GATE QUESTIONS
(MICROPROCESSOR-EC/EE/IN)
Topics Page No
9.1. BASIC OF MICRO 173
9.2. BASICS OF 8085 MICROPROCESSOR 177
9.3. INSTRUCTION OF 8085 MICROPROCESSOR 179
9.4. MEMORY INTERFACING 183
9.5. MICROPROCESSOR 8085 INTERFACING 184
9.6. MICROPROCESSOR 8085 INTERRUPTS 186
9.7. MICROPROCESSOR 8085 PROGRAMMING 187
9.8. MISCELLENEOUS 191
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material No part be
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copied should be copiedwithout
or reproduced or reproduced without permission
permission 172
9.1 BASIC OF MICRO
Q.1 A memory mapped I/O device has Q.4 8-bit signed integers in 2’s
an address of 00F0H. Which of the complement form are read into the
following 8085 instructions outputs accumulator of an 8085
the content of the accumulator to microprocessor from an I/O port
the I/O device? using the following assembly
a) LXI H,00F0H b)LXI H, 00F0H language program segment with
MOV M, A OUT M symbolic addresses.
c) LXI H, 00F0H d)LXI H, 00F0H BEGIN: INPORT
OUT F0H MOV A, M RAL
[GATE-2006] JNC BEGIN
RAR
Q.2 An 8085 assembly language END: HLT
program is given as follows. The This program
execution time of each instruction is a) Halts upon reading a negative
given against the instruction in number
terms of T-state. b) Halts upon reading a positive
Instruction T-states number
----------------- -------------- c) Halts upon reading a zero
MVI B, 0AH 7T d) Never halts
LOOP ; MVCI,05H 7T [GATE-2007]
DCR C 4T
DCR B 4T Q.5 A part of a program written for an
JNZ LOOP 10T/7T 8085 microprocessor is shown
The execution time of the program below. When the program execution
in terms of T-state. Is reaches LOOP2, the value of register
a) 247 T b) 250T C will be
c) 254 T d) 257 T SUB A
[GATE-2006] MOV C, A
LOOP I: INR A
Q. 3 snapshot of the address, date and DAA
control buses of an 8085 JC LOOP 2
microprocessor executing program INR C
is given below: JNC LOOPI
Address 2020H LOOP 2: NOP
Data 24H a) 63 H b) 64H
IO/ M Logic high c) 99H d)100H
RD Logic high [GATE-2008]
WR Logic Low
Q.6 The following is an assembly
The assembly language instruction language program for 8085
being executed is microprocessors
a) IN 24H b) IN 20H Address Instruction Mnemonic
c) OUT 24H d) OUT 20H Code
[GATE-2007] 1000H 3E,06 MVI A, 06H
1002 H C6 ,70 ADI 70H
1004 H 32, 07, 10 STA 1007H Address Op-code
1007H AF XRA A
1008 H 76 HLT 2000 3E, 00
When this program halts, the 2002 CD, 05, 20
accumulator contains 2005 3C
a) 00H b) 06H 2006 C9
c) 70H d) 76H
[GATE-2009] Level Mnemonic
SUB1: MVI A, 00h
Q.7 The subroutine SBX given below is CALL SUB 2
executed by an 8085 processor. The SUB 2: INR A
value in the accumulator RET
immediately after the execution of
the subroutine will be: a) 00 b) 01
SBX: MVI A, 99 H c) 02 d) 03
ADI 11 H [GATE-2010]
MOV C, A Q.9 A microprocessor accepts external
RET interrupts (Ext INT) through a
a) 00H b) 11H Programmable Interrupt Controller
c)99H d)AAH as shown in the figure.
[GATE-2010]
Q.8 In an 8085 processor, the main

program calls the subroutine SUB1
given below. When the program
returns to the main program after
executing SUB1, the value in the Assuming vectored interrupt, a
accumulator is correct sequence of operations
when a single external
interrupt (Ext INT1) is received will
be :
a) Ext INT1 → INTA → Data Read →
INT
b) Ext INT1 → INT → INTA → Data
Read
c) Ext INT1 → INT → INTA →
Address Write
d) Ext INT1 → INT → Data Read →
Address Write
[GATE-2014]
ANSWER KEY:
1 2 3 4 5 6 7 8 9
(a) (c) (d) (a) (c) (a) (d) (b) (b)
EXPLANATIONS
Q.1 (a) Q.5 (c)

Instruction operation
SUB A-----------A=00H and
LXI H, 00F0H - HL =00F0
CY=0
MOV M, A accumulator contents will
be transferred to IO of address 00F0
MOV C, A------C=00H and
A=00H and
Q.2 (c) CY=0
Execution time= (7 + (9 x 25) + 22)T LOOP1: INR A--Inrement A by 1.
= 254 T DAA---Decimal adjust
The loop will run for 9 times and at accumulator if any
the last when the instruction JNZ of the bytes are
loop will be false then greater than 9
microprocessor will come out from JC LOOP2-------go to LOOP 2 if
the loop and instruction will take carry is set
only 7T state instead of 10T state. INR C--------increment C but
there is no effect
Q. 3 (d) on carry flag.
It is OUT 20 instructions.
The only way to go to LOOP 2 is
Q.4 (a) when carry get set.
The program halts upon reading a And it get set when carry is
negative number. generated due to DAA instruction.
When A and C become 99H and
control goes
to LOOP 1 then INRA will make,
A=9AH
Now DAA will adjust the lower
order byte of accumulator since it is
greater than 9.
Now, 9AH serviced first and now INT signal is
+06H raised by interrupt controller and it
=A0H is sensed by microprocessor, then
Now again it will adjust the higher microprocessor first completes their
order byte by adding 6 to higher current machine cycle and raised
data byte, that is the INTA (interrupt acknowledge)
A0H signal back to PI controller. This is
+60H vectored interrupt so, their address
=1|00H is fixed and ISR (interrupt service
therefore CY=1, content of C=99H Routine) execution will takes place
and A=00H from that address. So, this
sequences is matching with option
(B) only
Q.6 (a)
MVI A, 06 → A = 06H
ADI 70 → A = 06H + 70H = 76H
STA 1007→A=76H,(1007H) =76H
XRA A → A = 00H
HLT
Last instruction is XRA A, so
accumulator contents will be 00.
Q.7 (d)
Instruction
Content of register
MVI A, 99 H → A=99
ADI 11 H → A=99+11=AAH
MOV C, A → A=AAH, C=AAH
Q.8 (b)
SUB 1: MVI A, 00H A← 00H
CALL SUB → program will shifted to
SUB 2 address location
SUB 2 : INR A →A
01H
RET → returned to main program
∴ The contents of Accumulation
after execution of the above SUB 2 is
01H
Q.9 (b)
When a single external interrupt
(Exp INT1) is raised then it is sensed
by programmable interrupt controller
and as per their priority it is
9.2 BASICS OF 8085 MICROPROCESSOR
Q.1 In register index addressing mode Q.4 An I/O processor controls the flow
the effective address is given by of information between
a) The index register value a) cache memory and I/O devices
b) The sum of the index register b) main memory and I/O devices
value and the operand. c) two I/O devices
c) The operand. d) cache and main memories
d) The difference of the index [GATE-1998]
register value and the operand. Q.5 An instruction used to set the carry
[GATE-1988] Flag in a computer can be classified
as
Q.2 In a microcomputer, WAIT states a) data transfer b) arithmetic
are used to c) logical d) program control
a) make the processor wait during [GATE-1998]
a DMA operation Q.6 In an 8085 microprocessor, the shift
b) make the processor wait during registers which store the result of an
an interrupt processing. addition and the overflow bit are,
c) make the processor wait during respectively
a power shutdown a) B and F b) A and F
d) interface slow peripherals to the c) H and F d) A and C
processor. [GATE-2015(1)]
[GATE-1993 ]
Q.3 An 'Assembler' for a microprocessor

is used for
a) assembly of processors in a
production line.
b) creation of new programmes
using different modules.
c) translation of a program from
assembly language to machine
language.
d) translation of a higher level
language into English text.
[GATE-1995]
ANSWER KEY:
1 2 3 4 5 6
(a) (d) (c) (b) (c) (b)
EXPLANATIONS
Q.1 (a)
In register index addressing mode the
effective address is given by the index
register value.
Q.2 (d)
In a microcomputer, wait states are
used to interface slow peripherals to
the processor.
Q.3 (c)
An 'Assembler' for a microprocessor is
used for translation of a program from
assembly language to machine
language.
Q.4 (b)
An I/O processor controls the flow of
information between main memory
and I/O devices.
Q.5 (c)
An instruction used to set the carry flag
in a compute-can be classified as
logical instruction.
Q.6 (b)
Shift register are accumulator and flag
register(A and F).
9.3 INSTRUCTION OF 8085 MICROPROCESSOR
Q.1 In an 8085 microprocessor. The [GATE-2004]

instruction CMP B has been Q.4 It is desired to multiply the numbers
executed while the content of the 0AH by 0BH and store the result in
accumulator is less than that of the accumulator. The numbers are
register B. As a result available in registers B and C
a) Carry flag will be set but Zero respectively. A Part of the 8085
flag will be reset program for this purpose is given
b) Carry flag will be reset but Zero below:
flag will be reset MVI A, 00H
c) Both Carry flag and Zero flag will Loop;-----------
be reset ------------------
d) Both Carry flag and Zero flag will ------------------
be set HLT END
[GATE-2003] The sequence of instructions to
Q.2 The number of memory cycles complete the program would be
required to executed the following a) JNZ LOOP,ADD B, DCR C
8085 instructions b) ADD B,JNZ LOOP, DCR C
(I)LDA 3000H c) DCR C, JNZ LOOP, ADD B
(II) LXI D,F0F1 H would be d) ADD B, DCR C, JNZ LOOP
[GATE-2004]
a) 2 for (I) and 2 for (II)
b) 4 for (I) and 3 for (II) Common data for questions 5 & 6
c) 3 for (I) and 3 for (II) Consider an 8085 microprocessor system
d) 3 for (I) and 4 for (II) Q.5 The following program starts at
[GATE-2004] location 0100H.
Q.3 Consider the sequence of 8085 LXI SP, 00FF
instructions given below. LXI H, 0107
LXI H, 9258, MVI A, 20H
MOV A, M, SUB M
CMA , The content of accumulator when
MOV M, A the program counter reaches 0109
Which one of the following is H is
performed by this sequence? a) 20H b) 02H
a) Contents of location 9258 are c) 00H d) FFH
moved to the accumulator [GATE-2005]
b) Contents of location 9258 are Q.6 If in addition following code exists
compared with the contents of from 0109H onwards,
the accumulator ORI 40 H
c) Contents of location 9258 are ADD M
complemented and stored in What will be the result in the
location 9258 accumulator after the last
d) Contents of location 5892 are instruction is executed?
complemented and stored in a)40H b)20H
location 5892 c)60 H d)42H
[GATE-2005]
Q.7 An 8085 executed the following Q.10 In an 8085 system, a PUSH
instructions operation requires more clock
2710 LXI H, 30A0H cycles than a POP operation. Which
2713 DAD H one of the following options is the
2714 PCHL correct reason for this?
All addresses and constants are in a) For POP, the data transceivers
Hex. Let PC be the contents of the remain in the same direction as
program counter and HL be the for instruction fetch (memory to
contents of the HL register pair just processor), whereas for PUSH
after executing PCHL. their direction has to be
Which of the following statements is reversed.
correct? b) Memory write operations are
a)PC=2715 H HL 30A0H slower than memory read
b) PC=30A0 H HL 2715H operations in an 8085 based
c) PC=6140 H HL 6140H system.
d) PC=6140 H HL 2715H c) The stack pointer needs to be
[GATE-2008] pre-decremented before writing
registers in a PUSH, whereas a
Q.8 For the 8085 assembly language POP operation uses the address
program given below, the contents already in the stack pointer.
of the accumulator after execution d) Order of registers has to be
of the program is interchanged for a PUSH
300 MVI A, 45 operation, whereas POP uses
3002 MOV B, A their natural order.
3003 STC [GATE-2016]
3004 CMC
3005 RAR Q.11 In an 8085 microprocessor, the
3006 XRA B contents of the accumulator and the
a)00H b)45H carry flag are A7 (in hex) and 0,
c)67 H d)E7H respectively. If the instruction RLC is
[GATE-2010] executed, then the contents of the
accumulator (in hex) and the carry
Q.9 In an 8085 microprocessor, which flag, respectively, will be
one of the following instructions a) 4E and 0 b) 4E and 1
changes the content of the c) 4F and 0 d) 4F and 1
accumulator? [GATE-2016]
a) MOV B, M b) PCHL
c) RNZ d) SBI BEH
[GATE-2015]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11
(a) (b) (c) (d) (c) (c) (c) (c) (d) (c) (d)
EXPLANATIONS
Q.1 (a)
M contains the data of memory
CMP B → Contents of B and A are
whose address is in HL pair.
compared and result is indicated by
HL has addressed 0107H.
flag.
0107H corresponds to 20 H.
A < B,∴ CY = 1, Z = 0
∴ A − M= 20H − 20H= 00H
Q.2 (b) Q.6 (c)
Memory cycles 0109 H ORI 40 H
Read, Read Read 010BH ADD M
LDA3000H → Fetch,
address data Initial: A =00H
LXID,F0F1H → Fetch,Read,Read 0109H:ORI40H⇒A←A(OR)40H
=40H
Q.3 (c) O10BH:ADD M⇒A←A+M
LXI H,9258 → HL ← 9258 =40H+20H=60H
MOV A, M → contents of add.9258 ∴ A=60H
CMA → Complement Accumulato
MOV MA → Complement of A is stroed Q.7 (c)
Contents
in M(9258H) LXI H 30 A0H HL=30A0
DAD H HL=6140
Q.4 (d) (i.e., 30A0+30A0)
ADD B, DCR C, JNZ LOOP PCHL PC=6140
Therefore contents are
MVI A, 00H A=00H PC=6140,
LOOP ADD B A=A+B HL= 6140
DCR C C=C-1
Loop will till Q.8 (c)
C=00H Instruction Content
JNZ LOOP So, loop will MVI A 45H
execute 11 times A=45H → (=01000101)
(OB)Hex MOV B, A B = 45 H
STC CY =1
Q.5 (c) CMC CY =0
0100H: LXI SP, 00FF RAR
0103H: LXI H, 0107
0106H: MVI A, 20H
0108H: SUB m → A ← A − M
A=00100010
XRA
B A ← (00100010) ⊕ (01000101)
Or A ← 01100111
Or A ← 67H
Therefore, the content of the
accumulator after execution of the
program is 67 H.
Q.9 (D)
Generally arithmetic or logical
instructions update the data of
accumulator and flags. So, in the
given option only SBT BE H is
arithmetic instruction.
SBI BE H → Add the content of
accumulator with immediate data
BE H and store the result in
accumulator.
Q.10 (C)
In push operation 3 cycles involved:
6T+3T+3T = 12T
POP operation 3 cycle involved:
4T+3T+3T = 10T
So in the opcode fetch cycle 2T
states are extra in case of push
compared to POP and this is
needed to decrement the SP.
Q.11 (D)
Accumulator
RLC-*Rotate left accumulator

content without carry
9.4 MEMORY INTERFACING
Q.1 An 8255 chip is interfaced to an a)F8H-FBH b)F8H=FCH

8085 microprocessor system as an c)F8H-FFH d)F0H=F7H
I/O mapped I/O as shown in the [GATE-2007]
figure. The address lines A 0 and A1
of the 8085 are used by the 8255 Q.2 In the circuit shown , the device
chip to decode internally its three connected to Y5 can have address in
ports and the Control register. The the range
address lines A 3 to A 7 as well as
the IO M
Signal are used for address decoding
The range of addresses for which
the 8255 chip would get selected is
a)2000-20FF b)2D00-2DFF
c)2E00-2EFF d)FD00-FDFF
[GATE-2010]
ANSWER KEY:
1 2
(c) (b)
EXPLANATIONS
Q.1 (c) A15 A14 A13 A12 A11 A10 A 9 A8 A 7 … A 6

O/P of NAND gates is 0 if A 7 to A 3 &
0 0 1 0 1 1 0 1 0…0
IO M =1 0 0 1 0 1 1 0 1 1…1
A7 A 6 A 5 A 4 A 3 A 2 A1 A0
Therefore, the device can have
Starting Address1 1 1 1 1 0 0 0 → F89H
address in the range of 2D00 H –
FinalAddresss1 1 1 1 1 1 1 1 → FFH
2DFF H.
Q.2 (b)
To connect Y5, input CBA should be
101.
Possible range will be
9.5 MICROPROCESSOR 8085 INTERFACING
Q.1 The 8255 Programmable Peripheral

interface is used as described below.
I) An A/D converter is interfaced
to a microprocessor through and
8255. The conversion is initiated
by a signal from the 8255 on
Port C. A signal on Port C causes
data to be strobed into Port A.
II) Two computers exchange data
using a pair of 8255s. Port A a) MVI A, F8H b) IN F8H
works as a bidirectional data c) OUT F8H d) LDA F8F8H
port supported by appropriate [GATE-2014]
handshaking signals. Q.3 An 8 Kbyte ROM with an active low
The appropriate modes of operation Chip Select input ( CS )is to be used
of the 8255 for (I) and (II) would be in an 8085 microprocessor based
a) Mode 0 for (I) and Mode 1 for (II) system. The ROM should occupy the
b) Mode 1 for (I) and Mode 0 for (II) address range 1000H to 2FFFH. The
c) Mode 2 for (I) and Mode 0 for (II) address lines are designated as Al5
d) Mode 2 for (I) and Mode 1 for (II) to A0, where A15 is the most
[GATE-2004] significant address bit. Which one of
the following logic expressions will
Q.2 For the 8085 microprocessor, the generate the correct ( CS ) signal for
interfacing circuit to input 8-bit this ROM?
digital data (DI0 – DI7) from an �13.A
a) A15 + A14 + (A13.Al2 + A �l2 )
external device is shown in the b) A15.A14.(A13 + Al2)
figure. The instruction for correct �15 A
c) A �14 + (A13.Al2 + A
�13.Al2 )
data transfer is �15 + A
d) A �14 A13.Al2
[GATE-2016]
ANSWER KEY:
1 2 3
* (d) (a)
EXPLANATIONS
Q.1 (*)
=CS (A14 A15 A13 A12 + A14 A15 A13 A12 )
Option are incorrect since port A ca
be operated as bidirectional port = A14 + A15 + (A13 A12 + A13 A12 )
only in mode -2 . (b) Can be correct
if it is mode 1 for (1) and mode 2 for
(11).
Q.2 (D)
This circuit diagram indicating that
it is memory mapped I/O because
to enable the 3-to-8 decoder ��
G2A is
required active low signal through
(Io/m� ) and ��
G2B is required active
low through (R ��
D ) it means I/o
device read the status of device LDA
instruction is appropriate with
device address
Again to enable the decoder o/p of
AND gate must be 1 and Ds2 signal
required is 1 which is the o/p of
multi-i/p AND gate to enable I/0
device.
So,
Device address = F8F8H

The correct instruction used → LDA
F8F8H
Q.3 (A)
Addressing varying from 1000 H to
2FFFH
i.e.
0001 0000 0000 0000 H
.
.
0010 1111 1111 1111 H
9.6 MICROPROCESSOR 8085 INTERRUPTS
Q.1 In an 8085 IP system, the RST Each interrupt is assigned 8-bytes

instruction will cause an interrupt for interrupt service routine. So,
a) Only if an interrupt service
routine is not being executed Q.3 In the 8085 microprocessor, the
b) Only if a bit in the interrupt mask RST6 instruction transfers the
is made 0 program execution to the following
c) Only if interrupts have been location:
enabled by an EI instruction a) 30 H b) 24 H
d) None of the above c) 48 H d) 60 H
[GATE-1997] [GATE-2000]
Q.2 The number of hardware interrupts Q.4 In a microprocessor, the service

(which require an external signal to routine for a certain interrupt starts
interrupt) present in an 8085 from a fixed location of memory
microprocessor are which cannot be externally set, but
a) 1 b) 4 the interrupt can be delayed or
c) 5 d) 13 rejected. Such an interrupt is
[GATE-2000] a) non-maskable and non-vectored
b) maskable and non-vectored
c) non-maskable and vectored
d) maskable and vectored
[GATE-2009]
ANSWER KEY:
1 2 3 4
(c) (c) (a) (d)
Q.1 (c)
RST instruction will cause an Q.3 (a)
interrupt only if interrupts have Hexadecimal address of RST6
been enabled by an EI instruction at (6 × 8 = 48)10 = 30 H.
the beginning of programme.
Q.2 (c) Q.4 (c)
1. TRAP Interrupt which has fixed address
2. RST 7.5 location is said to be vectored and
3. RST 6.5 which can be delayed or rejected is
4. RST 5.5 known as maskable.
5. INTR
9.7 MICROPROCESSOR 8085 PROGRAMMING
Q.1 Consider the following assembly Statement for Linked Answer Question
language program. 3&4
MVI B, 87 H An 8085 assembly language program is
MOV A, B given below:
START: JMP NEXT Line 1: MVI A, B5H
MVI B 00H 2: MVI B, 0EH
XRA B 3: XRI 69H
OUT PORT 1 4: ADD B
HLT 5:ANI9BH
NEXT: XRA B 6:CPI9FH
JP START 7: STA 3010 H
OUT PORT2 8: HLT
HLT
The execution of the above program Q.3 The contents of the accumulator just
in a n8085 microprocessor will after execution of the ADD
result in an 8085 microprocessor instruction in line 4 will be
will result in a)C3H b)EAH
a) an output of 87H at PORT 1 c)DCH d)69H
b) an output of 87 H at PORT 2 [GATE-2007]
c) Infinite looping of the program
execution with accumulator data Q.4 After execution of line 7 of the
remaining at 00H. program. The status of the CY and Z
d) infinite looping of the program flags will be
execution with accumulator data a) CY=0,Z=0 b) CY=0,Z=1
alternating between 00H and 87 H c) CY=1, Z=0 d) CY=1,Z=1
[GATE-2002] [GATE-2007]
Q.2 Following is the segment of a 8085 Q.5 For 8085 microprocessor, the
assembly language program: following program is executed
LXI SP, EFFFH MVI A, 05H;
CALL 3000H MVI B O5 H;
3000H: LXI H,3CF4H PTR: ADD B;
PUSH PSW DCR B;
SPHL JNZ PTR;
POP PSW ADI 03 H;
RET HLT;
On completion of RET execution, the At the end of program, accumulator
contents of SP is contains
a)3CFO H b)3CF8H a)17H b)20H
c)EFFD H d)EFFF H c)23H d)05H
[GATE-2006] [GATE-2013]
Q.6 An 8085 microprocessor executes

"STA 1234H" with starting address
location 1FFEH (STA copies the
contents of the Accumulator to the
16-bit address location). While the b) MVI, A, OOH
instruction is fetched and executed, CMP C
the sequence of values written at the LOOP DCR B
address pins A15-A8 is JNZ LOOP
a) 1FH, 1FH, 20H, 12H HLT
b) 1FH, FEH, 1FH, FFH, 12H c) MVI A, OOH
c) 1FH, 1FH, 12H, 12H LOOP ADD C
d) 1FH, 1FH, 12H, 20H, 12H DCR B
[GATE-2014] JNZ LOOP
HLT
Q.7 Which one of the following 8085 d) MVI A, OOH
microprocessor programs correctly ADD C
calculates the product of two 8-bit JNZ LOOP
numbers stored in registers B and LOOP INR B
C? HLT
a) MVI A, 00 H [GATE-2016]
JNZ LOOP
CMP C
LOOP DCR B
HLT
ANSWER KEY:
1 2 3 4 5 6 7
(b) (b) (b) (c) (a) (a) (c)
EXPLANATIONS
Q.1 (b) RET = POP + JMP ie.,

RET
MVI B, 87 H B ← 10000111 SP ← SP + 2
MOV A, B A ← 10000111 SP ← 3CF8H
START: JMP NEXT
MVI B, 00H Q.3 (b)
XRA B After
OUTPORT 1 Line1 → A ← 10110101
HLT Line2 → B ← 00001110
NEXT: XRA B → 00H A → 00H Line3 ← 01101001
JP START B → 87H, B → 87H A ← 10110101
OUTPORT 2 → 87H Line4 → B ← 00001110
HLT
XOR of A with B gives 00H.
→
00H 00000000
↓
+ 11101010
Sign flag =0 (plus)
A←EA
JP takes the loop to START. Again
A←EAH
JMP NEXT is executed. Now XOR of
B with A gives 87 H. Q.4 (c)
87 H → 10000111 After ADD B : A ← EAH
Sign flag =1(-ve) ANI 9B : A ← 8AH
∴ 87H at PORT2 CPI 9F H : A ← 8AH
But [A]<9FH
Q.2 (b)
I.e., 8A<FH
LXI SP, EFFFH
∴ CY=1;Z=0
CALL 3000H
⇒ PUSH + JMP SP → SP − 2 Q.5 (a)
⇒ SP = EFFFD A = 05 + 05 + 04 + 03 + 02 + 01 + 03
3000H: LXI H, 3CF 4 H A = 23
HL ← 3CF4 A = 17H
PUSH PSW SP ← SP − 2 = EFFB
SPHL SP ← 3CF4 Q.6 (A)
POP PSW SP ← SP + 2 = 3CF6 Let the opcode of STA is XXH and
content of accumulator is YYH.
Instruction: STA 1234 H
Starting address given = 1FFEH
So, the sequence of data and
addresses is given below:
Address (in hex) : Data (in hex)
Q.7 (c)
MVI A, 00H ← Load accumulator by
00H
Loop: ADDC ← Add the content
of accumulator with content of P
Register and store result in
accumulator.
This will continue till B register
reaches to 004.
DCRB
JNZ LOOP
HLT
So, repetitive addition of a number
as many times will give the product
of these two numbers.
9.8 MISCELLENEOUS
Q.1 An Intel 8085 processor is executing Q.4 When a program is being executed
The program given below. in an 8085 microprocessor, its
MVI A, 10H Program Counter contains
MVI B, 10H a) the number of instructions in the
Back: NOP current program that have
ADD B already been executed
RLC b) the total number of instructions
JNCBACK in the program being executed
HLT c) the memory address of the
The number of times that the instruction that is being
operation NOP will be executed is currently executed
equal to d) the memory address of the
a) 1 b) 2 instruction that is to be executed
c) 3 d) 4 next
[GATE-2001] [GATE-2003]
Q.2 The logic circuit used to generate Q.5 The following program is written for
the active low chip select (CS) by an an 8085 microprocessor to add two
8085 microprocessor to address a bytes located at memory addresses
peripheral is shown in figure. The 1FFE and 1FFF
peripheral will respond to LXI H, 1FFE
addresses in the figure. MOV B, M
INR L
MOV A, M
ADD B
INR L
a) E000-EFFF b) 000E-FFFE MOV M, A
c) 1000-FFFF d) 0001-FFF1 XRA A
[GATE-2002] On completion of the execution of
Q.3 When a program is being executed the program, the result of addition is
in an 8085 microprocessor, its found
program counter contains a) in the register A
a) the number of instructions in the b) at the memory address 1000
current program that have c) at the memory address 1F00
already been executed. d) at the memory address 2000
b) the total number of instructions [GATE-2003]
in the program being executed.
c) the memory address of the Q.6 If the following program is executed
instruction that is being in a microprocessor, the number of
currently executed. instruction cycles it will take from
d) the memory address of the START to HALT is
instruction that is to be executed START MVI A, 14H ; MOVE 14H
next. to register A
[GATE-2002] SHIFT RLC ; Rotate left
without carry
JNZ SHIFT ; Jump on Address Content
non-zero to . . . .
SHIFT 26FE 00
HALT ; 26FF 01
2700 02
a) 4 b) 8 2701 03
c) 13 d) 16 2702 04
[GATE-2004] . . . .
The content of stack (SP) program
Q.7 The 8085 assembly language counter (PC) and (H, L) are 2700 H,
instruction that stores the content of 2100 H and 0000 H respectively.
H and L registers into the memory When the following sequence of
locations 2050H and 2051H instruction are executed
respectively is 2100H : DAD SP
a) SPHL2050H b) SPHL2051H 2101H : PCHL
c) SHLD2050H d) STAX 2050H The content of (SP) and (PC) at the
[GATE-2005] end of execution will be
a) PC=2102 H, SP=2700
Q.8 A software delay subroutine is b) PC=2700 H, SP=2700 H
written as given below: c) PC=2800H, SP=26FE H
DELAY: MVI H, 255D d) PC=2A02 H, SP=2702 H
MVI L, 255D [GATE-2008]
LOOP: DCR L
JNZ LOOP Q.11 In an 8085 microprocessor, the
DCR H contents of the Accumulator, after
JNZ LOOP the following instruction are executed
How many times DCR L instruction will becomes
will be executed? XRA A
a) 255 b) 510 MVIB F0H
c) 65025 d) 65279 SUB B
[GATE-2006] a) 01H b) 0F H
c) F0 H d) 10 H
Q.9 In 8085 A microprocessor based [GATE-2009]
system, it is desired to increment
the contents of memory location Q.12 When a “CALL Addr” instruction is
whose address is available in (D, E) executed, the CPU carries out the
register pair and store the result in following sequential operations
same location .The sequence of internally:
instruction is Note :
a)XCHG b)XCHG (R) means content of register R
INR M INX H ((R)) means content of memory
c)INX D d)INR M location pointed to by R
XCHG XCHG PC means Program Counter
[GATE-2006] SP means Stack Pointer
a) SP incremented
Q.10 The content of some of the memory (PC) ← Addr
location in an 8085 A based system ((SP)) ← (PC)
are given below b) (PC) ← Addr
((SP)) ← (PC)
(SP) incremented a) 8C H b) 64 H
c) (PC)← Addr c) 23 H d)15 H
(SP) incremented [EC-GATE-2010]
((SP)) ←(PC)
d) ((SP)) ←(PC) Q.15 In an 8085 microprocessor, the
(SP) incremented following program is executed
(PC) ← Addr Address location — Instruction
[GATE-2010] 2000H XRA A
2001H MVI B,04H
Q.13 A portion of the main program to 2003H MVI A, 03H
call a subroutine SUB in an 8085 2005H RAR
environment is given below. 2006H DCR B
: 2007H JNZ 2005
LXI D, DISP 200AH HLT
LP: CALL SUB At the end of program, register A
: contains
: a) 60H b) 30H
It is desired that control be returned c) 06H d) 03H
to LP+DISP +3 when the RET [EE-GATE-2014-01]
instruction is executed in the
subroutine. The set of instructions Q.16 In 8085A microprocessor, the
that precede the RET instruction in operation performed by the
the subroutine are instruction LHLD 2100H is
a) POP D b) POP H a) ( H ) ← 21H , (L) ← 00H
DAD H DAD D
b) ( H ) ← M ( 2100H ) , (L) ← M(2101H )
PUSH D INX H
INX H c) ( H ) ← M ( 2101H ) , (L) ← M(2100H )
INX H d) ( H ) ← 00H , (L) ← 21H
PUSH H
[EE-GATE-2014-02]
c) POP H d) XTHL
DAD D INX D
Q.17 A portion of an assembly language
PUSH H INX D
INX D program written for an 8-bit
XTHL microprocessor is given below along with
[GATE-2011] explanations. The code is intended to
introduce a software time delay. The
Q.14 An 8085 assembly language processor is driven by a 5 MHz clock. The
program is given below. Assume hat time delay (in µs) introduced by the
the carry flag is initially unset. The program is _____________.
contents of the accumulator after
execution of the program is MVI B, 64 H; Move immediate the given byte into
MVI A, 07H register B. Takes 7 clock periods.
RLC
MOV B, A LOOP: DCR B; Decrement register B.
RLC Affects Flags. Take 4 lock periods.
RLC
ADD B JNZ LOOP; Jump to address with Label
RRC LOOP if zero flag is not set.
Takes 10 clock periods when jump is
performed and 7 clock periods
When jump is not performed.
[IN-GATE-2018]
ANSWER KEY:
1 2 3 4 5 6 7 8 9 10 11 12 13 14
(c) (a) (d) (d) (c) (a) (c) (d) (a) (b) (d) (c) (c) (c)
15 16 17
(a) (c) 280.8
EXPLANATIONS
Q.1 (c) Q.2 (a)

First loop
ADD B A15 A14 A13 A12 A11 L A 0
Accumulator -20H 1 1 1 0 0 L 0
1 1 1 0 1 L 1
⇒E000-EFFF
Q.3 (d)
RLC
Second loop: Q.4 (d)
0 10 00 00 0 Program counter contains the
ACC memory address of the instruction
0 00 10 00 0
that is to be executed next.
01010000
RLC
10100000 Q.5 (c)
Third loop: LXI H, IFFE→ Load 1FFE in H-L
CY 0 memory
1 01 0 0 0 0 0 MOV B → move content of 1FFE
ACC memory location to register B
0 00 10 00 0
10110 0 0 INR L → increment the content of
RLC ’HL’ by 1
10110 0 0 1FFE → 1FFF
CY 1 MOV A, M → move content of
Carry is generated. Now program 1FFF memory location to
will hault. accumulator
So NOP instruction is executed 3 ADD B → (A → A+B)
times. INR L → FF+1 → 00
∴HL → 1F 00
MOV M, A → move content of
accumulator to memory location 1F
00
XRA A → content of accumulator 2101 H: PCHL : the content of HL are
becomes zero. transferred to (PC)
So now
Q.6 (a) (PC)=2700H and (SP) also
There are four instructions that are unchanged
executed so required 4 instruction (PC)=2700H
cycles. (SP)=2700 H
Q.7 (c) Q.11 (d)

Instruction SHL 2050H D stores the XRA A → Accumulator is cleared,
content of L to memory location A → 00H
2050H and content of register H to MVI B
SUB B ← (A) ← (A) ← (B)
next memory location 2051H .
A ← 10H
Q.8 (d) Q.12 (c)

First of all DCR L will be executed First of all content of PC is loaded
for 255 times till content of L into stack i.e. address of next
becomes 0. instruction to be executed is loaded
After that for every decrement of H onto stack. i.e SP is decremented
it will be executed 256 times (first then PC is loaded by address given
when L is decremented by 1 and in call instruction.
becomes FFH and FFH =255D times)
and this will be happen til content of Q.13 (c)
H becomes 1 i.e. 254 times.
So overall it will be executed
=255+254×256
=65279
Q.9 (a) Call takes 3 address location. RET

The address of the memory location always returns to LP+3 location, this
is stored in DE register pair. But INR stored in SP. So to return to
M command will increase the LP+DISP+3
content of memory location M. But We have to add DISP to SP.
this command will execute only on POP H
HL pair. So we have to exchange the DAD D
address of memory location in HL PUSH H
pair from DE pair first. Normal call operation shown.
Q.10 (b) Q.14 (c)

Given RLC → Rotate Acc left without carry
(SP)=2700H B ← 00001110
(PC)=2100H RLC 
(HL)=0000H  → 00111000 → A
2100H : DAD SP RLC 
(SP) + (HL) →(HL) 00111000
2700H+0000H=2700H stored in HL 00001110
pair ADDB → 01000110
RRC → 00100011=23H is required 2-Byte data, but in 8085
at one address it contains only one-
Q.15 (a) byte data, so this instruction will
Address location Instruction access two memory locations. So,
operation first byte address (i.e., 2100H) is
2000H XRA A [A] mentioned in instruction itself and
=00H, CY = 0, Z= 1 by default second byte data is
2001H MVI B, 04H [B] accessed from the next location (i.e.,
=04H 2101H). Lower address data will be
2003H MVI A, 03H [A] copied to lower byte
=03H (L)←M(2100H)) and higher address
2005H RAR data will be copied to higher byte
Rotate accumulator right with carry (i.e, (L)←M(2101H)).
2006H DCR B
Decrement content of B register Q.17 280.8
by one
2007H JNZ 2005 H (64)10 = (100)10
200AH HLT → MVI B, 64 H ⇒=
B (64)= (100) H
H
It will be executed only once ⇒ 7clocks

DCR B 
→ Sin ce B =
JNZ LOOP 
100, this loop will run due to true con
So the number of clock = 99(4 + 10) = 1386
→ On the 100th iteration, when B = 0, “JNZ Loop”

will take 7 clocks, as the condition is false (Z= 1).
So this 100th iteration needs = 1 (4+7) = 11 clocks
→ So, total: 7 + 1386 + 11 = 1404 clocks are

needed
Q.16 (c)
Instruction given is: LHLD 2100H
The operation performed by this
instruction is load HL register pair
from the specified address in the
instruction, directly. HL register pair
ASSIGNMENT QUESTIONS (DIGITAL)
Q.1 For the logic circuit shown in figure

below, the output Y is equal to
a) NAND b) AND
��
a)ABC �+B
b)A � +C� c) NOR d)OR
�� + ��
c)AB � + C�
BC + A �� + ��
d)AB BC
Q.5 The initial contents of the 4-bit
Q.2 The logic realized by the circuit serial-in-parallel-out, right-shift,
shown in figure below, is Shift Register shown in figure below,
is 0110. After three clock pulses are
applied, the contents of the Shift
Register will be
a)0000 b)0101
c) 1010 d) 1111
a) F = A⨀C b) F = A⊕C Q.6 The binary representation of 5.375

c) F = B⨀C d) F = B⊕C is
a) 111.1011 b) 101.1101
Q.3 Choose the correct statement (s) c) 101.011 d) 111.001
from the following
a) PROM contains a programmable Q.7 Dual slope integration type Analog-
AND array and a fixed OR array. to-Digital converters provide
b) PLA contains a fixed AND array a) Higher speeds compared to all
and a programmable OR array. other types of A / D converters
c) PROM contains a fixed AND b) Very good accuracy without
array & programmable OR array putting extreme requirements
d) None of the above. on component stability
c) Poor rejection of power supply
Q.4 In the figure shown below the hums
circuit of a gate in the Resistor d) Better resolution compared to all
Transistor Logic (RTL) family. The other types of A / D converters
circuit represents for the same number of bits.
Q.8 Data in the serial form can be Q.15 In D/Aconverter, the resolution
converted into parallel form by required is 50mV and the total
using – maximum input is
a) PISO shift register 10V, the number of bits required is
b) SOIPshift register a) 7 b) 8
c) SIPO shift register c) 9 d) 200
d) POIS shift register
Q.16 A transistor is operated as a non-
Q.9 'Not allowed' condition in NAND saturated switch to eliminate
gate SR flip flop is a) Storage time b) turn- off
a) S = 0, R = 0 b) S = 1, R = 1 time
c) S = 0, R = 1 d) S = 1, R = 0 c) Turn-on time d) delay time
Q.10 Name the fastest logic family Q.17 The output Y of the circuit in the
a)TTL b) RTL given figure is –
c) DCTL d) ECL a) (A + B)C + DE b)
AB + C(D + E)
Q.11 The sequential circuit shown in Fig. c) (A + B)C + D + E d) (AB + C)DE
will act as a
Q.18 The Boolean expression for the
shaded area in the given Venn
diagram is –
a) Mod-1 counter
b) Mod-2 counter a) AB + BC + CA
c) Mod-3 counter b) (A + B)(B + C)(C + A)
d) Mod-4 counter
c) ABC + ABC + ABC
d) ABC
Q.12 The binary division 110002 ¸ 1002
gives
Q.19 (375)10 = (—)8
a) 110 b) 1100
c) 11 d) 101 a) 550 b) 557
c) 567 d) 577
Q.13 Identify the wrong statement?
a) 111002 – 100012 = 010112 Q.20 A pulse train with a frequency of 1
b) 15E16 = 35010 MHz is counted using a modulo
c) 8110 = 10100012 1024 ripple-counter with J-K flip-
d) 37.48 = 111 111.1002 flops. For proper operation of the
counter the maximum permissible
Q.14 In the 8421 BCD code the decimal propagation delay per flip-flop
number 125 is written as stages
a) 1111101 a) 100 n sec b) 50 n sec
b) 0001 0010 0101 c) 20 n sec d) 10 n sec
c) 7D
d) None of the above Q.21 The A/D convertor used in a digital
voltmeter could be
1) Successive approximation type a) Ex-OR gate b) AND gate
2) Flash convertor type c) NAND gate d) OR gate
3) Dual slope converter type
The correct sequence in the Q.27 If a counter having 10 FFs is initially
increasing order of their conversion at 0, what count will it hold after
time is 2060 pulses?
a) 1,2,3 b) 2,1,3 a) 000 000 1100 b)000 001
c) 3,2,1 d) 3,1,2 1100
c) 000 001 1000 d) 000 000
Q.22 What is the maximum clock 1110
frequency at which following circuit
can be operated without timing Q.28 A certain JK FF has tpd = 12 ns. The
violations? Assume that the largest MOD counter that can be
Combinational logic delay is 10 ns constructed from such FFs and still
and the clock duty varies from 40% operate up to 10 MHz is
to 60% a) 16 b) 256
c) 8 d) 128
Q.29 A 12 bit ADC is operating with a 1μs
clock period and the total
conversion time is seen to be 12μs.
The ADC must be of
a) Flash type
b) Counting type
a) 100 MHz b) 50 MHz
c) Integrating type
c) 40 MHz d) 25 MHz
d) Successive Approximation type
Q.23 For CMOS implementation of 2 input
Q.30 Which of the following ADCs uses
XOR logic gate, how many nMOS and
over sampling in its operation
pMOS transistors are required?
a) Sigma-delta ADC
a) 2 nMOS and 2 pMOS
b) Counter ramp convertor
b) 3 nMOS and 3 pMOS
c) Successive Approximation
c) 6 nMOS and 6 pMOS
Register
d) 8 nMOS and 8 pMOS
ADC
d) Flash Convertor
Q.24 A two input NOR gate has the
following states: A = 0, B = Not
Q.31 The characteristic equation of the T-
known. Then, the output will be
� FF is given by
a) A b) A
�
c) B d) B a) Q+ = T Q b) Q+ = T Q
c) Q+ = TQ d) Q+ =T Q + Q T
Q.25 According to Boolean algebra,
Q.32 A 5 bit DAC has a current output.
(ABCD + ABCD ) would be For a digital input of 10100, an
a) ABCD b) 0 output current of 10 mA is
c) 1 d) ��
ABCD produced. What will be the output
current for a digital input of 11101?
Q.26 Following diagram performs the a) 14.5 mA
logic function of b) 10 mA
c) 100 mA
d) Not possible to calculate
Q.33 For one of the following conditions, Q.38 The shift register shown in the given
clocked J-K flip-flop can be used as figure is initially loaded with the bit
DIVIDE BY 2 circuit where the pulse pattern 1010. Subsequently the shift
train to be divided is applied at register is clocked, and with each
clock input. clock pulse the pattern gets shifted
a) J = 1, K = 1 and the flip-flop by one bit position to the right. With
should have active HIGH inputs each shift, the bit at the serial input
b) J = 1, K = 1 and the flip-flop is pushed to the left most position
should have active LOW inputs (MSB). After how many clock pulses
c) J = 0, K = 0 and the flip-flop with the content of the shift register
should have active HIGH inputs become 1010 again?
d) J = 1, K = 1 and the flip-flop
should be a negative edge
triggered one
Q.34 Which of the following binary

number is equal to octal number
66.3?
a) 101101.100 b)1101111.111 a) 3 b) 7
c) 111111.1111 d) 110110.011 c) 11 d) 15
Q.35 The Boolean expression for the Q.39 The combinational logic circuit
output of the logic circuit shown in shown in the given figure has an
the figure is output Q which is
a) Y=AB+AB+C b) Y=A B+AB+C

c) Y=(AB+AB)C d) Y=AB+AB+C
a) ABC b) A + B + C
c) A ⊕ B ⊕ C d) A . B + C
Q.36 For the identity
AB + AC+BC=AB+AC, the dual Q.40 Determine the output voltage of a
form is network shown in figure if the
a) (A+B)(A+C)(B+C)=(A+B)(A+C) digital input is 101
b) (A+B)(A+C)(B+C)=(A+B)(A+C)
c) (A+B)(A+C)(B+C)=(A+B)(A+C)
d) A B+AC+BC=A B+AC
Q.37 A 4-bit presetable UP counter has

preset input 0101. The preset
operation takes place as soon as the
counter reaches 1111. The modulus
of the counter is a) −3.875 V b) −4.875 V
a) 5 b) 10 c) −5.875 V d) −6.875 V
c) 11 d) 15
Q.41 The sum S of A and B in a half Adder d) A 16 bit converter
can be implemented by using K Q.48 Which of the following statements
NAND gates. The value of K is are correct
a) 3 b) 4 1) A flip-flop is used to store 1 bit of
c) 5 d) None of these information
2) Race around condition occurs in
Q.42 The 8 bit DAC produces 1.0 V for a a J-K flip-flop when both the
digital input of 00110010. What is inputs are 1
the largest output it can produce? 3) Master-slave configuration is
a) 5V b) −5V used in flip-flops to store 2 bits
of information
c) 5.5 V d) 5.10 V 4) A transparent latch consists of a
D-type flip-flop
Q.43 The mod number of a Johnson a) 1, 2 and 3 b) 1, 3 and 4
counter will be always equal to the c) 1, 2 and 4 d) 2, 3 and 4
number of flip flops used
a) same Q.49 ow many 1’s are present in the
b) twice binary representation of 3 × 512 +
c) 2N where N is the number of flip 7 × 64 + 5 × 8 + 3?
flops a) 8 b) 9
d) None of the these c) 10 d) 11
Q.44 A S-R flip flop with a clock input can Q.50 For emitter-coupled logic, the
be converted to a ‘D’ flip flop using switching speed is very high
a) Two inverters because
b) The flip flop outputs (Q & Q ) a) Negative logic, is used
connected to its inputs (S & R) b) The transistors are not saturated
c) One inverter when conducting
d) Not possible c) Emitter-coupled transistors are
Q.45 A counter is designed with six stages used
of flip flops. Determine the output d) Multi-emitter transistors are used
frequency at the last (sixth) stage,
when input frequency is 1 MHz. Q.51 10 bit A/D converters, the
a) 1MHz b) 166 KHz quantization error is given by (in
c) 15.625 KHz d) zero percent)
a) 1 b) 2
Q.46 Minimum number of 2-input NAND c) 0.1 d) 0.2
gates that will be required to
implement the function: Y = AB + CD Q.52 For the switch circuit, taking open
+ EF is as 0 and closed as 1, the expression
a) 4 b) 5 for the circuit is Y.
c) 6 d) 7
Q.47 The resolution of a D/A converter is

approximately 0.4% of its full-scale
range. It is a) A + (B + C) D b) A + BC + D
a) An 8-bit converter c) A (BC + D) d) None of these
b) A 10-bit converter
c) A 12 bit converter
Q.53 The Boolean expression for the LOW only when A is HIGH while B
shaded area in the Venn diagram is and C are different. The logic
expression for the circuit is
a) A + BC’ + B’C
b) A (XOR) B
� . B(XNOR)C
c)A
�+�
a)X Y + Z� b)XY�Z + �
XYZ d) A.B(XOR)C
c) X + Y + Z �Y
d) X� Z + XY
Q.60 The specifications given for a TTL
Q.54 Given the decimal number −19, an logic family gate are as
eight bit two’s complement follows: IOH = − 40 μA , IOL =
representation is given by 8 mA , IIH = 2μA , and IIL =
a) 11101110 b) 11101101 − 0.36 mA. The fan-out of the gate
c) 11101100 d) None of is
these a) 10 b) 18
c) 20 d) 22
Q.55 The function shown in the figure
when simplified will yield a result Q.61 In the logic equation
with A(A + BC + C) + B(C + A + BC)(A + BC + AC) =
1,
if C = A then
a) A + B = 1 b) A + B = 1
c) A + B = 1 d) A = 1
a) 2 terms b) 4 terms Q.62 A 4-bit serial –in –parallel –out shift

c) 7 terms d) 16 terms register is used with a feedback as
shown in fig.
Q.56 The simplified equivalent of the The shifting sequence is QA
Logic expression: →QB→QC→QD. If the output is 0000
x = (C + D)’ + A’CD’ + AB’C’ + A’B’CD initially, the output repeats after
+ ACD’
a) x = D’ + AB’C’ + A’B’C
b) x = D + AB’C’ + A’B’C
c) x = D’ + A’B’C’ + A’BC’
d) None of the above
Q.57 The hexadecimal equivalent of the

binary number 11 1011 0111 1010 a) 4 clock cycles b) 6 clock
is cycles
a) EDE8H b) FB7AH c) 15 clock cycles d) 16 clock
c) 3B7AH d) 3557H cycles
Q.58 The address bus width of a memory Q.63 The complement of the Boolean
of size 1024 × 8 bits is
expression F = (X + Y + Z)( X + Z )
a) 8-bits b) 10-bits
(X + Y) is
c) 12-bits d) 16-bits
a) XYZ + X Z + Y Z
Q.59 A logic circuit has three inputs A, B, b) X Y Z + XY + X Y
C and an output Y. The output goes c) X Y Z + XZ + Y Z
d) XYZ + X Y a) Gray code
Q.64 The Boolean function F(A, B, C, D) = b) Excess 3-code
∑ (0,6,8,13,14) with don’t care c) BCD
conditions d(A,B,C,D) = ∑ (2,4,10) d) Error detecting code
can be simplified to
Q.70 In the Karnaugh map shown above,
a) F = B D + C D + AB C the minimal output X is
b) F = B D + C D + AB C D
c) F =A B D + C D + AB C
d) F = B D + C D + ABCD
Q.65 For which one of the following

ultraviolet light is used to erase the __ __ ___ __
second contents? = A B CD + A B + AB C
a) X
a) PROM b) EPROM __ __ __
b) X = B C + A B + A CD
c) EEPROM d) PLA
__ __ __ __ __ __ __
c) X = B C D + A B C + AB C + A BC D
Q.66 Which one of the following is Not a
__ __
synchronous counter? d)=
X BC+AC
a) Johnson counter
b) Ring counter
Q.71 2’s complement of a given 3 or more
c) Ripple counter
bit binary number of non-zero
d) Up-Down counter
magnitude is the same as the
original number if all bits except the
Q.67 The circuit shown in the given figure is
a) MSB are zeros b) LSB are zeros
c) MSB are ones d) LSB are ones.
Q.72 In the figure shown , X2 X1 X0 will be

1’s complement of A2 A1 A0 if
a) An AND gate b)An OR gate

c) A XOR gate d) A NAND gate
Q.68 What are the values respectively, of

a) Y = 0
R1 and R2 in the expression
b) Y = 1
(235)R1 = (565)10 = (865)R2
a) 8, 16 b) 16, 8 c) Y=A 0 =A1 =A 2
c) 6, 16 d) 12, 8 d) Y=A 0 =A1 =A 2
Q.69 The logic circuit shown converts y1 . Q.73 In a digital system, there are three
y2 into : inputs A, B and C. The output should
be high when at least two inputs are
high. The Boolean expression for the
output is:
a) AB + BC + AC
b) ABC + ABC + ABC + ABC
c) ABC + AB C + A BC Q.78 The black box in the above figure
consists of a minimum complexity
d) AB +BC + A C
circuit that uses only AND, OR and
Q.74 If (327)9 = (x)5 then the value of x NOT gates. The function f,(x, y, z) = 1
is given by whenever x, y are different and 0
a) 327 b) 268 otherwise. In addition the 3 inputs x,
c) 2033 d) 3302 y, z are never all the same value.
Which one of the following
Q.75 Consider the following Boolean equations leads to the correct
function of four variables: design for the minimum complexity
f (w, x, y, z) = ∑ (1,3, 4, 6,9,11,12,14) circuit?
The function is
a) Independent of one variable
b) independent of two variables
c) Independent of three variables
d) dependent on all the variables. a) x’y + xy’ b) x + yz’
c) x’y’z + xy’z d) xy + y’z + z’
Q.76 Given f1, f3 and f in canonical sum of
products form (in decimal) for the Q.79 When the Boolean function F(x1 x2 x3)
circuit = ∑ ( 0, 1, 2, 3) + ∑ ϕ (4,5, 6, 7) is
= f1 ∑ = m(4,5, 6, 7,8) f3 ∑ m(1, 6,15)
minimized, what does one get?
f = ∑ m(1, 6,8,15) a) 1 b) 0
Then f2 is c) x1 d) x3
Q.80 The circuit shown above generates

the function of
a)∑ m(4,6) b)∑ m(4,8)

c)∑ m(6,8) d)∑ m(4,6,8)
Q.77 Which of the following Maps

correctly represents the expression a) x ⊕ y b) 0
ad + a c + bcd ? c) xy + yx + yx d) x.y
Q.81 Which one of the following Boolean
expression is NOT correct?
a) x + y =x y b) x + y =
x.y
a) b) c) x y= x + y d) x + y =xy
Q.82 The minimized form of the Boolean

expression F(A, B, C) = Π (0, 2, 3) is
a) A + BC b) A + BC
c) AC + B d) A B C + AB
c) d)
Q.83 Consider the following circuit:
Which one of the following gives the
function implemented by the MUX-
based digital circuit
a) X0X2 b) X1X3
c) X1+X3 d) X0+X2
a) f = C2 .C1.S+C2 .C1.(A+B)
Q.88 Consider the following expressions:
b) f = C2 .C1 +C2 .C1 +C2 .C1.S+C2 .C1.AB 1. Y = f (A, B, C, D) =
c) f =AB+S ∑ (1, 2, 4, 7, 8, 11, 13, 14)
d) f = C2 .C1 +C2 .C1.S+C2 .C1.AB 2. Y = f (A, B, C, D) =
∑ (3, 5, 7, 10, 11, 12, 13, 14)
Q.84 How many min terms (excluding 3. Y = f (A, B, C, D) =
redundant terms) do minimal π (0, 3, 5, 6, 9, 10, 12, 15)
switching functionf(v, w, x, y, z) = x 4. Y = f (A, B, C, D) =
+ y z originally have? π (0, 1, 2, 4, 6, 8, 9, 15)
a) 16 b) 20 Which of these expression are
c) 24 d) 32 equivalent to the expression, Y =
A ⊕ B ⊕ C ⊕ D?
Q.85 Consider the following circuit: In the
a) 2 and 3 b) 1 and 4
circuit TTL circuit, S2 and S0 are
c) 2 and 4 d) 1 and 3
select lines and X7 to X0 are input
lines. S0 and X0 are LBSs. What is the
Q.89 In the circuit shown in the figure,
output Y?
Q=0 initially. When clock pulses are
applied, the subsequent states of ‘Q’
will be
a) Indeterminate b) A ⊕ B
c) A ⊕ B d) C ⊕ B ⊕ A a) 1,0,1,0,…… b) 0,0,0,0,……
Q.86 To add two m-bit numbers, the c) 1,1,1,1,…… d) 0,1,0,1,……
required number of half adders is
a) 2m -1 b) 2m – 1 Q.90 A divide–by-78 counter can be
c) 2 m + 1 d) 2m realized by using
a) 6 nos of mod-13 counters
Q.87 For the diode matrix shown in the b) 13 nos of mod-6 counters
figure, the output Y1 will be c) one mod-13 counter followed by
one mod-6 counters
d) 13 nos of mod-13 counters
Q.91 The block diagram shown in the

given figure represents
Q.96 What is represented by the digital
circuit given above?
a) Modulo-3 ripple counter.

b) Modulo-5 ripple counter a) An SR flip-flop with A = S & B = R
c) Modulo-7 ripple counter b) A JK flip-flop with A = K & B = J
d) Modulo-7 synchronous counter c) A JK flip-flop with A = J & B = K
d) An SR flip-flop with A = R & B = S
Q.92 In a ripple counter, the stage whose
Q.97 Which one of the following is TRUE?
output has a frequency equal to
a) Both latch and flip –flop are edge
1/8th that of the clock signal applied
triggered
to the first state. The counter is
b) A latch is level triggered and a
a) Modulo-8 b) Modulo-6
flip-flop is edge triggered
c) Modulo-64 d) Modulo-16
c) A latch is edge triggered and a
flip-flop is level triggered
Q.93 The initial state of MOD-16 DOWN
d) Both latch and flip-flop are level
counter is 0110. After 37 clock
triggered
pulses, the state of the counter will
be
Q.98 In fig, U1 is a 4-bit binary
a) 1011 b) 0110
synchronous counter with
c) 0101 d) 0001
synchronous clear. Q0 is the LSB and
Q3 is the MSB of the output. The
Q.94 The circuit given is that of a:
circuit shown in fig represents a
a) Mod-5 counter b) Mod-6 counter a) mod 2 counter b) mod 3 counter

c) Mod-7 counter d) Mod-8 counter c) mod 4 counter d) mod 5 counter
Q.95 The counter shown in the above Q.99 For a six ladder D/A converter
figure has initially Q2Q1Q0=000. the which has digital input of 101001,
status of Q2Q1Q0 after the first pulse the analog value is (assume 0=0V
is and 1 = +10V)
a) 0.423 b) 0.552
c) 6.41 d) 0.923
Q.100 In a 4-bit weighted-resistor D/A
converter, the resistor value
corresponding to LSB is 16 kW. The
resistor value corresponding to the
a) 001 b) 010 MSB will be
c) 100 d) 101 a) 1 k Ω b) 2 k Ω
c) 4 k Ω d) 16 k Ω.
Q.101 The resolution of an-n-bit D/A b) Propagation delay time × power
converter with a maximum input of dissipation
5 V is 5 mV, The value of `n` is c) Gain out × propagation delay
a) 8 b) 9 time
c) 10 d) 11 d) Noise margin × power
dissipation
Q.102 Match List I with List II and select
the correct answer using codes Q.105 Match List I (Logic gates) with List I
given below the lists: (Operation) and select the correct
List I answer using codes given below the
(Types of A/D converters) lists:
1. Fixed conversion time; depends List I(Logic Gates)
on the no. bits (A) TTL
2. High speed operation (B) ECL
3. Conversion time dependent on (C) HTL
amplitude (D) CMOS
List II List II(Operation)
(Properties of A/D converters) 1.More logical swing
A. Dual Slope 2.Low power dissipation
B. Counter-Ramp 3.Current hogging
C. Successive Approximation 4. NOR/OR output
D. Simultaneous 5. Totem-pole output
4. Large conversion time Code: A B C D
Codes: a) 3 2 5 1
A B C D b) 3 2 4 5
a) 3 2 1 4 c) 2 3 4 5
b) 2 3 4 1 d) 5 4 1 2
c) 3 4 1 2
d) 4 1 2 3 Q.106 Match List I with List II and select
the correct answer using the codes
Q.103 For a logic family given below the lists :
VOH is the minimum output high List I
level voltage A. TTL
VOL is the maximum acceptable B. ECL
input low level voltage C. MOS
VIH is the minimum acceptable input D.CMOS
high level voltage List II
VIL is the maximum acceptable input 1. Low propagation delay
low level voltage 2. Low power consumption
The correct relationship among 3. Higher packing density on Si
these is: wafer
a) VIH> VOH> VIL> VOL 4. Saturated bipolar logic High fan
b) VOH> VIH> VIL> VOL out
c) VIH> VOH> VOL> VIL Codes: A B C D
d) VOH> VIH > VOL> VIL a) 4 1 3 2
b) 5 3 2 1
Q.104 The figure of merit of a logic family c) 4 3 2 1
is given by d) 5 1 3 2
a) Gain × bandwidth
Q.107 Consider the following statements in
respect of ECL gate: List-I List-II
1. Its switching speed is high (type of gates) (values of propagation delay)
2. It provides OR and NOR logic A. ECL 1) 5ns
B. TTL 2) 20 ns
operations
C. CMOS 3) 100 ns
3. Its power dissipation is small as D. NMOS 4) 1 ns
compared to other logic gates Codes: A B C D
4. Its logic levels are compatible a) 1 4 3 2
with other logic family gates b) 4 1 3 2
Which of these statements are correct?
c) 1 4 2 3
a) 1 and 2 b) 1, 2 and 3 d) 4 1 2 3
c) 1, 2 and 4 d) 3 and 4
Q.112 The noise margin of a digital IC is the
Q.108 The above-shown NMOS circuit is a a) Maximum frequency of
gate of the type extraneous voltage that does not
cause a gate to change its state
b) Maximum extraneous voltage
that does not cause a gate to
change its state
c) Thermal noise voltage which
causes a gate to change its state
a) NAND b) NOR d) Minimum frequency of
c) AND d) EXCLUSIVE-OR extraneous voltage that cause a
gate to change its state
Q.109 Consider the following statements:
1. TTL has high switching speed
Q.113 A 4-bit twisted Ring counter is
and good fan-out capability.
loaded with an initial value of 1000.
2. ECL has the least propagation
Clock pulses are applied to its clock
delay.
input. The state of the counter at the
3. I2L uses multi-collector transistors.
end of 4th clock pulse is
Which of the following statements is
a) 0001 b) 1000
correct?
c) 1111 d) 0111
a) 1. 2 and 3 b) 2 and 3
c) 1 and 3 d) 1 and 2
Q.110 The open collector output of two 2-
input NAND gates are connected to a
common pull-up resistor. If the
inputs of the gates are A, B and C,D
respectively, the output is equal to
a) A.B ⋅ C.D b) A.B + C.D
c) A.B + C.D d) A.B ⋅ C.D
Q.111 Match list-I (type of gates) with list-

II (values of propagation delay) and
select the correct answer using the
codes given below the lists:
ANSWER KEY (DIGITAL):
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
(b) (b) (c) (d) (c) (c) (b) (c) (b) (d) (c) (a) (d) (b) (b)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(b) (c) (c) (c) (d) (b) (c) (c) (c) (c) (b) (a) (b) (d) (a)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
(d) (a) (d) (d) (c) (c) (b) (b) (b) (d) (b) (d) (b) (c) (c)
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
(c) (a) (c) (b) (b) (c) (c) (d) (b) (c) (b) (c) (b) (c) (c)
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
(c) (b) (c) (b) (b) (c) (b) (b) (a) (b) (a) (b) (a) (c) (b)
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
(c) (a) (a) (a) (a) (d) (a) (d) (c) (b) (a) (c) (d) (a) (c)
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
(c) (a) (d) (a) (c) (c) (b) (c) (c) (b) (c) (c) (b) (b) (d)
106 107 108 109 110 111 112 113
(a) (a) (a) (a) (a) (b) (b) (d)
EXPLANATIONS
Q.1 (b) 0.375 × 2 =0.75 →0

0.75 × 2 =1.50 →1
0.50 × 2 =1.00 →1
∴ ( 5.375 )10 =(101.011)2
Q.7 (b)
Dual slope integration type A to D
converters is of slow speed and has
a very good accuracy.
Q.2 (b) Q.8 (c)
The expression for output is given
by Q.9 (b)
F = ABC + ABC + ABC + AB
⇒= (
F AC B + B + AC B + B ) ( ) Q.10 (d)
ECL is non-saturated logic family
⇒ F= AC + AC
⇒ F =A ⊕ C Q.11 (c)
Clk 𝐉𝐉𝟏𝟏 𝐊𝐊 𝟏𝟏 𝐐𝐐𝟏𝟏 𝐉𝐉𝟐𝟐 𝐊𝐊 𝟐𝟐 𝐐𝐐𝟐𝟐
Q.3 (c) 0 1 1 0 0 1 0
1 1 1 1 1 1 0
Q.4 (d) 2 0 1 0 0 1 1
3 1 1 0 0 1 0
𝐕𝐕𝐢𝐢𝐢𝐢 𝐕𝐕𝐢𝐢𝐢𝐢 𝐓𝐓𝟏𝟏 𝐓𝐓𝟐𝟐 𝐓𝐓𝟑𝟑 𝐕𝐕𝐎𝐎 4 1 1 1 1 1 0
0 0 OFF OFF ON 0 As there are 3 different states of
0 1 OFF ON OFF Vcc Q1Q 2 i.e. 00, 10 & 01 therefore it is
1 0 ON OFF OFF Vcc
a MOD-3 counter.
1 1 ON ON OFF Vcc
Q.12 (a)
Q.5 (c)
Clk 𝐐𝐐𝟑𝟑 𝐐𝐐𝟐𝟐 𝐐𝐐𝟏𝟏 𝐐𝐐𝟎𝟎
Q.13 (d)
0 0 1 1 0
37.48 = 011111.1002
1 1 0 1 1
2 0 1 0 1 Q.14 (b)
3 1 0 1 0 In BCD code
1 ⇒ 0001
Q.6 (c) 2 ⇒ 0010
Dividing 5 by 2 5 ⇒ 0101
2 5 ∴ 125 = ( 000100100101)BCD
2 2 1
2 1 0 Q.15 (b)
0 1 10V
Now, multiplying .375 by 2 50mV =
2n − 1
⇒ 2n = 199
∴ n = 8bits Q.23 (c)
Q.16 ( b)
Q.17 (c)
Q.18 (c)
Q.24 (c)
Q.19 (c) For NOR gate the truth table is
8 375 A B Y
8 46 7 0 0 1
8 5 6 0 1 0
0 5 Therefore output is complement of
∴ (375)10 =
(567)8 B.
Q.20 (d) Q.25 (c)

In modulo 1024 counter there will (ABCD + ABCD )=1
be 10 flip flops. For ripple counter
TClk ≥ 10t pd Q.26 (b)
TClk
∴ t pd ≤ = 10−7 = 10nsec Q.27 (a)
10 The modulo count for 10 flip-flops is
1024 i.e. after every 1024 clock
Q.21 (b) pulses the counter will be reset. It
will reset again after 2048 clk
Q.22 (c) pulses.
TON 2060 − 2048 = 12 therefore the count
= 40% = 0.4
TClk will be 000 000 1100
The second flip flop will operate
when clk goes low & before this the Q.28 (b)
combinational should produce its TClk ≥ nt pd
final output .e.TON ≥ 10nsec . TClk
TON ⇒ n≤
= 40% = 0.4 t pd
TClk ⇒ n ≤ 8.33
T
⇒ TClk = ON =
1 Considering n = 8 , the modulo
0.4 40 ×106 count is
f Clk = 40MHz 28 = 256
Q.29 (d) Q.38 (b)
In successive approximate type ADC Clk 𝐐𝐐𝟑𝟑 𝐐𝐐𝟐𝟐 𝐐𝐐𝟏𝟏 𝐐𝐐𝟎𝟎
the number of clock cycles required 0 1 0 1 0
1 1 1 0 1
for conversion is equal to the
2 0 1 1 0
number of bits. 3 0 0 1 1
4 0 0 0 1
Q.30 (a) 5 1 0 0 0
6 0 1 0 0
Q.31 (d) 7 1 0 1 0
Q.32 (a) Q.39 (b)

o F = ABC + AB.1 + AB1 + AB.1
= resolution ×
Analog
p ⇒ F = ABC + AB + A B + B ( )
decimal equivalent of digital i / p
⇒ F = ABC + AB + A
=
10mA resolution × 20 ⇒ F = A+B+C
∴ resolution = 0.5mA
Analogo /=p 0.5mA × 29 = 14.5mA Q.40 (d)
100
Q.33 (d) V0 =- ( 5+2×5+4×0+8×5)
800
For the above purpose the flip flop =-6.875V
must be edge triggered.
Q.41 (b)
Q.34 (d) S= A ⊗ B
68 = 1102 An XOR gate will be implemented
38 = 0112 using 4 NAND gates.
∴ 66.38 = 110110.0112
Q.42 (d)
Q.35 (c) = Vr resolution × decimal equivalent of digital i / p
= 1V resolution × 50
Q.36 (a) ∴ resolution = 20mV
While finding dual, OR operator is Full scale output= 20mV × ( 28 − 1) = 5.10V
replaced with AND operator & vice
versa. Q.43 (b)
Q.37 (b) Q.44 (c)
Clk 𝐐𝐐𝟑𝟑 𝐐𝐐𝟐𝟐 𝐐𝐐𝟏𝟏 𝐐𝐐𝟎𝟎
0 0 1 0 1 Q.45 (c)
1 0 1 1 0 f=
f clk
= 15.625KHz
2 0 1 1 1
out
26
3 1 0 0 0
Q.46 (c)
4 1 0 0 1
5 1 0 1 0
6 1 0 1 1
7 1 1 0 0
8 1 1 0 1
9 1 1 1 0
10 0 1 0 1
Q.47 (a) A B C Y
1 0.4 0 0 0 1
=
% resolution =
2 − 1 100
n
0 0 1 1
∴ n = 8bits 0 1 0 1
0 1 1 1
Q.48) (c) 1 0 0 1
1 0 1 0
Q.49 (b) 1 1 0 0
3 × 512 + 7 × 64 + 5 × 8 + 3 1 1 1 1
= 3 × 83 + 7 × 82 + 5 × 8 + 3
This is the expansion of (3753)8
Y= ( A + B + C )( A + B + C )
= (011111101011) 2 =A ( B + C )( B + C )
Y= A. ( BC + BC )= A.B e C
Q.50 (b)
Q.51 (c) Q.60 (c)

Quantization error is equal to 1 LSB =
Fanout high
IOH 40μA
= = 20
i.e. resolution. I IH 2μA
IOL 8mA
Q.52 (c) = =
Fanout low = 22
I IL 0.36mA
Q.53 (d) Fanout is the minimum of both i.e. 20
Q.54 (b) Q.61 (c)

+19 = 00010011 ( ) (
A A + BC + C + B C + A + BC )
−19 =
( A + BC + AC ) =
11101101
(by taking 2’s complement) 1
If C = A
Q.55 (c)
( ) (
A A + BA + A + B A + A + BA )
Q.56 (b)
(A + BA + AA) =
1
x =( C + D )’ + A’CD’ + AB’C’ + A’B’CD + ACD’
x= C’ D’ + AB’C’ + A’B’CD + ( A + A’) CD’
(
A (1) + B(1) A + B =
1 )
A + AB + B =
x= AB’C’ + A’B’CD + ( C + C’) D’
1
A+B= 1
x= AB’C’ + ( A’B’CD + D’)
x = AB’C’ + A’B’C + D’ Q.62 (b)
Clk 𝐐𝐐𝐀𝐀 𝐐𝐐𝐁𝐁 𝐐𝐐𝐂𝐂 𝐐𝐐𝐃𝐃
Q.57 (c) 0 0 0 0 0
= 0011 → 31011
11101101111010 1 1 0 0 0
→ B0111 → 71010 → A 2 1 1 0 0
3 0 1 1 0
Q.58 (b) 4 0 0 1 1
1024 = 210 hence there are 10 5 0 0 0 1
address lines. 6 0 0 0 0
Therefore output repeats after 6
Q.59 (c) clock pulses.
Q.63 (c) Q.74 (c)
=
(327) 9 =
(268)10 (2033)5
Q.64 (b)
Q.75 (b)
F = BD + CD + ABCD
Q.65 (b) =
f xz ' + x ' z
An EPROM can be erased by
exposing it to strong ultraviolet light Q.76 (c)
source (such as from a mercury-
vapor light). Q.77 (a)
Q.66 (c) Q.78 (a)

x y z f
Q.67 (b) 0 0 0 x
0 0 1 0
Q.68 (b) 0 1 0 1
R1 > R 2 so option b or d is correct. 0 1 1 1
( 235)16 = 5 + 3 ×16 + 2 × 256 1 0 0 1
= (565)10 1 0 1 1
1 1 0 0
(865)8 = 5 + 6 × 8 + 8 × 64 = (565)10 1 1 1 x
Q.69 (a) Solving for f using K-map we get
=f x ' y + xy '
Q.70 (b)
Q.79 (a)
Q.71 (a)
Q.80 (a)
Q.72 (b)
A ⊕ 1 =A
Q.73 (a)
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1 Q.81 (d)
1 1 0
1 1 1
1
1 ( x + y) = x.y = x.y
Y = AB + BC + AC
Q.82 (a) Different clock pulse is applied to
different flip flops hence it is a
ripple counter.
Q.92 (a)
In MOD-N counter the output
Q.83 (d) frequency
= ( )
f C2 C1.1 + C2 C1 A + B + C2 C1S + C2 C1.0
is f out = f Clk / N
⇒ f=
C2 C1 + C2 C1 AB + C2 C1S( ) Q.93 (d)
After 16 & 32 clock pulses the
Q.84 (c) counter will come to its initial stage
In canonical SOP form f can be i.e. 0110
written as 𝐂𝐂𝐂𝐂𝐂𝐂 𝐐𝐐𝟑𝟑 𝐐𝐐𝟐𝟐 𝐐𝐐𝟏𝟏 𝐐𝐐𝟎𝟎
32 0 1 1 0
33 0 1 0 1
( )( )( )(
f = x v + v w + w y + y z + z + yz ) 34 0 1 0 0
( v + v )( w + w )( x + x ) 35 0
36 0
0
0
1
1
1
0
Solving this there will be 24 min
37 0 0 0 1
terms
Q.94) (a)
Q.85 (b)
The counter in the figure is 3 bit
In TTL logic gate the floating input is
ripple UP counter & it will reset
considered as logic 1 therefore S2 = 1
when count is 101 hence it is a
. MOD-5 counter.
𝐒𝐒𝟐𝟐 𝐒𝐒𝟏𝟏 𝐒𝐒𝟎𝟎 Y
1 0 0 0 Q.95 (c)
1 0 1 1 =
Here J 2 Q=
1, K2 Q0
1 1 0 1
1 1 1 0
𝐂𝐂𝐂𝐂𝐂𝐂 𝐉𝐉𝟐𝟐 𝐊𝐊 𝟐𝟐 𝐉𝐉𝟏𝟏 𝐊𝐊 𝟏𝟏 𝐉𝐉𝟎𝟎 𝐊𝐊 𝟎𝟎 𝐐𝐐𝟐𝟐 𝐐𝐐𝟏𝟏 𝐐𝐐𝟎𝟎
From the truth table the expression
0 1 0 0 1 0 1 0 0 0
for Y is
1 1 0 0
Y =S1 ⊕ S0 = A ⊕ B
Q.86 (a) Q.96 (c)

=
T AQ + BQ
Q.87 (c) Now for T flip flop the
characteristics equation is
Q.88 (d) Q n= TQ + TQ
+1
Q.89 (a) ( ) (
⇒ Q n +1 = AQ + BQ Q + AQ + BQ Q )
Q.90 (c) ⇒ Q n +1 = AQ + ( A + Q )( B + Q ) Q
When MOD-M & MOD-N counters Q= AQ + BQ
n +1
are cascaded the resulting counter is
It is similar to characteristics
MOD-MN counter
equation of JK flip flop if J=A &
K=B
Q.91 (c)
Q.97 (b) Current hogging is the problem of
DCTL family.
Q.98 (c)
Q.106 (a)
Clk 𝑸𝑸𝟑𝟑 𝑸𝑸𝟐𝟐 𝑸𝑸𝟏𝟏 𝑸𝑸𝟎𝟎
0 0 0 0 0 Q.107 (a)
1 0 0 0 1 It has highest power dissipation &
2 0 0 1 0 its logic levels are not compatible to
3 0 0 1 1 other logic gates.
1 (counter will
4 0 0 0 Q.108 (a)
reset)
There are 4 different counts hence it
is a A B 𝐓𝐓𝟐𝟐 𝐓𝐓𝟑𝟑 Y
MOD-4 counter 0 0 OFF OFF 1
0 1 OFF ON 1
Q.99 (c) 1 0 ON OFF 1
Ana log output = 1 1 ON ON 0
resolution × decimal equivalent of digital input
Q.109 (a)
10
Ana log output = 6 × 41 = 6.41V
2 Q.110 (a)
With open collector output a TTL
Q.100 (b) NAND gate perform wired AND
operation.
Q.101 (c)
full scale output Q.111 (b)
Re solution =
2n − 1
⇒ 5mV = n
5V Q.112 (b)
2 −1
⇒ 2n − 1 =1000 Q.113 (d)
⇒ n = 10 The truth table of twisted ring
counter is
Q.102 (c) Clk Q3 Q2 Q1 Q0
Converter Maximum Time 0 1 0 0 0
Simultaneous No clock pulse require 1 1 1 0 0
Successive
2 1 1 1 0
Approximation n × TClk
3 1 1 1 1
Counter-Ramp 2n × TClk
4 0 1 1 1
(Conversion time depends on
amplitude)
Dual Slope 22n × TClk (Slowest)
Q.103 (b)
Q.104 (b)
Q.105 (d)
ASSIGNMENT QUESTIONS (MICROPROCESSOR)
Q.1 In an 8085 microprocessor system Memory address in Hex

with memory mapped I / O Instruction
1) I / O devices have 16-bit 2000 LXI SP, 1000
addresses 2003 PUSH H
2) I / O devices are accessed using 2004 PUSH D
IN and OUT instructions 2005 CALL 2050
3) There can be a maximum of 256 2008 POP H
input devices and 256 output 2009 HLT
devices As the completion of execution of
4) Arithmetic and logic operations the program, the program counter
can be directly performed with of the 8085 contains ………, and the
the I / O data. stack pointer contains ……..
Select the correct answer using the a)2050, OFFC b)200A, OFFE
codes given below: c)1025, OCCF d)1025, OCCF
a) 1, 2 and 4 b) 1, 3 and 4
c) 2 and 3 d) 1 and 4 Q.6 A 32 bit microprocessor has the
word length equal to
Q.2 An ‘Assembler’ for a microprocessor a) 2 bytes b) 1 byte
is used for c)4 bytes d) 8 bytes
a) assembly of processors in a
production line Q.7 The data bus in 8080A / 8085
b) creation of new programs using microprocessor is a group of
different modules a) Eight bidirectional lines that are
c) translation of a program from used to transfer 8 bits between
assembly language to machine the microprocessor and its I / O
language and memory.
d) translation of a higher level b) Eight lines used to transfer data
language into English text among the registers
c) Eight unidirectional lines that
Q.3 An I/O processor control the flow of are used for I / O devices.
information between d) Sixteen bidirectional lines that
a) Cache memory and I / O devices are used for data transfer
b) Main memory and I / O devices between the microprocessor and
c) Two I / O devices memory
d) Cache and main memories
Q.8 Consider the following connection
Q.4 An instruction used to set the carry to memory. The accessible range of
Flag in a computer can be classified address from the memory is
as
a) data transfer
b) arithmetic
c) logical
d) program control
Q.5 The following program is run on an
8085 microprocessor,
a) 0000 – 0FFF b) IFFF – 4FFF a) at the address contained in the
c) 0000 – FFFF d) 0000 – 4FFF register pair
b) in the register pair
Q.9 Consider the following set of c) in the accumulator
instructions: d) in a fixed location of the memory
STC
CMC Q.13 The Bit position of AC flag in flag
MOV A, B register is-
RAL a) D2 b) D4
MOV B, A c) D6 d) D7
This set of instructions
a) doubles the number in Register Q.14 In which arithmetic operation CY
by B flag do not affect even if result is
b) Divides the number in Register larger than 8 bit
by 2. a) INR B b) ADD A, B
c) multiples B by A c) SUB A, B d) None
d) Adds A and B.
Q.15 A stack means
Q.10 The range of the address of the RAM a) an 8 bit register in
which is interfaced to a microprocessor
microprocessor as shown in Fig. is b) a 16 bit memory address in
memory
c) a 16 bit register in
microprocessor.
d) a set of memory location in
memory reserved for storing
information temporarily.
Q.16 RIM instruction

a) checks pending interrupts
b) sets the interrupt mask
a)1400-17FF b) E400-EFFF
c) resets the RST interrupt
c) F000-F3FF d) F400-F7FF
d) none of above
Q.11 After the execution of the following
Q.17 A signal generated by
program in the 8085
microprocessor to provide timing of
microprocessor, the contents of the
various operation is
accumulator are
transmittedthrough
Address Code Mnemonics
a) Address bus.
203A 3E 20 MVI A, 20H
b) Data bus
203C 2A 3A 20LHLD 203AH
c) Control bus
203F 86 ADD M
d) in built signal no need to transmit
2040 76HLT
a) 20H b) 40H
Q.18 On execution of RAL-
c) 5EH d) 7CR
a) Each bit is shifted right to the
adjacent position bit Do becomes
Q.12 In the register indirect addressing
Dy
mode of 8085 microprocessor, data
b) Each bit is shifted right to
is stored
adjacent position bit Do becomes
the carry bit and carry bit is a) Time require to execute set of
shifted into DT instructions
c) Each bit is shifted to adjacent left b) Time require to execute one
position. Bit DT becomes Do instruction
d) Each bit is shifted to the adjacent c) Time require to complete one
left position. Bit DT becomes the operation of accessing memory,
carry bit and the carry bit is or I/o
shifted into Do d) None of above
Q.19 An arithmetic operation in the 8085 Q.26 If the clock frequency is 5 MHz, how
microprocessor sets the sign and much time is required to execute on
parity flags. The contents of the instruction of 18T states
accumulator after the execution of a)3.6 µsec. b) 3.6 msec.
the operation can be c) 0.36 µsec. d) 36 µsec.
a) 1011 0100 b) 0010 1101
c) 1010 1101 d) 0110 0111 Q.27 In data transfer operation which flag
gets affected
Q.20 An instruction of the 8085 a)Zero flag b)Carry flag
microprocessor that requires both c)Sign flag. d) None
memory read and memory write
machine cycles is Q.28 CMP instruction comes under group
a) MVI M, 8F b) LHLD 8088 a)Data transfer
c) RST 1 d) ADD M b)Branching operations
c) Machine control operation
Q.21 The duration of one T-state in the d) Logical operations
8085 microprocessor that uses a Q.29 The logic operation
crystal of 5.00 a) are performed in relation to
MHz is content of Accumulator
a)0.2μs b)0.4 μs b) can be performed directly with
c)2.5μs d)5.0 μs content of the register.
c) are performed without content
Q.22 Intel's 8085 microprocessor chip of a
contains d) none of above.
a) seven 8 bit registers
b) 8 seven bits registers Q.30 What happen when PUSH
c) seven 7 bit registers instruction executed
d) eight 8 bit registers. a) data retrieved from stack to
register
Q.23 The number of hardware interrupts b) data from register saved on the
(which require an external signal to stack.
interrupt) present in 8085 c) 16 bit address of instruction
microprocessor are saved on stock.
a) 1 b) 4 d) 16 bit address from stock
c) 5 d) 13 retrieved
Q.24 Highest priority interrupt is Q.31 SIM stands for

a) INTR b)RST 7.5 a) serial interface memory
c) RST 6.5 d)TRAP b) set interrupt mask
c) set if minus
Q.25 One instruction cycle means d) set internal memory
Q.32 Maximum clock frequency required c) the call location is determined by
to operate 8085 an external device
a )2 MHz b) 3 MHz d) the program is transferred to a
c) 6 MHz d) 9 MHz call location indicated by HL
register pair.
Q.33 In memory mapped I/O address
lines are Q.39 When a microprocessor interfaces
a) 8 b) 16 with a peripheral or memory device,
c) 32 d) 64 the normal timing of the
microprocessor may need to be
Q.34 The parity bit adding technique is altered by introducing __________
used for a) Latching
a)Indexing b)Coding b) Wait states
c)Error detection d)Controlling c) Tristate logics
d) None of the above
Q.35 While executing program
microprocessor checks INTR line Q.40 A microprocessor with 12-bit
clearing address bus will be able to access
a)each instruction kilobytes of memory
b) after interval of two instruction a) 0.4 b) 2
c) after a subroutine c) 10 d) 4
d) at the end of program.
Q.41 A ‘DMA’ transfer implies
Q.36 In a microprocessor the register a) Direct transfer of data between
which holds the address of the next memory and accumulator
instruction to be fetched is b) Direct transfer of data between
a)Accumulator memory & I/O devices without
b) Program counter the use of μp
c) Stack pointer c) Transfer of data exclusively
d) Instruction register within μp registers
d) A fast transfer of data between
Q.37 The content of the accumulator of μp registers
8085 microprocessor after
execution of the following Q.42) In microcomputer, WAIT states are
instructions will be used to
MVI A, A7H a) Make the processor wait during
ORA A a DMA operation
RLC b) Make the processor wait during a
a) FF H b) 4F H power interrupt processing
c) 3F H d) CE H c) Make the processor wait during
a power shutdown
Q.38 When the 8085 receives an d) Interface slow peripherals to the
interrupt on its INTR pin, processor
a) the program is directly
transferred to a fixed call Q.43 A microprocessor has 24 address
location lines. The maximum amount of
b) 8085 waits till an interrupt memory that can be interfaced to
acknowledgement is received this microprocessor is
and transfers program to a fixed a) 2 MB b) 4 MB
call location. c) 16 MB d) 8 MB
Q.44 TRAP, HOLD and RESET inputs to XTHL
8085 are activated simultaneously. POPH
The system response is HLT
a) System is reset a) 2095 H b) 20BFH
b) System does a DMA operation c) 8F95H d) 8FBFH
and is then RESET
c) System branches to TRAP ISR Q.49 The fig shows an interfacing circuit
and is then RESET for
d) System responds to all the inputs the 8085 microprocessor to read an
in the order: TRAP, HOLD, 8-bit data from an external device.
RESET The appropriate instruction for
reading the data is
Q.45 A memory system of size 16K bytes
is required to be designed using
memory chips which have 12
address lines & 4 data lines each.
The number of such chips required
to design the memory system is
a)2 b)4
c)8 d)16
Q.46 The total number of memory

accesses involved (inclusive of the
op-code fetch)when an 8085
processor executes the instruction a) MVI A, FAH b) IN FAH
LDA 2003 is c) IN FFFAH d) LDA FFFAH
a)1 b)2
c)3 d)4 Q.50 Consider the following connection
to memory. The accessible range of
Q.47 Which one of the following address from the memory is
statements about the 8085 is TRUE?
a) Only accumulator can be loaded
with an 8-bit number in a single
instruction.
b) The processor can be
interrupted even after it
executes HLT instruction.
c) When HOLD input is activated,
the processor can execute a) 0000 – 0FFF b) IFFF – 4FFF
register-to-register instructions. c) 0000 – FFFF d)0000-4F
d) The program and data memories
are separate.
Q.48 The contents of the HL register pair

after the execution of the following
program on the 8085 are
LXI H, 2095H
LXI B, 8FBFH
PUSH B
ANSWER KEY (MICROPROCESSOR):
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
(d) (c) (b) (c) (b) (c) (a) (a) (a) (c) (b) (b) (b) (a) (d)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(a) (c) (d) (a) (a) (b) (d) (c) (d) (b) (a) (d) (d) (a) (b)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
(b) (b) (b) (c) (a) (b) (b) (b) (b) (d) (b) (d) (c) (a) (c)
46 47 48 49 50
(d) (b) (a) (b) (a)
EXPLANATIONS
Q.1 (d) microprocessor and its I/O and

Statements 2 & 3 are false memory.
2) IN and OUT instructions are not
used with memory mapped I/O Q.8 (a)
scheme. A15 A14 A13 A12 A11 A10 A 9 A8 A 7 A 6 A 5 A 4 A 3 A 2 A1 A 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ⇒ 0000H
3) The number of input output
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 ⇒ OFFFH
devices can exceed 256 in
0000H − OFFFH
memory mapped I/O scheme.
Q.9 (a)
Q.2 (c)
Assembler is a computer program STC CY ← 1
which translates from assembly CMC CY ← 0
language to machine language MOV A, B A←B
format. RAL Rotate accumulator left
without carry. This doubles ACC
Q.3 (b) content.
I/O processor controls the flow of MOV B, A B←A
information between Main memory
and I/O devices. Q.10 (c)
A15 A14 A13 A12 A11 A10 A9 A8 A 7 A 6 A5 A 4 A3 A 2 A1 A 0
Q.4 (c) 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Logical instructions are used to set 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1
the carry flag. F000 – F3FF
Q.5 (b) Q.11 (b)

LXI SP, 1000 ; SP ← 1000 MVI A, 20H A ← 20
PUSH H ; SP ← SP − 2 =OFFE LHLD 203AH L ← 3EH ← 20
PUSH D ; SP ← SP − 2 =OFFC
CALL 2050 ; SP ← SP − 2 = OFFA ADD MA ← A + ( HL )= 20H + 20H= 40H
Program execution is transformed
HLT STOP
to subroutine and after the
execution of RET it is returned to
Q.12 (b)
current program and
In register indirect addressing mode
SP ← SP + 2 = OFFC
the operand in the instruction is
POP H SP ← SP + 2 = OFFE
address which is stored in register
HLT PC ← 200A
pair.
e.g. LXI, STAX, LDAX
Q.6 (c)
1 byte =8 bits
Q.13 (b)
32 bits = 4 byte
D7 D6 D5 D4 D3 D2 D1 D0
Q.7 (a)
Data bus is bidirectional used to
transfer 8-bits between S Z X AC X P X CY
Q.14 (a) Q.22 (d)
Let B ← FF =
11111111 8085 microprocessor has 8 eight bit
INR B B ← FF + 1 =00 registers. They are A, B, C, D, E, H, L
CY ← 0 Flag register.
Q.15 (d) Q.23 (c )

Stack is a set of memory location in There are 5 hardware interrupts:
memory reserved for storing Trap, RST 7.5, RST 6.5, RST 5.5 INTR
information temporarily
Q.24 (d)
Q.16 (a) TRAP is the highest priority
RIM instruction is used to read the interrupt.
status of interrupts 7.5, 6.5, 5.5.
Q.25 (b)
Q.17 (c ) Time required to execute one
All the timing signals are instruction is called instruction
transmitted cycle Range:1 Machine cycle to 5
through control bus. machine cycles
Q.18 ( d) Q.26 (a)

RAL → Rotate Accumulator left 1 1
1Tstate = = µs = 0.2µs
through carry. f 5
Bit D7 is of Accumulator is placed in 18 T state 18 × 0.2µs= 3.6µs
CY flag and the carry flag is placed in
LSB (D0 ) Q.27 (d)
Data transfer operation doesn’t
Q.19 (a) affect any flag
Only in case the content of
accumulator is 10110100 the sign Q.28 (d)
and parity flags will be set. When CMP instruction comes under
MSB is 1 sign flag is set which Logical operation. The content of
indicates a negative number and if operand is compared with
the number of 1’s are even then accumulator.
parity flag is set.
Q.29 (a)
Q.20 (a) All the logical operations are
MVI M, 8 F performed in relation to the content
This instruction requires Fetch, of Accumulator.
Read, write machine cycles.
Q.30 (b)
Q.21 (b) Using PUSH instruction data from
crystal freq register is saved on the stack .SP is
Clock freq = determined by 2
2
5
=f = MHz 2.5MHz Q.31 (b)
2 SIM → Set Interrupt Mask
1 1
T= = µs = 0.4µs
f 2.5 Q.32 (b)
Crystal frequency =6MHz
crystal freq Q.42) (d)
Clock frequency =
2 WAIT states are used to interface
=3MHz slow peripherals to the processor.
Q.33 (b) Q.43 ( c)

There are 16 address lines in 224 × 8 = 24 × 220 × 8
memory mapped I/O whereas 8
address lines are provided for I/O = 16MB
mapped I/O.
Q.44 (a)
Q.34 (c) System is Reset.
Parity bit adding technique is used
for Error detection. Q.45 (c)
16 × 210 × 8 217
Q.35 ( a) Number=
of chips =
212 × 4 214
Microprocessor checks INTR line = 2=
3
8
after each instruction for any
external interrupt. Q.46 (d)
LDA 2003 requires 4 machine
Q.36 (b) cycles: Op-code Fetch, 3 Memory
Program Counter holds the address read cycles.
of the next instruction to be fetched.
Q.47 (b)
Q.37 (b) To get the processor out of the halt
MVI A, A 7H ; A ← A7 state interrupt signal can be used.
ORA A ; A ← A7
RLC ;Rotate left Q.48 (a )
without carry LXI H, 2095 H ; HL ← 2095
A7 → 10100111CY = 0
LXI B, 8 FBFH ; BC ← 8FBF
After rotating → 01001111CY = 1
PUSH B ; B, C will be
A ← 4FH copied into the
stack
Q.38 (b) XTHL ; Exchange H, L with top of
stack
Q.39 (b) H ← 8F, L ← BF Stack
By introducing WAIT states the
contains 20, 95
microprocessor can be
synchronized with POP H ; Stack data will be copied
into H, L. H ← 20 L ← 95
slow peripherals.
HLT ; stop
Q.40 (d)
Q.49 (b)
212 × 8 = 22 × 210 × 8
Q.50 (a)
= 4kB A15 A14 A13 A12 A11 A10 A 9 A8 A 7 A 6 A 5 A 4 A 3 A 2 A1 A 0
Q.41) (b) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA transfer data between memory 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
and I/O devices without the use of 0000H − OFFF H
µP .

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DIGITAL CIRCUITS

Combinational logic circuits, minimization of Boolean functions. IC families, TTL, MOS

ELECTRONICS ELECTRICAL INSTRUMENTATION

8.1 Introduction 150

9.1 Introduction 158

10. ASSIGENMENT QUESTIONS (DIGITAL) 198

11. ASSIGENMENT QUESTIONS (MICROPROCESSOR) 218

1.1 INTRODUCTION the number. In other words, we have the

Positional numbering system uses a set of

Example: Convert ( 55.03125)10 to its

Example: Perform 66+99 using BCD

Complements are used to simplify the 1.6.1 NUMBER REPRESENTATION

1.6.2 SUBTRACTION USING 2’s

Earlier we have discussed binary

Example: Add +7 and –2 using 2’s

Q.1 The 2’s complement representation 010100. In this numbering system,

Q.6 A new Binary coded Pentary (BCP)

Q.1 (b) Carry is discarded in the addition of

Q.3 The base of the number system for

Q.1 (d) Q.5 (c)

Q.2 (c) → Integer part

2.1 INTRODUCTION A+A = A

1. NOT Theorem: AB= A + B

x y z F Complement of a function can be calculated

7. Four 1s at the corner of K-map can

Example: Simplify the function

group will contain two 1's since 2 =

2. If n = 2, a group will contain four

A 3 variable K-map can be used for

A 4 variable K-map can be used for

In the upper quad we have covered 2 don’t

f ( A, B, C, D ) =AC + BCD + BCD + BCD

Q.1 The number of distinct Boolean [GATE -2005]

Q.11 Consider the Boolean function,

Y = RS + PR + PQ + PQ + PRS + PQS + PQR + QRS

Simplified expression from the

So, the essential prime implicants

F ( A, B, C ) = ABC + ABC + ABC

Q.1 The Boolean expression Q.4 In the sum of products function

Q.12 Digital input signals A, B, C with A as

The equivalent minimized

Hence, the correct option is (B).

Q.1 Min-term (Sum of products) Q.5 The minimal sum- of products

b) X 0 .Y1 + Y1 Y 0 + X1 .X 0 Q.7 The output Y of a 2-bit comparator

b) ABC + ABC + ABC + ABC

c) ABC + ABC + ABC + ABC

d) ABC + ABC + ABC + ABC

Q.1 (c) Q.4 (a)

A logic gate is a general purpose electronic

3.2 BASIC GATES b. Bistable Multivibrator:

1. NOT Gate: A NOT gate, often called an

2. OR Gate: An OR gate is a digital logic

b. AND Gate using NAND Gate:

d. XOR Gate using NAND Gate:

3.3 UNIVERSAL GATES

There are two universal Gates NAND &

1. NAND Gate: A NAND gate (sometimes

c. OR Gate using NOR Gate:

Example: Prove that ( X ⊕ Y )’ =

3.4.1 PROPERTIES OF X-OR & X-NOR GATES