ECOM 4423

VHDL
Hardware Description Language

Instructor: Ruba A. Salamah

Islamic University of Gaza
Continue
Outline
This slide set covers the principles of sequential
circuit design
• Overview of sequential circuits
• Synchronous circuits
• Danger of synthesizing asynchronous
circuit
• Inference of basic memory elements
• Simple design examples
• Timing analysis **Optional
• •Alternative one-segment coding style
• Use of variable for sequential circuit
ECOM 4423 – Hardware Description Language VHDL Chapter 8 2
 Overview of sequential
circuit

ECOM 4423 – Hardware Description Language VHDL

Combinational vs sequential circuit

A combinational circuit, is a A sequential circuit, on the other

circuit whose output, after the hand, has an internal state, or
initial transient period, is a memory. Its output is a function of
function of current input.
current input as well as the internal
It has no internal state and
state. The internal state essentially
therefore is “memoryless”
about the past events (or past “memorizes” the effect of the past
inputs). input values.
• The output thus is affected by
current input value as well as past
input values (or the entire
sequence of input values).
• That is why we call a circuit with
internal state a sequential circuit.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 4

Basic Memory Elements
• We will use predesigned memory components.
• These can be divided into two broad categories: latch
and flip-flop (FF).
• We will concentrate on D-type latch (D latch) and D-
type FF (D FF).

ECOM 4423 – Hardware Description Language VHDL Chapter 8 5

Basic Memory Elements

ECOM 4423 – Hardware Description Language VHDL Chapter 8 6

Timing Diagram

ECOM 4423 – Hardware Description Language VHDL Chapter 8 7

Timing of D Flip Flop

Clock-to-q delay (Tcq): Delay required for sampled d value to show up on q

Setup time (Tsetup): time interval that d must be stable for before the rising edge
of clock
Hole time (Thold): time interval that d must be stable for after the rising edge.

To satisfy the timing constraints of the FFs, the clock period must be
large enough to accommodate the propagation delay of the next-state
logic, the clock-to-q delay of the FFs and the setup time of the FFs.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 8

Synchronous vs asynchronous circuits
• According to the arrangement of the clock, we
can mainly divide the sequential circuits into
the following classes:
• synchronous circuit: It uses FFs as memory
elements, and all FFs are controlled (i.e.,
synchronized)by a single global clock signal.
Synchronous design is the most important.
• asynchronous circuit: It does not use a clock
signal to coordinate the memory operation.
The state of a memory element changes
independently. The design of asynchronous circuits is very
different from that of synchronous circuits and
is not recommended for HDL synthesis.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 9

 SYNCHRONOUS
CIRCUITS

ECOM 4423 – Hardware Description Language VHDL

Basic model of a synchronous circuit
Basic Block diagram:
• State registers (state_reg) represent the memory
elements
• Next state logic represent the combinational circuit that
determines state_next
• Output logic represent the combinational circuit that
generates the external output signal.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 11

 Operation
• At the rising edge of the clock, the value of the
state_next signal (appearing at the d port) is
sampled and propagated to the q port, which
becomes the new value of the state_reg signal. The
value is also stored in FFs and remains unchanged
for the rest of the clock period. It represent the
current state of the system.
• Based on the value of the state_reg signal and
external input, the next-state logic computes the
value of the state_next signal and the output logic
computes the value of external output.At the next
rising edge of the clock, the new value of the
state_next signal is sampled and the state_reg
signal is updated. The process then repeats.
ECOM 4423 – Hardware Description Language VHDL Chapter 8 12
Advantages of synchronous design

• A single global clock makes the task of

satisfying the timing constraints of a design
with of thousands of FFs manageable.
• The synchronous model separates the
combinational components from the memory
elements, making it possible to treat the
combinational part by itself
• Propagation delay anomalies such as
hazards can be dealt with easily by focusing
on the worst case timing behavior

ECOM 4423 – Hardware Description Language VHDL Chapter 8 13

Inference of basic memory elements
• You should use the following ’templates’ to
create latches and FFs, so that the
predesigned library cells are inferred by the
synthesis tools.
• VHDL code
• D Latch
• Positive edge-triggered D FF
• Negative edge-triggered D FF
• D FF with asynchronous reset

ECOM 4423 – Hardware Description Language VHDL Chapter 8 14

 D Latch
library ieee; architecture arch of dlatch is
use begin
ieee.std_logic_1164.all process(c,d)
; begin
entity dlatch is if (c='1') then
port( q <= d; No else branch
c: in std_logic; end if; cause D latch to
d: in std_logic; end process; be inferred

q: out std_logic end arch;

);
end dlatch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 15

Positive edge-triggered D FF
library ieee; architecture arch of dff is
use ieee.std_logic_1164.all; begin Note that the d signal is
entity dff is process(clk) not in the sensitivity list
port( begin
clk: in std_logic; if (clk'event and clk='1') then
d: in std_logic; q <= d;
q: out std_logic end if;
); end process;
end dff; end arch;

The “ ’event “ term is a VHDL attribute

returning true when there is a change in
signal value (i.e., an event). Thus, when clk
event is true, it means that the value of clk
has changed. When the clk= ‘1’ expression is
true, it means that the new value of clk is ’ 1 ’
. When both expressions are true, it indicates
that the clk signal changes to ‘1’ , which is the
rising edge of the clk signal.
ECOM 4423 – Hardware Description Language VHDL Chapter 8 16
Negative edge-triggered D FF
library ieee; architecture arch of dff is
use ieee.std_logic_1164.all; begin
entity dff is process(clk)
port( begin
clk: in std_logic; if (clk'event and clk=‘0') then
d: in std_logic; q <= d;
q: out std_logic end if;
); end process;
end dff; end arch;

There is a defined function,

rising_edge( ), in the IEEE
std_logic_1164 package. It
also returns true when the
checked signal is changed to
‘1’.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 17

D FF with asynchronous reset
library ieee; architecture arch of dffr is
use ieee.std_logic_1164.all; begin
entity dffr is process(clk,reset)
port( begin
clk: in std_logic; if (reset='1') then
reset: in std_logic; q <='0';
d: in std_logic; elsif (clk'event and clk='1') then
q: out std_logic
q <= d;
);
end if;
end dffr;
end process;
end arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 18

Notes:
• Asynchronous reset, as its name implies, is
not synchronized by the clock signal and thus
should not be used in normal synchronous
operation.
• The major use of a reset signal is to clear the
memory elements and set the system to an
initial state. Once the system enters the initial
state, it starts to operate synchronously and
will never use the reset signal again.
• In many digital systems, a short reset pulse is
generated when the power is turned on.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 19

D FF with asynchronous reset and preset
library ieee; architecture arch of dffrp is
use ieee.std_logic_1164.all;
begin
entity dffrp is
port( process(clk,reset,preset)
clk: in std_logic; begin
reset, preset: in std_logic; if (reset='1') then
d: in std_logic;
q <='0';
q: out std_logic
); elsif (preset='1') then
end dffrp; q <= '1';
elsif (clk'event and clk='1') then
q <= d;
end if;
end process;
end arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 20

Register
A register is a collection of a D FFs that is driven by the same
clock and reset signals

library ieee; architecture arch of reg8 is

use ieee.std_logic_1164.all; begin
entity reg8 is process(clk,reset)
port( begin
clk: in std_logic; if (reset='1') then
reset: in std_logic; q <=(others=>'0');
d: in std_logic_vector(7 downto 0); elsif (clk'event and clk='1’)
q: out std_logic_vector(7 downto 0) then
); q <= d;
end reg8; end if;
end process;
Note: The code is similar to D FF end arch;
except that the d input and the q
output are now 8 bits wide.
ECOM 4423 – Hardware Description Language VHDL Chapter 8 21
 SIMPLE DESIGN
EXAMPLES

ECOM 4423 – Hardware Description Language VHDL

Methodology
• We will first identify and separate the memory
elements and then derive the next_state logic
and output logic which are combinational circuits.
• A clear separation between memory elements
and combinational circuits is essential for the
synthesis of large, complex design and is helpful
for the verification and testing processes.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 23

Methodology
Since identifying and separating the memory
elements is the key in deriving a sequential
circuit, we utilize the following coding practice to
emphasize the existence of the memory
elements:
• Use an individual VHDL code segment to infer
memory elements. The segment should be the
standard description of a D FF or register.
• Use the suffix reg to represent the output of a
D FF or a register.
• Use the suffix next to indicate the next value
(the d input) of a D FF or a register.
ECOM 4423 – Hardware Description Language VHDL Chapter 8 24
Example 1:D FF with enable

library ieee;
use ieee.std_logic_1164.all;
entity dff_en is
port(
clk: in std_logic;
reset: in std_logic;
en: in std_logic;
d: in std_logic;
q: out std_logic
);
end dff_en;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 25

Example 1:D FF with enable
architecture two_seg_arch of dff_en is
signal q_reg: std_logic;
signal q_next: std_logic;
begin
-- D FF
process(clk,reset)
begin
if (reset='1') then
q_reg <= '0';
elsif (clk'event and clk='1') then Basic model of synchronous circuit
q_reg <= q_next;
end if;
end process;
-- next-state logic
q_next <= d when en ='1' else
q_reg;
-- output logic
q <= q_reg;
end two_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 26

Example 1:D FF with enable (one segment code)
architecture one_seg_arch of dff_en is
begin
process(clk,reset)
begin
if (reset='1') then
q <='0';
elsif (clk'event and clk='1') then
if (en='1') then
q <= d;
end if;
end if;
end process;
end one_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 27

 Example 2: T Flip Flop

ECOM 4423 – Hardware Description Language VHDL Chapter 8 28

 Example 2: T Flip Flop
architecture two_seg_arch of tff is
signal q_reg: std_logic;
signal q_next: std_logic;
begin
-- D FF
process(clk,reset)
begin
if (reset='1') then
q_reg <= '0';
elsif (clk'event and clk='1') then
q_reg <= q_next;
entity tff is end if;
port( end process;
clk: in std_logic; -- next-state logic
reset: in std_logic; q_next <= q_reg when t='0' else
t: in std_logic; not(q_reg);
q: out std_logic -- output logic
); q <= q_reg;
end tff; end two_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 29

Example 3:Free-running shift-right register
• A free-running shift register performs the shifting operation
continuously. It has no other control signals.
• One major application of a shifter register is to send parallel
data through a serial line. In the transmitting end, a data word
is first loaded to register in parallel and is then shifted out 1 bit
at a time.
• In the receiving end, the data word is shifted in 1 bit at a time
and reassembled.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 30

Example 3:Free-running shift-right register
We will rearrange the FFs
and align then vertically.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 31

Example 3:Free-running shift-right register

Grouping the four FFs together and treating them as a single

memory block, we transform the circuit into the basic sequential
circuit block diagram.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 32

Example 3:Free-running shift-right register

Grouping the four FFs together and

treating them as a single memory
block, we transform the circuit into
the basic sequential circuit block
diagram.
library ieee;
use ieee.std_logic_1164.all;
entity shift_right_register is 4 bit register (memory element)
port(
clk, reset: in std_logic;
d: in std_logic; Combinatioal circuit
q: out std_logic r_next <= d & r_reg(3 downto 1);
);
end shift_right_register;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 33

Example 3:Free-running shift-right register
architecture two_seg_arch of shift_right_register is
signal r_reg: std_logic_vector(3 downto 0);
signal r_next: std_logic_vector(3 downto 0);
begin
-- register
process(clk,reset)
begin
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then
r_reg <= r_next;
end if;
end process;
-- next-state logic (shift right 1 bit)
r_next <= d & r_reg(3 downto 1);
-- output
q <= r_reg(0);
end two_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 34

Example 4: Universal Shift Register
• There are four operations: load, shift right, shift left and pause.
• A control signal, ctrl, specifies the desired operation.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 35

Example 4: Universal Shift Register
Note that the d(0) input and the q(3) output are used as serial-in and serial-out for
the shift-left operation, and the d(3) input and the q(0) output are used as serial-
in and serial-out for the shift-right operation

ECOM 4423 – Hardware Description Language VHDL Chapter 8 36

Example 4: Universal Shift Register

library ieee;
use ieee.std_logic_1164.all;
entity shift_register is
port(
clk, reset: in std_logic;
ctrl: in std_logic_vector(1 downto 0);
d: in std_logic_vector(3 downto 0);
q: out std_logic_vector(3 downto 0)
);
end shift_register;
architecture two_seg_arch of shift_register is
signal r_reg: std_logic_vector(3 downto 0);
signal r_next: std_logic_vector(3 downto 0);
Begin

ECOM 4423 – Hardware Description Language VHDL Chapter 8 37

Example 4: Universal Shift Register
-- register
process(clk,reset)
begin
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1')
then
r_reg <= r_next;
end if; -- output
end process; q <= r_reg;
end two_seg_arch;

-- next-state logic
with ctrl select
r_next <= r_reg when "00", --no op
r_reg(2 downto 0) & d(0) when "01", --shift left;
d(3) & r_reg(3 downto 1) when "10", --shift right;
d when others;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 38

Example 5: Arbitrary-sequence counter
• A sequential counter circulates a predefined sequence of
states. The next-state logic determines the patterns in the
sequence.
• For example, if we need a counter to cycle through the
sequence of “000”, “011” , “110”, “101” and “111”, we can
construct a combinational circuit with a function table that
specifies the desired patterns.

entity arbi_seq_counter4 is
port(
clk, reset: in std_logic;
q: out std_logic_vector(2 downto 0)
);
end arbi_seq_counter4;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 39

Example 5: Arbitrary-sequence counter
architecture two_seg_arch of
arbi_seq_counter4 is -- next-state logic
signal r_reg: std_logic_vector(2 r_next <= "011" when r_reg="000"
downto 0); else
signal r_next: std_logic_vector(2 "110" when r_reg="011"
downto 0); else
begin "101" when r_reg="110"
-- register else
process(clk,reset) "111" when r_reg="101"
begin else
if (reset='1') then "000"; -- r_reg="111"
r_reg <= (others=>'0'); -- output logic
elsif (clk'event and clk='1') then q <= r_reg;
r_reg <= r_next; end two_seg_arch;
end if;
end process;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 40

Example 6: Free-running binary counter
• An n-bit binary counter has a register with n
FFs, and its output is interpreted as an
unsigned integer.
• A free-running binary counter increments the
content of the register every clock cycle,
counting from 0 to (2n – 1) and then repeating.
• For example, a 3-bit binary counter cycles
through “000”, “001”, “010”, “011, “100”, “101”,
“110” and “111” , and then repeats.
• In addition to the register output, we assume
that there is a status signal, max_pulse, which
is “1‟ when the counter is in the all-one state.
ECOM 4423 – Hardware Description Language VHDL Chapter 8 41
Example 6: Free-running binary counter

The next_state logic consists of an incrementor, which calculates the new

value for the next state of the register
Note that the definition requests the 4-bit binary counter counts in a
wrapped-around fashion; i.e., when the counter reaches the maximal
number, “1111”, it should return to "0000" and start over again. This is
achieved here because in the IEEE numeric_std package, the definition
of ‘+’ on the unsigned data type is modeled after a hardware adder
r_next <= r_reg + 1;
We don’t need to use mod operator
r_next <= (r_reg + 1) mod 16
ECOM 4423 – Hardware Description Language VHDL Chapter 8 42
Example 6: Free-running binary counter

entity binary_counter4_pulse is -- register

port( process(clk,reset)
clk, reset: in std_logic; begin
max_pulse: out std_logic; if (reset='1') then
q: out std_logic_vector(3 downto 0) r_reg <= (others=>'0');
); elsif (clk'event and clk='1') then
end binary_counter4_pulse; r_reg <= r_next;
end if;
architecture two_seg_arch of end process;
binary_counter4_pulse is -- next-state logic
signal r_reg: unsigned(3 downto 0); r_next <= r_reg + 1;
signal r_next: unsigned(3 downto 0); -- output logic
begin q <= std_logic_vector(r_reg);
max_pulse <= '1' when r_reg="1111" else
'0';
end two_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 43

Example 7: Featured Binary Counter
• Rather than leaving the counter in the free-
running mode, we can add more control.
• In the counter, we can synchronously clear the
counter to 0, load a specific value, and enable or
pause the counting.

entity binary_counter4_feature is
port(
clk, reset: in std_logic;
syn_clr, en, load: in std_logic;
d: in std_logic_vector(3 downto 0);
q: out std_logic_vector(3 downto 0)
);
end binary_counter4_feature;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 44

Example 7: Featured Binary Counter

architecture two_seg_arch of
binary_counter4_feature is
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
-- register
process(clk,reset)
begin
if (reset='1') then
-- next-state logic
r_reg <= (others=>'0');
r_next <= (others=>'0') when syn_clr='1’
elsif (clk'event and clk='1') then
else
r_reg <= r_next;
unsigned(d) when load='1' else
end if;
r_reg + 1 when en ='1' else
end process;
r_reg;
-- output logic
q <= std_logic_vector(r_reg);
end two_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 45

Example 8: Decade Counter
• Instead of utilizing all possible 2n states of an n-bit binary
counter, we sometime only want the counter to circulate
through a subset of the states.
• Ex: A decade counter (mod-10 counter) which counts from 0 to
9 and then repeats. We define a mod-m counter as a binary
counter whose states circulate from 0 to m - 1 and then repeat.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 46

Example 8: Decade Counter
-- register
entity mod10_counter is process(clk,reset)
port( begin
clk, reset: in std_logic; if (reset='1') then
q: out std_logic_vector(3 downto 0) r_reg <= (others=>'0');
); elsif (clk'event and clk='1') then
end mod10_counter; r_reg <= r_next;
end if;
architecture two_seg_arch of end process;
mod10_counter is
-- next-state logic
constant TEN: integer := 10;
r_next <= (others=>'0') when r_reg=(TEN-1)
signal r_reg: unsigned(3 downto 0); else
signal r_next: unsigned(3 downto 0); r_reg + 1;
begin -- output logic
q <= std_logic_vector(r_reg);
end two_seg_arch;

The key to this design is the next_state logic. When the counter reaches 9, as indicated
by the condition r_reg=(TEN-1), the next value will be 0. Otherwise, the next value will
be incremented by 1.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 47

Example 9: Programmable mod-m counter
• We will design a "programmable" 4-bit mod-m
counter.
• m is a 4-bit input signal which is interpreted as
an unsigned number.
• The range of m is from "0010 to “1111”, and
thus the counter can be programmed as a
mod-2, mod-3, . . . , or mod- 15 counter.
• The maximal number in the counting
sequence of a mod-m counter is m-1.
• when the counter reaches m-1, the next state
should be 0.

ECOM 4423 – Hardware Description Language VHDL Chapter 8 48

Example 9: Programmable mod-m counter
First Design

When the counter reaches m - 1, the next state should be 0. Our first
design is based on this observation. The VHDL code is similar to the
decade counter except that we need to replace the r_reg=(TEN-1)
condition of the next-state logic with r_reg=(unsigned(m)-1).

ECOM 4423 – Hardware Description Language VHDL Chapter 8 49

Example 9: Programmable mod-m counter
-- register
First Design process(clk,reset)
begin
if (reset='1') then
entity prog_counter is r_reg <= (others=>'0');
port( elsif (clk'event and clk='1') then
clk, reset: in std_logic; r_reg <= r_next;
m: in std_logic_vector(3 downto 0); end if;
q: out std_logic_vector(3 downto 0) end process;
); -- next-state logic
end prog_counter; r_next <= (others=>'0') when
architecture two_seg_clear_arch of r_reg=(unsigned(m)-1) else
prog_counter is r_reg + 1;
signal r_reg: unsigned(3 downto 0); -- output logic
signal r_next: unsigned(3 downto 0); q <= std_logic_vector(r_reg);
begin end two_seg_clear_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 50

Example 9: Programmable mod-m counter
Second Design (More Efficient)

Since the r_reg + 1 operation is needed for incrementing operation,

we can use it in comparisonand eliminate the decrementor

ECOM 4423 – Hardware Description Language VHDL Chapter 8 51

Example 9: Programmable mod-m counter
Second Design (More Efficient)

architecture two_seg_effi_arch of -- next-state logic

prog_counter is r_inc <= r_reg + 1;
signal r_reg: unsigned(3 downto 0); r_next <= (others=>'0')
signal r_next, r_inc: unsigned(3 downto 0); when r_inc=unsigned(m)
begin else r_inc;
-- register -- output logic
process(clk,reset) q <=
begin std_logic_vector(r_reg);
if (reset='1') then end two_seg_effi_arch;
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then
r_reg <= r_next;
end if;
end process;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 52

 TIMING ANALYSIS
Optional*

ECOM 4423 – Hardware Description Language VHDL

 Alternative One-Segment
Coding Style

ECOM 4423 – Hardware Description Language VHDL

Alternative One-Segment Coding Style
• Although it is possible to combine the memory elements with next-state and
output logic into one segment, you should avoid this coding practice b/c it is
error prone
architecture two_seg_arch of dff_en is
signal q_reg: std_logic;
signal q_next: std_logic;
begin
-- D FF 3-segments
process(clk,reset) Coding Style
begin architecture one_seg_arch of dff_en is
if (reset='1') then begin
q_reg <= '0'; process(clk,reset) 1-segment
elsif (clk'event and clk='1') then begin
q_reg <= q_next; Coding Style
if (reset='1') then
end if; q <='0';
end process; elsif (clk'event and clk='1') then
-- next-state logic if (en='1') then
q_next <= d when en ='1' else q <= d;
q_reg; end if;
-- output logic end if;
q <= q_reg; end process;
end two_seg_arch; end one_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 55

Consider the T FF discussed earlier
architecture two_seg_arch of tff is
signal q_reg: std_logic;
signal q_next: std_logic;
begin
-- D FF
process(clk,reset)
begin
architecture one_seg_arch of tff is
if (reset='1') then signal q_reg: std_logic;
q_reg <= '0'; begin
elsif (clk'event and clk='1') then process(clk, reset)
q_reg <= q_next; begin
end if; if reset='1' then
q_reg <= '0';
end process;
elsif (clk'event and clk='1') then
-- next-state logic
if (t='1') then
q_next <= q_reg when t='0' else q_reg <= not q_reg;
not(q_reg); end if;
-- output logic end if;
q <= q_reg; end process;
end two_seg_arch; q <= q_reg;
end one_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 56

Consider the Free-Running Binary Counter
architecture two_seg_arch of
binary_counter4_pulse is
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
-- register 3-segments
process(clk,reset) Coding Style
begin
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then
r_reg <= r_next;
end if;
end process;
-- next-state logic
r_next <= r_reg + 1;
-- output logic
q <= std_logic_vector(r_reg);
max_pulse <= '1' when r_reg="1111"
else '0';
end two_seg_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 57

Consider the Free-Running Binary Counter
architecture not_work_one_seg_glitch_arch
This does NOT work as expected because
of binary_counter4_pulse is
the following is INSIDE the if
signal r_reg: unsigned(3 downto 0); (clk’event...
begin if (r_reg = "1111") then
process(clk,reset) max_pulse <= ’1’;
1-segment
begin else
Coding Style
if (reset='1') then max_pulse <= ’0’;
r_reg <= (others=>'0'); end if;
elsif (clk'event and clk='1') then
r_reg <= r_reg + 1;
if r_reg="1111" then
max_pulse <= '1';
else
max_pulse <= '0';
end if;
end if;
This creates a 1-bit register for max_pulse
end process; -- which works as a buffer and creates a 1
q <= std_logic_vector(r_reg); clock signal delay of the output pulse
end not_work_one_seg_glitch_arch; max_pulse will be asserted with r_reg =
"0000"
ECOM 4423 – Hardware Description Language VHDL Chapter 8 58
Consider the Free-Running Binary Counter
architecture work_one_seg_glitch_arch To correct, you must
of binary_counter4_pulse is move the output logic
signal r_reg: unsigned(3 downto 0); outside the process
begin
2-segments
process(clk,reset) Coding Style
begin
if (reset='1') then
r_reg <= (others=>'0'); Correct Version
elsif (clk'event and clk='1') then
r_reg <= r_reg + 1;
end if; It is possible to add the
end process; next state logic to the
q <= std_logic_vector(r_reg); storage element in one
max_pulse <= '1' when r_reg="1111"
process but the output
else '0'; logic should be in a
end work_one_seg_glitch_arch;
separate segment

ECOM 4423 – Hardware Description Language VHDL Chapter 8 59

consider the Programmable Counter
architecture not_work_one_arch of
prog_counter is Incorrect Version
signal r_reg: unsigned(3 downto 0);
begin Does NOT work as expected
process(clk,reset) because a signal is NOT
updated until the end of the
begin
process. The code actually
if reset='1' then
specified a mod-(m + 1)
r_reg <= (others=>'0'); counter instead.
elsif (clk'event and clk='1') then
r_reg <= r_reg+1;
if (r_reg=unsigned(m)) then
To correct the problem, we
r_reg<= (others=>'0'); must move the incrementing
end if; operation outside the
end if; process so that it can be
end process; performed concurrently with
the process.
q <= std_logic_vector(r_reg);
end not_work_one_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 60

consider the Programmable Counter
rchitecture work_one_arch of prog_counter is
signal r_reg: unsigned(3 downto 0); To correct the problem, we
signal r_inc: unsigned(3 downto 0); must move the incrementing
begin
operation outside the
process so that it can be
process(clk,reset)
performed concurrently with
begin
the process.
if reset='1' then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then Correct Version
if (r_inc=unsigned(m)) then
r_reg <= (others=>'0');
else
r_reg <= r_inc;
end if;
end if;
end process;
r_inc <= r_reg + 1;
q <= std_logic_vector(r_reg);
end work_one_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 61

consider the Programmable Counter
architecture variable_arch of prog_counter is
signal r_reg: unsigned(3 downto 0); We can use a variable to
begin fix the problem we had
process(clk, reset) with the one-segment
variable q_tmp: unsigned(3 downto 0); version of the mod-m
begin counter
if (reset = ’1’) then
r_reg <= (others => ’0’);
elsif (clk’event and clk’ = ’1’) then The proper use of variables
q_tmp := r_reg + 1; is to use them to store
if (q_tmp = unsigned(m)) then intermediate results
r_reg <= (others => ’0’);
else
Correct Version
r_reg <= q_tmp;
end if;
end if;
end process;
q <= std_logic_vector(r_reg);
end variable_arch;

ECOM 4423 – Hardware Description Language VHDL Chapter 8 62

Using Variables in Sequential Circuit Descriptions
• A variable can also be assigned under the
clk’event and clk = ’1’ condition, but
whether a FF is created or not depends on
how it is used
• If a variable is assigned a value before it is
used, it will get a value on each invocation
of the process and therefore, there is not
need to remember its previous value

ECOM 4423 – Hardware Description Language VHDL Chapter 8 63

 End Of Chapter 8

ANY QUESTIONS??

ECOM 4423 – Hardware Description Language VHDL Chapter 8 64