ELEC 2441 - Computer

Organization and Microprocessors

(Lecture Note #2A: Basic Organization &

Operations of A Microcomputer)

by Dr. Vincent TAM

* Ref: Chapter 2 & 4 of Microcomputers and

Microprocessors (6th Edition), R.J. Tocci & F.J. Ambrosio,
2003.

Todays Quote

Once we accept our limits, we go beyond them.

- Albert Einstein.

Chapter 2 1
2. Basic Organization & Operations of
A Microcomputer

[Part A]

Objectives:
The uses of tri-state logic gates to control data bus in a
microcomputer;
The RS flip-flops (FFs), clocked RS FFs and D-type
FFs;
The importance of Setup and Hold time for clocked
FFs;
FFs as registers to transfer data in parallel or serial
mode;
The basic concepts and operation of data buses;
Decoders, Encoders, Multiplexers and their uses in
modern computers;
Basic operations of an Arithmetic Logic Unit (ALU) in
modern computers;
Understand the basic computer organization (i.e. CPU,
Memory and I/O units);
An overview of computer instructions: common types
and formats.
Basic steps involved in a program execution.

Chapter 2 2
Tri-state (three-state) logic (ref. Ch. 2.3) for Control of
Signal Flows

In addition to the normal High and Low logic

voltage levels, the third condition is the high-
impedance (or high-Z) state.

When the enable input E = 1

the logic gate operates normally & is in either the High
or Low state. The output voltage = logic function of
the input voltages (e.g. B = A')

A B A B
E=1

When the enable input E = 0

the output is 'disconnected' from the input. In
practice, although the disconnection is not perfect (i.e.,
impedance ), the impedance between the output
terminal & the internal circuit is sufficiently high.

A B A B
E=0

Chapter 2 3
Active high signal

A signal is active high if it is asserted or activated (logic

TRUE) when its voltage is high (e.g., 5V). It is de-
asserted or deactivated (logic FALSE) when its voltage is
low.

The ENABLE signal in the above example is active high.

Active low signal

It is asserted or activated (logic TRUE) when its voltage

is low (e.g., 0V). It is de-asserted or deactivated (logic
FALSE) when its voltage is high.

A signal is usually written in negated form to indicate it

is active low, e.g. E or E'.
Considering the above example with E ,

A B

If E = 0, B = A' ,
if E = 1, B is disconnected (high impedance state).
[In fact, active-low signals are very popular examples used in our ref. book #1!]

Chapter 2 4
Bus organization (ref. Ch. 2.3, pp.39)

A bus is a set of parallel conductors carrying signals from

one location to another. An n-bit bus has n parallel wires.
Tri-state buffers are used to implement a bus.
1-bit bus

E2 E4 E6 E8 E10
E1 E3 E5 E7 E9

Device Device Device Device Device

A B C D E

e.g. to transfer data from A to both D & E, set

E1 = E8 = E10 = 1
E2 = E3 = E4 = E5 = E6 = E7 = E9 = 0

Only one device can send data through the bus at any one
time, otherwise there will be a conflict (bus contention), &
will cause hardware damage.

More than one device can receive data at any one time
because there is no conflict.

A device which has control of the bus is called the bus

master. The others are slaves. Bus arbitration is done
from time to time to decide which should be the master.

Chapter 2 5
An n-bit bus can be implemented by duplicating a 1-bit
bus n times. n bits can be transferred at any one time.

3-bit bus

Device Device Device

A B C

For small systems, the data bus is usually 8-bit or 16-bit.

More powerful systems use 32-bit, 64-bit, or 128-bit buses.

Chapter 2 6
Flip-flops (ref. Ch. 2.4)
Flip-flops possess 2 states only.

RS flip-flop (Latch)
[Caution: The RS flip-flop is different from the Basic FF Circuit
introduced on pp.41. Here, we used NOR rather than NAND gate]

R R S Qn+1 Q'n+1
(reset, Q
clear) 0 0 Qn Q'n
0 1 1 0
S Q' 1 0 0 1
(set) 1 1 0 0

State of flip-flop logic level of Q

Qn state after the nth transition
May treat Qn+1 as current state, Qn as previous state.

Since output of a NOR gate = 0 if any input =1,

R=1 Q=0
S=1 Q'=0

Avoid R=S=1 because Q & Q' will not be complements of

each other.

When R=S=0, Q & Q' will not change, i.e., current state =
previous state.

Chapter 2 7
Clocked RS flip-flop (ref. Ch. 2.6)
R S Qn+1 Q'n+1
R
Q 0 0 Qn Q'n
CLK 0 1 1 0
1 0 0 1
Q'
S 1 1 Avoid
level-triggered flip-flop
In the above circuit, transition occurs only during CLK=1.

Hence multiple transitions may occur if the input (R or S)

varies within the finite pulse period. This is undesirable.

Edge-triggered flip-flop
Corrects the above pitfall. Transition occurs only during
the rising edge of the clock pulse. The circuit is more
complex.
When the clock pulse exceeds a given threshold, inputs are
locked out & the flip-flop is unresponsive to further
changes in the input until the clock pulse returns to zero &
another pulse occurs.
S Q
CLK
R Q'

Chapter 2 8
D flip-flop (ref. Ch. 2.6)

RS flip-flop with an inverter at the input.

D stands for data transfer.

D Q S Q
CLK CLK
Q' R Q'
Truth table
D Q
0 0
1 1

At the rising edge of the clock pulse, the logic state at

input D is copied to Q and is locked up until the next clock
pulse arrives.

D flip-flop is very useful as a latch and for storing data.

Data which is present only for a short while can be
captured & stored in D flip-flops.

Chapter 2 9
Practical waveforms (ref. Ch. 2.8)

Ideal signal

Real signal

Rise time Fall time

Electronic circuits are not ideal. It takes a finite time, say

a few ns, for a signal to change from 0 to 1 (e.g., 0V to 5V).

Chapter 2 10
Setup time (ref. Ch. 2.8)
Sampling
instant
D=1

D Q
D=0 CLK=1
CLK
Q'
CLK=0
t1 t2
Setup time
At t1, the input at D changes from 0 to 1.

Inside the flip-flop, some logic gates are associated with D.

After D has changed from 0 to 1, it takes some time (say
until t2) for these gates to reach the correct logic state.

If the clock signal also changes from 0 to 1 before t2, the

result will be unreliable because the internal logic levels
associated with D have not yet settled to the correct values.

To ensure correct operation, CLK must not rise to 1

before t2. i.e., the input at D must reach the target level
some time before the rising edge (sampling instant) of
CLK. This minimum time is the Setup time which is
specified by the manufacturer. Usual setup times are in
the range of 5 to 50 ns.

Chapter 2 11
Hold time

Sampling
instant
D=1

D Q
CLK D=0 D=0
CLK=1
Q'

CLK=0
t1 t2 t3
Setup time Hold time

At t2, the signal D is sampled at the rising edge of CLK.

Again, it takes a finite time (until t3) for the internal logic
gates of the flip-flop to reach the correct state following
the rising edge of CLK.

Hence, the signal at D should not change before t3,

otherwise it will cause another transient, and depending
on the circuit, the operation may not be reliable.

The minimum time that D should remain unchanged

following the sampling instant is the Hold time. Typical
values range from 0 to 10 ns depending on the actual
circuit.

Chapter 2 12
Registers (ref. Ch. 2.9)

An n-bit register consists of n flip-flops. It can be used to

store n bits of data.

x1 x2 xn
LOAD

D Q y1 D Q y2
... D Q yn
Q' Q' Q'
CLOCK

Input data = x1 x2 ... xn

Stored data = y1 y2 ... yn

To store the input data, first set LOAD=1. Then when

CLOCK changes from 0 to 1, the data is stored in the flip-
flops.

Chapter 2 13
Parallel transfer from one register to another (ref. Ch. 2.9)

D Q x1 D Q x2 D Q xn
Q' Q' Q'
...
D Q y1 D Q y2 D Q yn
Q' Q' Q'
CLOCK

When CLOCK changes from 0 to 1, data in the upper

register is transferred to the lower register.

Shift register

Data can be shifted into an n-bit register bit by bit.

Serial
input S
D Q1
Q1'
D Q2
Q2'
D Q3
Q3'
... D Qn
Qn'
CLOCK

When CLOCK changes from 0 to 1, the present input S is

copied to Q1, Q1 is copied to Q2, Q2 to Q3, ..., Qn-1 to Qn
(assume hold time = 0 for all flip-flops).
Each clock pulse shifts the contents of the registers by one
bit to the right.

Chapter 2 14
Bus operation (ref. Ch. 2.11 and 2.12)
Flip-flops can be used for sending & receiving data from a
bus.
1-bit bus

E1 E2 E3

D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6
CLK1 CLK2 CLK3 CLK4 CLK5 CLK6

Device A Device B Device C

For Device A, flip-flop #1 is the output register, & flip-flop

#2 is the input register.

Chapter 2 15
e.g. to transfer data from Device A to Device C:

E1
data valid
Data bus High-Z High-Z

CLK6
t1 t2 t3 t4 t5

1. Initially E1 = E2 = E3 = 0, the data bus is in the high

impedance (High-Z) state, i.e. floating.

2. At t1, Set E1 = 1, the state Q1 will appear on the bus

after a delay of say 10 ns (it takes time to turn on the
tri-state buffer & for the signal to propagate).

3. At t2, data on the bus is valid.

4. At t3, at the rising edge of the clock CLK6, data on the

bus is sampled and stored into Q6. Make sure that
t3 - t2 setup time of flip-flop.

5. At t4, deactivate E1 (set E1=0). The bus returns to the

floating state at t5. Make sure that t4 - t3 hold time
of flip-flop.

Chapter 2 16
An n-bit bus can be implemented by duplicating the 1-bit
bus n times. Common bus widths are 8-bit, 16-bit, 32-bit
& 64-bit.

E1 E2
E1
D Q E2 D Q
D Q D Q
E1 E2
D Q D Q D Q D Q
D Q D Q D Q D Q

Device A Device B

Chapter 2 17
Integrated circuits (I.C.) (ref. Ch. 2.10)
The 74173 is a 4-bit register with 4 flip-flops & tri-state
buffers.

IE1', IE2' : input enable

If IE1' = IE2' = 0, the data at D0 to D3 are copied into the
flip-flops at the rising edge of the CLOCK; otherwise the
input buffers are disabled & no data transfer occurs.
OE1', OE2' : output enable
If OE1' = OE2' = 0, the output buffers are enabled & data
in the flip-flops are transferred to the output pins O0 to O3
at the rising edge of the CLOCK; otherwise the output
pins are in high-impedance state.
When MR=1, contents of the flip-flops are cleared (i.e. set
to 0) asynchronously disregard the logic states of IE1',
IE2', OE1', OE2', & CLOCK.

Chapter 2 18
Bidirectional register

When IE'=0, data on the bus is transferred into the

register at the rising edge of CLOCK.

When OE'=0, data in the register is driven onto the bus at

the rising edge of CLOCK.

The above diagram can be simplified as:

Chapter 2 19
It can be further simplified as:

The following diagram shows an 8-bit output device

connected to a microprocessor through an 8-bit bus.

Chapter 2 20
Decoders (ref. Ch. 2.13)
A decoder is a logic device such that given an input code,
the associated (corresponding) output line is activated.

e.g. 3-to-8 binary code decoder

When input code = 000, output line #0 is activated,

when input code = 011, output line #3 is activated, etc.

The implementation is simple,

e.g., line O5 = 1 when input code = 101
O5 = CB'A
C

B O5

Chapter 2 21
Encoders (ref. Ch. 2.14)
An encoder is the inverse of a decoder.

e.g. when input line #5 is activated, output code = 101.

Chapter 2 22
Multiplexers (ref. Ch. 2.15)
A multiplexer (or data selector) has a number of input
data streams. Depending on the selector input, one of the
input data streams is routed to the output.

e.g. When SELECT=00...01, Output Z = I1 .

Chapter 2 23
e.g.

Chapter 2 24
A multiplexer can be implemented using a decoder and
some logic gates.

e.g. -- the 3-to-8 decoder acts as selector which puts a 1

into the corresponding line that will then be OR with the
selected input channel to produce the expected output !

I0
Input I1
channels
I2

I7

S2

Channel 3-to-8
S1
select Decoder Output

S0

When S2S1S0 = 010, I2 is connected to the output.

Chapter 2 25
Arithmetic circuit (ref. Ch. 2.16)

The Arithmetic/logic unit (ALU) is responsible for

performing operations such as +, , , , logical
operations such as AND, OR, etc.

The two numbers (operands) to be operated on are copied

into the data buffer register B and the accumulator
register A.

Chapter 2 26
The operation to be performed (e.g. +) is given by the
control inputs.

The ALU then performs the required operation on the

operands. The result is transferred out of the ALU into
the accumulator.

Chapter 2 27
Basic Computer Organization [ref. text. Ch. 4.4]

Control ALU Memory Input /

Unit Registers or Output
accumulators Unit Unit
Datapath
CPU

Input unit:
Accepts information from the outside world, e.g.
keyboard, mouse, hard disk, CD reader.

Output unit:
Outputs processed data to the outside world, e.g.
monitor, printers, hard disk, CD writer.

Memory unit:
Stores both instructions & data ready for execution.
Made up of a large no. of memory units (e.g. 216 units
in the Motorola MC68HC11 a simple example of 8-bit
uniprocessor).
Each unit has a unique address.
Each unit may contain a collection of bits (a nibble,
character, or byte), or even larger unit called a word.
Most computers: 1 byte = 8 bits, 1 word = 2 bytes

Chapter 2 28
CPU:
The CPU consists of the Control (unit) + Datapath =
ALU and some registers (or accumulators).

Control unit:
Sequences operations, decodes instructions,
controls other units. [i.e. timing and control logic
(TCL) unit, instruction decoder, etc]

Datapath
- ALU (as shown on p.26 - 27):
Performs arithmetic & logic operations.

- Registers (or accumulators):

Storage cells (e.g., flip-flops) for storing temporary
data & intermediate results during calculations
inside the CPU.

* The total number of general-purpose & specialized

registers (e.g. R0-31 for general uses & F0-63 for
floating-pt. operations) contained in a computer
may often determine its overall performance!

Chapter 2 29
Bus: [ref. p159 - 160]
The bus connects the units together so that information
can travel from one unit to another. There are three
buses: data bus, address bus & control bus.

Data bus:
Transfers data from one unit to another.

Address bus:
Carries address information. For example, to
access memory for data, the address of the
memory cell is put onto the address bus. To access
the internal register of an input/output device, the
address of that register is put onto the address bus.

Control bus:
Carries control information. For example, if the
CPU wants to read from a memory cell, CPU (i)
puts the address of the cell onto the address bus,
(ii) activates the READ signal on the control bus.
The memory unit, knowing that it is a read
operation, will take the address from the address
bus, read the addressed cell, and put the data onto
the data bus. The CPU then gets the data from the
data bus.

Chapter 2 30
 As explained in the previous section on digital circuits,
all the above information transfers can be effected by
enabling and disabling the appropriate tri-state buffers
so that the registers holding the information and the
registers receiving the information are connected to the
bus.

Chapter 2 31
Instructions (ref. text Ch. 4.9)

* The control unit signals the ALU what to do

by decoding/interpreting an instruction (which
consists of one or more bytes of information).
* An instruction contains information such as what to
do (operation code), e.g., + , & where data are
located (operand address).

Basic Types of Assembly Instructions

1. Arithmetic or logic instructions,
e.g. + , AND, OR, NEGATE.

2. Program control instructions,

e.g. JMP/BEQ - skip over a block of instructions.

3. Internal data manipulation instructions,

e.g. ASLA - shift the bits of a word.

4. Input output instructions,

e.g. read data from keyboard, output to printer.

Chapter 2 32
Common Instruction Formats
(1) Three-address Instructions
An operation code (op-code) followed by 3
addresses/registers (as in most ARM instructions);
An example of 3-address instruction format:

Operation Destination Source-1 Source-2

Code Addr. / Reg. Addr. / Reg. Addr. / Reg.
(Op-code)
ADD X,Y,Z ; Y+Z X

(2) Two-address Instructions

An operation code (op-code) followed by 2
addresses/registers (as in specific ARM instructions);
An example of 2-address instruction format:

Op-code Destination Source

Addr. / Reg. Addr. / Reg.
As compared to the above 3-address example, its
more economical to use address of the 1st operand to
hold the result and sometimes used as the source as
well (YET the original value of the 1st operand is lost).
MOV A,B ; BA

Most computers are 3-address or 2-address machines.

Chapter 2 33
(3) One-address instructions

To reduce cost further, a special register in the CPU

(Accumulator) is used as both the source and
destination locations. Hence only one address is
needed. This kind of instructions can be viewed as
accumulator-based (as in the MC68HC11)!

Op-code Source
Addr. / Reg.

ADD X; X+ACC ACC

Example of an one-address instruction (ref. text

p154)
On a hypothetical (word length = ) 20-bits computer, let
the operation code (i.e. op code) be 4-bit and the address
as 16-bit.

4-bit
16-bit operand address
op code
19 18 17 16 15 14 ................2 1 0

4-bit op code 16 different instructions can be coded

16-bit address 216 = 65,536 different possible addresses
Chapter 2 34
An example instruction is shown as below.

0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0

op code address code

Assume the op code 0100 represents ADD.
The operand address is 0101101001110010.
For convenience, the binary values can be displayed as
hexadecimal values, e.g. $45A72:
4 5 A 7 2
0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0

op code address code

The instruction informs the CPU to get the data byte from
memory at address $5A72, send it to the ALU, add the
data byte to the integer in the accumulator. The result is
to be stored in the accumulator (i.e. the original integer in
the accumulator (ACC) is lost).

* Note on the Hex notation ($ or H)

To indicate an address/number is Hex, a '$' or 'H' is
appended with it, e.g. $5A72.

Chapter 2 35
An Example of Assembly program (based on 1-
address or accumulator-based instructions)
Basically, a program, no matter expressed in which prog.
lang., = a sequence of instructions.

Assume the 3 hex. integers $10, $A1 & $2B already stored at
consecutive memory cells/units starting at address $E0.

Address Content
$E0 $10
$E1 $A1
$E2 $2B
$E3

The following program computes the sum of these 3

integers and store the result at memory address $E3.

LDAA $E0 ;copy first integer (at addr. $E0) into

accumulator A
ADDA $E1 ;add second integer to accumulator A
ADDA $E2 ;add third integer to accumulator A
STAA $E3 ;store accumulator A's content in memory

Note:
The above program does not compute $E0+$E1+$E2.

Chapter 2 36
Instead, it computes $10+$A1+$2B (i.e. values stored at
addr. $E0..E2) & stores the result $DC at address $E3.

Chapter 2 37
Basic Steps Involved in A Program Execution
The program to be executed is always stored in memory.

In the following example, the simply program consists of 1

instruction only.

Let an operand = $20 which is stored at memory address

$80. The following instruction copies the operand from
memory into accumulator A:

LDAA $80 ; load the value from addr. $80 into ACC-A

Since the op-code for LDAA is $96, the complete instruction

is coded in hex as $9680 (i.e. in fact coded in binary in the
memory).

Let the instruction be stored at memory address $A0.

Hence the memory contains:

Address (Hex) Content (Binary) Content (Hex)

80 00100000 20 (operand)
. . .
. . .
A0 10010110 96 (op-code)
A1 10000000 80 (operand address)

Chapter 2 38
Here are the basic steps to execute the above instruction
($96 $80):

1. Instruction fetch (IF): the CPU fetches (reads) the first

byte from memory at address $A0. The byte obtained from
the memory is $96. The CPU treats it as the op-code.

2. Instruction decode (ID): the control unit decodes this op-

code & finds it to be LDAA. Hence it knows the operand
address is stored at the next memory address. So it fetches
the byte $80 from memory at address $A1 into the CPU.
The CPU treats the byte $80 as the operand address.

3. Operand fetch (OF): the control unit fetches the byte at

address $80 into a data buffer/register of the CPU. The
value obtained from the memory address $80 is $20.

4. Execution (EX): loading the value $20 from the data

buffer/register into the accumulator A (ACC-A) of the
CPU. Execution of the instruction ends.

In summary, the basic steps of executing any instruction

are:
1. Instruction fetch (IF)
2. Instruction decode (ID)
3. Operand fetch (OF)
4. Execution (EX)

Chapter 2 39
After executing the current instruction, if the program
contains more instructions, the CPU fetches the next
instruction, decodes & executes it. This continues until all
instructions in the program have been executed.

Chapter 2 40
Summary: [** The following key points are written to facilitate your revision.
Knowing ONLY these key points is always not sufficient for test or exam.]
Tri-state logic devices for the control of signal flows: when
ENABLE, the normal HIGH/LOW output; else DISABLE (high-
Z) state, output as disconnected from the device!
When multiple device outputs are often connected to the same line
in a data bus, the high-Z state of tri-state logic gates can be set to
avoid bus contention (i.e. two or more buffer outputs compete for
the same data line)!
Basically, flip-flops (FFs) can be used as memory devices to store
binary information in digital computers. The simplest RS FFs
takes two input signals: basically when Set = 1 Output (Q) = 1;
when Reset = 1 Output (Q) = 0. The clocked RS FFs allows the
synchronous changes of states for FFs to exchange information
between the FFs thru the clock signal. The D-type FF is mainly
used to lock up/store binary information.
The Setup time is the minimum time interval before the activation
CLK signal, during which the synchronous input has to be stable
at a proper level for the reliable operation of clocked FFs; whereas
the Hold time is the minimum time interval for that synchronous
input to remain unchanged after the activation CLK signal.
A register is a group of memory devices to store binary
information. The most common register device is the FF. To
transfer data between two groups (X1 and X2 versus Y1 and Y2)
of registers in parallel, simply wire the registers one-to-one to
facilitate the parallel transfer of: [X1][Y1] and [X2][Y2]. For
serial transfer, we need SHIFT registers to shift one bit at a time.

Chapter 2 41
 The basic concepts and operation of data buses: A data bus is a set
of common data lines carrying signals from one device to another.
Always remember to carefully set/unset the Input/Output Enable
of connected devices (tri-state registers) so as to ensure exclusive
access to the concerned data bus at any time!
A decoder is a logic device such that given an input code, the
associated (corresponding) output line is activated, e.g. 3-to-8
binary code decoder. An encoder works in the reverse way of a
decoder. A multiplexer is basically a data selector which can be
implemented by a decoder and some logic gates.
The Arithmetic/logic unit (ALU) is responsible for performing
operations such as +, , , , logical operations such as AND, OR,
etc. with an accumulator (A) and a data buffer register (B). The
immediate result is always stored at the accumulator.
Most modern computers contain five basic units:
(i) datapath: the arithmetic/logic unit (ALU) + registers (or
other functional units), (ii) the control unit [(i) + (ii) = the central
processing unit (CPU)], (iii) the memory, (iv) the input unit, (v)
the output unit.
Basically, computer instructions can be categorized into 4 types: i)
arithmetic or logic, ii) program control, iii) internal data
manipulation and iv) I/O. In general, there can be 3 different kinds
of instruction formats, namely the 3-address, 2-address and 1-
address instructions, depending on the number of operand
address(es) or register(s) allowed in a single instruction.
A (computer) program is basically a sequence of instructions
stored in memory (ROM or RAM) to specify the operations to be
performed in a computer.

Chapter 2 42
 The basic execution cycle of a program is: i) fetch op code, ii)
decode op code, iii) fetch operand, iv) execute the instruction.

Chapter 2 43