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    Isolation: Chapter 3 CMOS Processing Technology

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    Carlos Saavedra
    Oxidation of silicon is commonly achieved through wet oxidation using water vapor at 900-1000°C, dry oxidation using oxygen at 1200°C, or atomic layer deposition layering thin chemical layers. The oxidation process consumes silicon and causes the silicon dioxide layer to project above and below the original silicon surface. Individual transistors in a CMOS process need isolation to prevent unwanted interactions, which was historically provided by thick field oxide and reverse-biased p-n junctions. Shallow trench isolation using insulating trenches of silicon dioxide surrounding transistors was introduced at the 0.35um node to avoid issues with field oxide and allow closer transistor packing.

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    Isolation: Chapter 3 CMOS Processing Technology

    Uploaded by

    Carlos Saavedra
    21 views1 page
    Oxidation of silicon is commonly achieved through wet oxidation using water vapor at 900-1000°C, dry oxidation using oxygen at 1200°C, or atomic layer deposition layering thin chemical layers. The oxidation process consumes silicon and causes the silicon dioxide layer to project above and below the original silicon surface. Individual transistors in a CMOS process need isolation to prevent unwanted interactions, which was historically provided by thick field oxide and reverse-biased p-n junctions. Shallow trench isolation using insulating trenches of silicon dioxide surrounding transistors was introduced at the 0.35um node to avoid issues with field oxide and allow closer transistor packing.

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    CMOS-VLSI-design-133

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    Oxidation of silicon is commonly achieved through wet oxidation using water vapor at 900-1000°C, dry oxidation using oxygen at 1200°C, or atomic layer deposition layering thin chemical layers. The oxidation process consumes silicon and causes the silicon dioxide layer to project above and below the original silicon surface. Individual transistors in a CMOS process need isolation to prevent unwanted interactions, which was historically provided by thick field oxide and reverse-biased p-n junctions. Shallow trench isolation using insulating trenches of silicon dioxide surrounding transistors was introduced at the 0.35um node to avoid issues with field oxide and allow closer transistor packing.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    21 views1 page

    Isolation: Chapter 3 CMOS Processing Technology

    Uploaded by

    Carlos Saavedra
    Oxidation of silicon is commonly achieved through wet oxidation using water vapor at 900-1000°C, dry oxidation using oxygen at 1200°C, or atomic layer deposition layering thin chemical layers. The oxidation process consumes silicon and causes the silicon dioxide layer to project above and below the original silicon surface. Individual transistors in a CMOS process need isolation to prevent unwanted interactions, which was historically provided by thick field oxide and reverse-biased p-n junctions. Shallow trench isolation using insulating trenches of silicon dioxide surrounding transistors was introduced at the 0.35um node to avoid issues with field oxide and allow closer transistor packing.

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    106 Chapter 3 CMOS Processing Technology

    Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere.


    The following are some common approaches:
     Wet oxidation––when the oxidizing atmosphere contains water vapor. The temper-
    ature is usually between 900 °C and 1000 °C. This is also called pyrogenic oxidation
    when a 2:1 mixture of hydrogen and oxygen is used. Wet oxidation is a rapid
    process.
     Dry oxidation––when the oxidizing atmosphere is pure oxygen. Temperatures are
    in the region of 1200 °C to achieve an acceptable growth rate. Dry oxidation forms
    a better quality oxide than wet oxidation. It is used to form thin, highly controlled
    gate oxides, while wet oxidation may be used to form thick field oxides.
     Atomic layer deposition (ALD)––when a thin chemical layer (material A) is attached
    to a surface and then a chemical (material B) is introduced to produce a thin layer
    of the required layer (i.e., SiO2––this can also be used for other various dielectrics
    and metals). The process is then repeated and the required layer is built up layer by
    layer. [George96, Klaus98].
    The oxidation process normally consumes part of the silicon wafer (deposition and
    ALD do not). Since SiO2 has approximately twice the volume of silicon, the SiO2 layer
    grows almost equally in both vertical directions. Thus, after processing, the SiO2 projects
    above and below the original unoxidized silicon surface.

    3.2.5 Isolation
    Individual devices in a CMOS process need to be isolated from one another so that they
    do not have unexpected interactions. In particular, channels should only be inverted
    beneath transistor gates over the active area; wires running elsewhere shouldn’t create par-
    asitic MOS channels. Moreover, the source/drain diffusions of unrelated transistors
    should not interfere with each other.
    The process flow in Section 1.5 was historically used to provide this isolation. The
    transistor gate consists of a thin gate oxide layer. Elsewhere, a thicker layer of field oxide
    separates polysilicon and metal wires from the substrate. The MOS sandwich formed by
    the wire, thick oxide, and substrate behaves as an unwanted parasitic transistor. However,
    the thick oxide effectively sets a threshold voltage greater than VDD that prevents the tran-
    sistor from turning ON during normal operation. Actually, these field devices can be used
    for I/O protection and are discussed in Section 13.6.2. The source and drain of the tran-
    sistors form reverse-biased p–n junctions with the substrate or well, isolating them from
    their neighbors.
    The thick oxide used to be formed by a process called Local Oxidation of Silicon
    (LOCOS). A problem with LOCOS-based processes is the transition between thick and
    thin oxide, which extended some distance laterally to form a so-called bird’s beak. The lat-
    eral distance is proportional to the oxide thickness, which limits the packing density of
    transistors.
    Starting around the 0.35 Rm node, shallow trench isolation (STI) was introduced to
    avoid the problems with LOCOS. STI forms insulating trenches of SiO2 surrounding the
    transistors (everywhere except the active area). The trench width is independent of its
    depth, so transistors can be packed as closely as the lithography permits. The trenches iso-
    late the wires from the substrate, preventing unwanted channel formation. They also
    reduce the sidewall capacitance and junction leakage current of the source and drain.

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