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    Gate and Source/Drain Formations: Chapter 3 CMOS Processing Technology

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    Carlos Saavedra
    This document discusses the gate oxide structure in CMOS processing technology. It describes how current processes use a stack of thin layers of materials like silicon dioxide and oxynitrided oxide to form the gate oxide. This stacked "gate stack" structure provides benefits like increased dielectric constant and thickness while maintaining reliability. The document also discusses how gate and source/drain formations are done using a self-aligned polysilicon gate process, where the polysilicon gate acts as a mask for precise implantation of source and drain regions on either side.

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    Gate and Source/Drain Formations: Chapter 3 CMOS Processing Technology

    Uploaded by

    Carlos Saavedra
    38 views1 page
    This document discusses the gate oxide structure in CMOS processing technology. It describes how current processes use a stack of thin layers of materials like silicon dioxide and oxynitrided oxide to form the gate oxide. This stacked "gate stack" structure provides benefits like increased dielectric constant and thickness while maintaining reliability. The document also discusses how gate and source/drain formations are done using a self-aligned polysilicon gate process, where the polysilicon gate acts as a mask for precise implantation of source and drain regions on either side.

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    CMOS-VLSI-design-135

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    This document discusses the gate oxide structure in CMOS processing technology. It describes how current processes use a stack of thin layers of materials like silicon dioxide and oxynitrided oxide to form the gate oxide. This stacked "gate stack" structure provides benefits like increased dielectric constant and thickness while maintaining reliability. The document also discusses how gate and source/drain formations are done using a self-aligned polysilicon gate process, where the polysilicon gate acts as a mask for precise implantation of source and drain regions on either side.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    38 views1 page

    Gate and Source/Drain Formations: Chapter 3 CMOS Processing Technology

    Uploaded by

    Carlos Saavedra
    This document discusses the gate oxide structure in CMOS processing technology. It describes how current processes use a stack of thin layers of materials like silicon dioxide and oxynitrided oxide to form the gate oxide. This stacked "gate stack" structure provides benefits like increased dielectric constant and thickness while maintaining reliability. The document also discusses how gate and source/drain formations are done using a self-aligned polysilicon gate process, where the polysilicon gate acts as a mask for precise implantation of source and drain regions on either side.

    Copyright:

    © All Rights Reserved
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    108 Chapter 3 CMOS Processing Technology

    Gate Oxide Figure 3.8. The oxide structure is called the gate stack. This
    term arises because current processes seldom use a pure
    SiO2 gate oxide, but prefer to produce a stack that consists
    of a few atomic layers, each 3–4 Å thick, of SiO2 for reli-
    n-well p-well n-well ability, overlaid with a few layers of an oxynitrided oxide
    (one with nitrogen added). The presence of the nitrogen
    Substrate
    increases the dielectric constant, which decreases the effec-
    tive oxide thickness (EOT); this means that for a given oxide
    thickness, it performs like a thinner oxide. Being able to use
    FIGURE 3.8 Gate oxide formation a thicker oxide improves the robustness of the process. This
    concept is revisited in Section 3.4.1.3.
    Many processes in the 180 nm generation and beyond
    provide at least two oxide thicknesses, as will be discussed in Section 3.4.1.1 (thin for logic
    transistors and thick for I/O transistors that must withstand higher voltages). At the 65 nm
    node, the effective thickness of the thin gate oxide is only 10.5–15 Å.

    3.2.7 Gate and Source/Drain Formations


    When silicon is deposited on SiO2 or other surfaces without crystal orientation, it forms
    polycrystalline silicon, commonly called polysilicon or simply poly. An annealing process is
    used to control the size of the single crystal domains and to improve the quality of the poly-
    silicon. Undoped polysilicon has high resistivity. The resistance can be reduced by
    implanting it with dopants and/or combining it with a refractory metal. The polysilicon
    gate serves as a mask to allow precise alignment of the source and drain on either side of
    the gate. This process is called a self-aligned polysilicon gate process. Aluminum could not
    be used because it would melt during formation of the source and drain.
    As a historical note, early metal-gate processes first diffused source and drain regions,
    and then formed a metal gate. If the gate was misaligned, it could fail to cover the entire
    channel and lead to a transistor that never turned ON. To prevent this, the metal gate had
    to overhang the source and drain by more than the alignment tolerance of the process.
    This created large parasitic gate-to-source and gate-to-drain overlap capacitances that
    degraded switching speeds.
    The steps to define the gate, source, and drain in a self-aligned polysilicon gate are as
    follows:
     Grow gate oxide wherever transistors are required (area = source + drain + gate)––
    elsewhere there will be thick oxide or trench isolation (Figure 3.9(a))
     Deposit polysilicon on chip (Figure 3.9(b))
     Pattern polysilicon (both gates and interconnect) (Figure 3.9(c))
     Etch exposed gate oxide—i.e., the area of gate oxide where transistors are required
    that was not covered by polysilicon; at this stage, the chip has windows down to
    the well or substrate wherever a source/drain diffusion is required (Figure 3.9(d))
     Implant pMOS and nMOS source/drain regions (Figure 3.9(e))
    The source/drain implant density is relatively low, typically in the range 1018–1020
    cm–3 of impurity atoms. Such a lightly doped drain (LDD) structure reduces the electric
    field at the drain junction (the junction with the highest voltage), which improves the
    immunity of the device to hot electron damage (see Section 7.3.6) and suppresses short-
    channel effects. The LDD implants are shallow and lightly doped, so they exhibit low

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