International Journal of Electrical Engineering.

ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 53-60

© International Research Publication House
http://www.irphouse.com

Design and Analysis of Double Gate MOSFET Devices using

High-k Dielectric

Asha Balhara* and Divya Punia

Department of E.C.E., B.P.S. Women University, khanpur kalan, Sonepat, India.

*E-mail id: ashabalhara89@gmail.com

Abstract

Double gate MOSFET is one of the most promising and leading contender for
Nano regime devices. In this paper an n-channel symmetric Double-Gate
MOSFET using high-k (TiO2) dielectric with 80nm gate length is designed
and simulated to study its electrical characteristics. ATHENA and ATLAS
simulation tools from SILVACO are used in simulating electrical performance
and analyzing the effectiveness of double gate MOSFET. High-k gate
technology is emerging as a strong alternative for replacing the conventional
SiO2 dielectrics gates in scaled MOSFETs for both high performance and low
power applications. High-k oxides offer a solution to leakage problems that
occur as gate oxide thickness’ are scaled down. Non-ideal effect of a
MOSFET design such as short channel effects are investigated. The most
common effect that generally occurs in the short channel MOSFETs are
channel modulation, drain induced barrier lowering (DIBL). It is observed in
the results that the device engineering would play an important role in
optimizing the device parameters.

Keywords- MOSFET-metal oxide semiconductor field effect transistor; DG-

MOSFET-double-gate MOSFET; SG-MOSFET-single gate MOSFET; SCE-
short channel effects; High-k; DIBL-drain induced barrier lowering; TiO2.

Introduction
Double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and
related multiple-gate device architectures are nowadays widely identified as one of
the most promising solutions for Nanoscale integration [7].With one extra gate, the
gate to channel coupling is doubled resulting in good reduction of SCE’s [5].These
devices present an excellent Ion/Ioff trade off, very good control of short-channel
effects and potentially higher channel conductivity [7] as compared to planar
54 Asha Balhara* and Divya Punia

MOSFET devices with a single gate. When the gate length becomes comparable of
depletion region then short channel effects are seen but in DG-MOSFET we are able
to reduce these effects. Because of having two gates in DG-MOSFET both gates
control the channel from both sides and have better electrostatic control over the
channel. So we can perform more scaling of gate length. Due to better control on
short channel effects DG-MOSFET is better alternative of conventional bulk
MOSFET and it has higher current density, higher sub-threshold swing at low supply
voltages. Thus we are able to maintain the device performance in term of higher
current density and low leakage by using DG-MOSFET [5].
In recent times DGMOSFET device structures have drawn more attention of the
researchers due to their inherent capability of suppressing the short channel effects.
Due to two-channel formation in symmetrical DGMOSFET, it shows steep sub-
threshold swing, high drive current and transconductance [5].
In order to prevent direct gate tunneling in very thin oxides envisaged for the end-
of-the roadmap nodes, the SiO2 is replaced by alternative materials with higher
permittivity and greater physical thickness. However, the introduction of these high-k
dielectrics poses several problems, such as bi-dimensional electrostatic effects which
may have a dramatic impact on the device performances when the gate dielectric
thickness becomes comparable to the device gate length [7].
In this paper section II contains a description about High-k dielectric (TiO2) while
section III gives a brief introduction of Double-gate MOSFET structure. Section IV
would describe the design and simulation of N-channel DGMOSFET device with all
the results and analysis discussed in section V.

HIGH-k DIELECTRIC MATERIALS

Using an insulator with higher dielectric constant is one of the solutions to continue
scaling in nanometer regime with suppressing the SCEs. The alternative insulator
should have the following properties [2] : (i) chemical and electrical stability on
silicon, (ii) uniform oxide thickness during fabrication, (iii) high breakdown voltage,
(iv) thermal stability up to 1000○C, (v) pinhole free and negligible defects, (vi) low
charge trapping and ionic impurities, (vii) high life time under normal operating
conditions, (viii) low interface state density for high carrier mobility, (ix) small gate-
leakage current (x) low hot-carrier degradation, (xi) low diffusivity of boron and
phosphorous at typical processing conditions. Some of these properties depend on the
material as well as on the processing technology. At first Campbell et al. introduced
TiO2 as the potential high-k gate dielectric [2]. Later various research groups work on
the feasibility of other alternative high-k dielectric (e.g. Al2O3, ZrO2, Ta2O5, HfO2,
ZrSixOy, Y2O3, Ya2O3) for submicron MOSFET. The various dielectric materials are
shown with their properties in table1. All these high-k materials have some practical
limitations [2]. In this paper study is laid upon using titanium oxide as high-k
dielectric for the DGMOSFET structure. So, Titanium oxide (TiO2) is briefly
discussed below with some of its advantages.
Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric 55

Table 1 High-k dielectric materials and their properties [2].

Gate Dielectric Energy Conduction Valence

dielectric constant bandgap band offset band offset
Material (k) Eg (eV) ∆Ec (eV) ∆Ec (eV)
SiO2 3.9 9 3.5 4.4
Al2O3 8 8.8 3 4.7
TiO2 80 3.5 1.1 1.3
ZrO2 25 5.8 1.4 3.3
HfO2 25 5.8 1.4 3.3
Ta2O5 25 6 1.5 3.4
Y2O3 13 6 2.3 2.6
Ya2O3 27 4.3 2.3 0.9

Titanium Dioxide (TiO2)as gate dielectric.

TiO2 has been used as an alternative gate dielectric material for deep submicron
MOSFET’s earlier in 1995[2].
Advantages: The dielectric constant of TiO2 is 80. The bandgap of the material is
3.5eV for amorphous films and 3.2eV for crystalline films. These band gaps are good
for semiconductor but higher bandgap is required to act as an effective insulator [2].
The TiO2 has low energy band offset with respect to Si. TiO2 has EOT of less than
10Å. Transistors made with TiO2 shows near ideal behavior but they have challenges
with mobility. It has been shown that the low field effective mobility is approximately
160cm2/V-s, which is about a three order lower than the mobility in SiO2 based
MOSFET’s. This mobility reduction is due to interface trap state and surface
roughness at TiO2/Si interface. The electron traps in TiO2 is due to oxygen vacancy.
An empirical relationship between the effective mobility and the interface state
density [2] which is given by equation 1,
μ
…….. (1)
μ D
where Dit is the concentration of charged states at the bias condition and α is a
constant. So the effective mobility is inversely related with Dit [2].
In Si/SiO2 interface bond strain causes fixed charge which is about 0.1% of the
interface atoms (1010-1011cm2). So for strained-Si/TiO2 leakage occurs from these
defects as well as from low conduction band discontinuity. Therefore, ultra-thin SiO2
can be incorporated between TiO2 and strained-Si layer to reduce the defect states at
the interface. Therefore if TiO2 is grown on (100) Si substrate Dit decreases and the
mobility increase [2].
Mobility can also be increased by growing TiO2 gate dielectric stack on Si
substrate. The device speed can be improved by 20-80% at a constant gate length by
using high mobility strained-Si at the channel region. TiO2 reduces gate leakage and
Si enhances the device speed. Hence TiO2 is our choice of high-k dielectric gate
material [2].
56 Asha Balhara* and Divya Punia

DOUBLE-GATE MOSFET STRUCTURE

In DG-MOSFET structure we use two gates namely top gate (G1) and bottom gate
(G2). The intimate coupling between the gates and the channel makes DG MOSFET
technology the most scalable of all MOSFET designs. The DG-MOSFET is
electrostatically superior to a single-gate MOSFET because two gates are used to
control the channel from both sides. This allows additional gate length scaling by
nearly a factor of two. The two gates together control roughly twice as much current
as a single gate, resulting in stronger switching signals [1]. Due to double gate
structure, gate to channel coupling gets doubled and hence SCE’s can be suppressed
easily [5].

Figure 1: Double-gate MOSFET structure using high-k dielectric.

Figure 1 shows a general structure of a double gate MOSFETs. Here we are using
polysilicon gate technology and high-k dielectric (TiO2) as gate oxide to suppress the
short channel effects.

Types of DG-MOSFET
Depending upon the way the gate voltages are applied, DG-MOSFETs may be
categorized as following [5]:

Symmetric DG-MOSFET
A DG-MOSFET is said to be symmetric when both gates have the same work
function and a single input voltage is applied to both gates [4].

Asymmetric DG-MOSFET
An asymmetric DG-MOSFET either has synchronized but different input voltages to
both of the identical gates, or has the same input voltage to two gates but gates having
different work functions [5].
The name of “symmetric” and “asymmetric” essentially depicts presence or
absence of symmetry of the electric field inside the channel of the DG-MOSFET [5].
Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric 57

Design & Simulation

In this work we had designed an n-channel polysilicon gate symmetric DG-MOSFET
with 80nm gate length on ATHENA process simulator considering the standard
Silicon Integrated chip processing technology and its electrical performance is
characterized using ATLAS device simulator. TiO2 is used as gate oxide material and
spacers are also used on both sides to reduce fringing field effect.
The specifications of the Silicon substrate considered for the design are p-type
Boron doped substrate with doping concentration of 1 x 1018 atoms cm-3 and <100>
orientation. The design structure of DGNMOSFET using TiO2 gate dielectric with
Polysilicon gate is considered to explore the advantages of TiO2 over SiO2 dielectric.
The simulated structure, which are based on fully scaled 80 nm gate length
MOSFET’s proposed in the ITRS, have gate length of 80 nm, with effective oxide
thicknesses (EOT) of 2nm. The dielectric constant of TiO2 gate dielectric was
considered to be 80. Steep retrograde channel doping is used with surface doping
concentration of 8 x 1012 cm-3. The complete summary of DG-NMOSFET process
flow is given below in table 2.

Table 2 Summary of DG-NMOSFET design features process flow.

PROCESS DG-NMOSFET
Initial substrate doping, Na Boron, B = 1 x 1018 cm-3
Retrograde well Boron, B = 8 x 1012 cm-2
E =100keV
Gate oxide thickness, tox 2.0nm
Source/drain implant Arsenic, As = 9.5 x 1011 cm-3
E = 10keV
Halo Implantation Boron, B = 3 x 1013cm-2
E =20keV / 30°
Spacer deposition 100nm
Source/Drain implant Arsenic, As = 6.6 x 1017cm-2
E =82.75keV
Final Rapid Thermal (RTA) 1000oC/1 sec

RESULTS & DISCUSSION.

The results of fabrication & simulation of 80nm NMOS can be viewed in the
TONYPLOT as shown below.
58 Asha Balhara* and Divya Punia

Figure 2: Simulated structure of symmetric DG- NMOSFET using TiO2 with 80nm
gate length.

The simulated device structure (figure 2) is a symmetric N-channel DGMOSFET

with following parameters mentioned below in table 3:

Table 3: Device parameters taken for process simulation of device design using
ATHENA simulation tool.

PARAMETERS DG-NMOS with TiO2

Sheet resistance (Ω/square) 1624.97
Channel concentration (atoms/cm3) 5.06249e+017
Gate oxide thickness, tox (µm) 0.00208031 µm (2.08031nm)
Gate length (µm ) .08
Gate width (µm) .2
Channel length (µm) .05
Channel width (µm) .6

The simulated DG-NMOSFET structure with source/drain junction depth and net
doping concentration is shown below in figure 3.
Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric 59

Figure 3: DG-NMOSFET structure showing the junction depth.

CONCLUSION
Symmetric N-channel DG-MOSFET structure with 80 nm gate length was designed
and simulated to study the effect of high-k dielectric (TiO2), additional gate and oxide
thickness on the device performance. It was found that some of the parameters like
threshold voltage, sub-threshold swing and DIBL were reduced while drain current
was increased upon applying high-k dielectric and additional gate on planar MOSFET
device structure. The sub-threshold leakage current was found to be decreased with
increasing threshold voltage; this reduces the power consumption and thus improves
the device performance. The reduction in gate leakage and sub-threshold swing
projects the high-k Double-Gate MOSFET structure to be a strong alternative for
future Nanoscale MOS devices. It can also be concluded from the analysis that as
device was scaled down, the threshold voltage of the device decreases. Hence, to
adjust the threshold voltage and other short channel effects within the permissible
limits device engineering can be employed.

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60 Asha Balhara* and Divya Punia

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