IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO.

1, JANUARY 2018 51

Heteroepitaxial Diamond Field-Effect Transistor

for High Voltage Applications
Mohd Syamsul , Nobutaka Oi, Satoshi Okubo, Taisuke Kageura, and Hiroshi Kawarada

Abstract — The exceptional performance of diamond- single crystalline diamond film growth is the heteroepitaxial
based field-effect transistor technology is not restricted to growth method, which was established in the early 1990s [10].
devices that use single crystalline diamond alone. This letter Following this discovery, and with the same objective of single
explores the full potential of the heteroepitaxial diamond
field-effect transistor (HED-FET). HED-FET devices were crystalline growth, in-depth numerical research on refinement
fabricated with a long gate–drain length (LGD ) configuration of heteroepitaxial diamond growth on SiC has also been
using C–H bonded channels, and a high maximum current conducted [11]. The highly-oriented heteroepitaxial diamond
density of 80 mA/mm and a high ION /IOFF ratio of 109 were films have shown promise, with advantages similar to those
achieved. Additionally, the HED-FETs showed an average of conventional single crystalline diamond. It has previously
breakdown voltage of ≥500 V and comparatively high break-
down voltage of more than 1 kV. This letter represents a been shown that hydrogenated diamond-based single and poly-
significant step toward the realization of the potential of crystalline diamond FETs have surpassed a variety of previous
widely available heteroepitaxial diamond for use in FET FET performance levels, including those of low on resistance
applications. (R O N ) and high-frequency performance ( f max ) short gate-
Index Terms — Diamond, FETs, heteroepitaxial, drain length devices [12], [13], and we recently showed
two-dimensional hole gas, high voltage. that high-performance devices can also be achieved despite
the unappealing large grain boundaries and cracks in black
I. I NTRODUCTION polycrystalline diamond [14]. These however, did indicate
that few studies have explored the potential of heteroepitaxial
D IAMOND-BASED field-effect transistors (FETs) have
been established as promising candidates for use in
high-power electronic device applications in the near future.
diamond layers on a large-scale wafer for FET applications
and this has motivated the present work. Heteroepitaxial
Numerous papers have been published on diamond FETs and diamond FET (HED-FET) devices that use two-dimensional
have reported outstanding results, demonstrating performance hole gas (2DHG) systems were fabricated. These findings
levels with much of the work focusing on hydrogenated show that the HED-FET has similar I D Smax and I O N /I O F F
diamond devices due to its simple structure [1]–[3], high ratio characteristics to those of the homoepitaxial layer based
frequency [4]–[7], and temperature operations [8]. Diamond- FETs conventional device. This is the first work to report on
based FETs have also reported to offer stable operation at the breakdown voltages of HED-FETs.
high temperature ranging up to 400°C, and high breakdown
II. FABRICATION
voltage devices have been realized to satisfy the robustness
requirements of devices for high voltage operation at an aver- On the 3C-SiC 001 grown on Si 001, nitrogen-doped
age electric field of 1 MV/cm [9]. One alternative method for heteroepitaxial diamond 001 substrate was synthesized by
microwave plasma chemical vapor deposition (MPCVD)
Manuscript received September 25, 2017; revised October 25, 2017; equipped with counter electrode and electronically isolated
accepted November 6, 2017. Date of publication December 1, 2017;
date of current version December 27, 2017. This work was supported substrate holder in situ by means of bias-enhanced nucleation.
in part by a Grant-in-Aid for Fundamental Research S from JSPS under Thorough crystallographic information has been reported else-
Grant 26220903 and in part by the Advanced Low Carbon Technology where [15]. HED-FET device fabrication processes started
Research and Development Program of JST. The review of this
letter was arranged by Editor D. G. Senesky. (Corresponding author: with the deposition of a 500 nm undoped homoepitaxial
Mohd Syamsul.) diamond layer by plasma enhanced chemical vapor deposi-
M. Syamsul, N. Oi, S. Okubo, and T. Kageura are with the tion (PECVD). These layers contained unintended concen-
Faculty of Science and Engineering, Institute of Nano-Science and
Nano-Engineering, Waseda University, Tokyo 169-8555, Japan (e-mail: trations of boron and nitrogen dopants of <1014 cm−3 and
naysriq@asagi.waseda.jp ). <1016 cm−3 , respectively. Metal bilayers of gold and titanium
H. Kawarada is with the Faculty of Science and Engineering, for the source and drain electrodes were formed by sequential
Institute of Nano-Science and Nano-Engineering, Waseda University,
Tokyo 169-8555, Japan, and also with the Kagami Memorial Lab- deposition processes and were further annealed for 30 minutes
oratory for Material Science and Technology, Waseda University, in a hydrogen ambient at 450 °C to form a TiC layer on
Tokyo 169-0051, Japan. their undersides. Hydrogenation was performed for 6 min
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org. across the entire surface using a 600°C H2 plasma. The sheet
Digital Object Identifier 10.1109/LED.2017.2774290 resistance, carrier density and carrier mobility values were

0741-3106 © 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted,
but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
52 IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 1, JANUARY 2018

determined to be 18−20 k/sq, 1−10 × 1013 cm−2 and

30−38 cm2 V−1 s−1 , respectively, for the HED. Followed by
photoresist masking of the horizontal channel between the
source and the drain. A narrow channel was formed between
the source and drain Ti (30 nm)/Au (100 nm) bilayers after the
isolation process by oxidation, using an ultraviolet (UV)-ozone
treatment to form a C-O bonded surface. 2DHG was formed
on the narrow channel after passivation and gate insulator layer
of 200-nm-thick Al2 O3 was deposited on top of the surface
(with the exception of the source and drain layers) at 450 °C
by alternate exposure to H2 O and trimethylaluminum, and was
followed by aluminum deposition to form the gate electrode
and the source and drain contacts [16]. Figure 1(a) shows a
three-dimensional diagram of the HED-FET that was fabri-
cated with gate width (WG ) of 25 μm.

III. C URRENT-VOLTAGE C HARACTERISTICS

Two HED-FET devices were measured at room tem-
perature using the Agilent Technologies (Keysight) B1505
Power Device Parameter Analyzer and a vacuum probe
system (Nagase Techno-Engineering). Figure 1 shows the
characteristics of two HED-FET devices with L G D values
of 17 μm and 21 μm. To measure the I D S -V D S character-
istics, the gate-source voltage VG S was varied from 60 V
to −20 V (in 10 V steps) for the HED-FETs. These devices
show obvious p-type channel FET characteristics. The maxi-
mum drain current I Dmax values for the corresponding devices
were measured as follows: the HED-FET with L G D of 17 μm
had I Dmax of 55.6 mA/mm (see Fig. 1(b)), while that with
L G D of 21 μm had I Dmax of 81.2 mA/mm (see Fig. 1(c))
at VDS = 50 V. For comparison, the I Dmax values of
the HED-FETs of 55.6 mA/mm and 81.2 mA/mm for L G D
values of 17 μm and 21 μm, respectively in terms of absolute
values. This is an unexpected odd tendency, because larger
L G D results in higher conductance. These current densities
are 20 - 30% smaller than those of homoepitaxial layer based
FETs.
Via transfer characteristics at a constant V D S = −10 V for
these devices are also shown in Fig. 2. The I O N /I O F F ratios
for the HED-FETs with the L G D of 17 μm shown in Fig. 2(a)
and the L G D of 21 μm shown in Fig. 2(b) were both of the
order of up to 109 , which is similar to the corresponding value
Fig. 1. (a) Diagram of HED-FET and 2DHG horizontal channel between
for the homoepitaxial layer based FET. From these curves, the the source and drain. Electrical characteristics, IDS -VDS of HED-FET
threshold voltage (VT H ) absolute values were also determined (b) LGD of 17 µm and (c) LGD of 21 µm.
to be 18 V for both of the HED-FETs with L G D of 17 μm
and L G D of 21 μm respectively, based on the absolute square
root of I D S versus VG S . gate/Al2 O3 interfaces of the HED-FET devices when a high
V D S was applied. A device achieves a high breakdown volt-
IV. B REAKDOWN VOLTAGES age when the occurrence of impact ionization is delayed.
Figure 3 shows the average breakdown voltages of Energetic holes that were excited by high bias affects the
over 500 V for devices with seven different L G D values; breakdown voltages. These energetic holes tunnels into the
devices with L G D values of 11 μm, 14 μm, 16 μm, 17 μm, Al2 O3 passivation layer and/or the heteroepitaxial diamond
18 μm, 19 μm, 20 μm and 21 μm showed breakdown voltages substrate. These energetic holes induces impact ionization.
of 699 V, 540 V, 840 V, 1120 V, 780 V, 980 V, 698 V The I D S behavior shown in HED-FET devices before they
and 560 V respectively, at VG S = 20 V. The breakdown approach breakdown can be divided into three categories.
voltages in these HED-FETs correlated with the electric field Gradual I D S increments indicate suppression by the Al2 O3
distributions alongside the gate-edge point and the drain. passivation layer to counter the impact ionization phenomenon,
High concentrated electric field spikes were located at the while a sudden radical rise in I D S indicates high occurrence of
SYAMSUL et al.: HED-FET FOR HIGH VOLTAGE APPLICATIONS 53

TABLE I
E LECTRICAL P ROPERTIES OF HED-FET

voltage reaches >200 V; however, a second voltage increment

is followed by a slow increase in I D S until the device reaches
breakdown at 1120 V. Initially, a small leakage occurs within
the Al2 O3 passivation layer, indicates its vulnerability, fol-
lowed by very stable suppression behavior until further gradual
increases in IDS cause the device to reach breakdown. This
illustrates the mediocre quality of the Al2 O3 passivation layer.
Low leakage and small increments in I D S were shown for the
19 μm L G D device from the initial stage until final breakdown
at 980 V. This indicates a fairly firm Al2 O3 passivation layer.
The leakage current is higher by a factor of 102 to 103
(2 to 3 orders) when compared with that of the homoepitaxial
layer based FETs. This is due to heteroepitaxial/SiC interface
Fig. 2. Transfer characteristics, IDS -VGS in linear and log |IDS |-VGS and can be improved by the removal of SiC layer and Si
characteristics of (a) LGD of 17 µm and (b) LGD of 21 µm. substrate. In addition, further improvements can be made
by structural modifications such as use of field-plated [17]
and triple gate [18] device architectures, as indicated by
the indistinguishable performances shown by the HED-FET
devices during high voltage measurements. The HED-FET
shows adequate FET behavioral performance similar to those
of single diamond FETs, more than 10 times higher current
density than those of diamond JFET [19] and MESFET [20]
formed by highly boron doped layers. Assessment based
on the characteristics listed in Table I indicates that the
HED-FET shows several of the unique traits comparable to the
homoepitaxial layer based FETs. However these unexpected
odd tendencies can be observed and still open for further
investigation.
V. C ONCLUSIONS
HED-FET device was demonstrated to be a credible
candidate to provide widespread availability of diamond-based
high-power FETs with several unique properties, including
Fig. 3. HED-FET device average breakdown characteristics exceeding high maximum current densities and high I O N /I O F F ratios
500 V for several wide LGD (11 µm to 21 µm) devices. comparable to those of lateral planar diamond devices.
In addition, HED-FETs were also shown to have high average
the impact ionization phenomenon, and a slow increase in I D S breakdown voltages and high maximum breakdown voltages.
indicates the suppression effect of the Al2 O3 passivation layer These new findings for heteroepitaxial diamond devices
in temporarily limiting further occurrences of impact ioniza- will thus drive further advancements in diamond-based FET
tion. For example, in the 11 μm L G D device, high leakage devices because they offer no limitations in terms of device
currents and radical increments occur until the device reaches size or availability on a large scale.
breakdown due to high occurrences of impact ionization, thus
indicating a vulnerable Al2 O3 passivation layer. The 17 μm ACKNOWLEDGMENT
L G D device exhibits an increment in IDS of less than 102 Additional contributors were C. Wild, N. Herres, E. Wörner,
(2 orders) initially and this remains stable until the applied and P. Koidl, the ex-members of Fraunhofer IAF, Germany.
54 IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 1, JANUARY 2018

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