Name: P.Aswin Bharathi Date: 24-02-2021 Reg - Num: 9519005303 Experiment Number: 1 Study of Embedded Soc in Fpga Aim

Name: P.
ASWIN BHARATHI DATE: 24-02-2021
Reg.Num: 9519005303 Experiment Number: 1
Study of Embedded SoC in FPGA
AIM:
To study about the architecture and pin details of Altera Cyclone V FPGA Starter
Development Kit
COMPONENTS/APPARATUS/SOFTWARE REQUIRED:
• Altera Cyclone V -DE I SoC 4
• Modelsim
• Virtual Lab: https://eceklu.labsland.com/?lang=en
THEORY: (FPGA introduction, block diagram, pin details, components, FPGA

programing steps)
Name Description
SW: in std_logic_vector(9 downto 0) 10 virtual switches, numerated 0 to 9. You will be

able to set them to 1 or 0 until you change the
(or) switch value.
V_SW: in std_logic_vector(9 downto 0)

KEY: in std_logic_vector(3 downto 0) 4 virtual buttons, numerated 0 to 3, active low. By
default they will send 1, and whenever you click
(or) them they will become 0 for a short period of time.
You can keep the button pressed if you want to
V_BT: in std_logic_vector(3 downto 0) keep sending a 0, but once you release it, it will
become 1 again.
Additionally, you will be able to refer to board peripherals with the following abstract names (which will
be the same across boards):
Name Description
CLOCK_50: in std_logic Clock that works at 50 MHz.
(or)
G_CLOCK_50: in std_logic
LEDR: out std_logic_vector(9 downto 10 red LEDs, numerated 0 to 9. They are

0) guaranteed to be red.
(or)
G_LEDR: out std_logic_vector(9

downto 0)
G_LED: out std_logic_vector(9 downto 10 LEDs, numerated 0 to 9. They are the same
0) LEDs as the red ones above.
HEX0: out std_logic_vector(6 downto Seven-segment display number 0.

0)
(or)
G_HEX0: out std_logic_vector(6

downto 0)

0)
(or)

downto 0)

0)
(or)

downto 0)

0)
(or)
downto 0)
0)
Name Description
(or)

downto 0)

0)
(or)

downto 0)
FPGA Implementation Steps:
• Open Labsland using the link: https://labsland.com/en/labs/fpga-llstd1

• Create a student account then Access FBGA Laboratory.
• Followed by, Access VHDL IDE and start developing the code, Synthesis it and
upload /simulate it with the virtual FBGA Board.
This is how the IDE would look:
Create a new file and start coding.
Below image represent how the created file window would appear here. Further
modifications can also be done.
Above picture depicts how code synthesize is done. Followed by that this below
window which gives the compilation feedback for the code will help programmers to
analyze the error.
After the code was compiled perfectly with zero errors a green pop up would appear.
Meaning the code is verified successfully and it’s completely safe to upload the code
into Virtual FBGA board.
This is how the virtual FBGA board would look. Here the practical process takes place
by switching the switch into on and off mode and output verification is done with the
help of LED’s.
CONCLUSION:
Thus, in this manner every VHDL programs are developed and uploaded into Virtual
FBGA board. Screenshots are further taken for output submission.
VIVA QUESTIONS:
1. WHAT IS FPGA?
2. LIST THE COMPONENTS OF ALTERA CYCLONE II FPGA KIT
3. GIVE THE FPGA PIN DETAILS OF SWITCH, PUSH BUTTON INTERFACE
WITH FPGA.
4. GIVE THE FPGA PIN DETAILS OF SEVEN SEGMENT LED INTERFACE WITH
FPGA.
5. COMPARE PLD AND FPGA
6. LIST THE TOP FPGA DESIGN COMPANIES.
7. WHAT ARE THE FPGA PROGRAMMING Languages?
8. WHAT ARE THE FPGA PROGRAMMERS?
ANSWERS:
1. FPGA stands for field-programmable gate array. An FPGA is an array of logic gates
that are hardware-programmed to perform a user-specified task. FPGAs are arrays of
programmable logic cells interconnected by a matrix of wires and programmable
switches. Each cell in an FPGA performs a simple logic function.
A FPGA can be used if the design requires complex logic and requires high processing
ability and if the cost is comparable to the performance achieved.
2. The Cyclone II FPGA Starter Development Kit features:
• Cyclone II Starter Development Board

• Cyclone II EP2C20F484C7N device
Configuration -
• USB-BlasterTM download cable (embedded)

• EPCS4 serial configuration device
Memory - 8-Mbyte SDRAM, 512-Kb SRAM, 1- to 4-Mbyte flash
Switches and indicators -
• Ten switch and four push buttons

• Four, 7-segment displays
• Ten red and eight green LEDs
Audio - 24-bit coder/decoder (CODEC)
Connectors –
• VGA, RS-232, and PS/2 ports

• Two 40-pin expansion ports
• SD/MMC socket, Cables/power
• USB cable
Clocking - SMA connector (external clock input)
3.
4.
5.
FPGA CPLD
1) Field – Programmable Gate Array, is a 1) Complex programmable logic device, is

type of programmable logic chip has more also other type of digital logic chip but has
complex architecture. less complex architecture.
2) FPGA contains up to 100,000 of tiny 2) CPLD contains only few blocks of logic
logic blocks. that reaches up to few thousand.
3)In terms of architecture, FPGA are 3) In terms of architecture, CPLD are

considered as “Fine Grain” Devices considered, as “Coarse-grain” devices.
4) CPLD are better for simpler application.

4) FPGA are useful for more complex
application.
5) FPGA, are made up of tiny blocks. 5) CPLD are, made up of larger blocks.
6) FPGA is RAM-Based digital logic chip.

6) CPID, is EEPROM-based digital logic
chip.
7) White, CPLD are much cheaper.

7) FPGA are more expensive as compared
to, CPLD
8) Delays are less predictable as compared 8)Delays are much more predictable in
to CPLD. CPLD as compared to FPGA’s
6.
• Xilinx
• Altera.
• Lattice Semiconductor.
• Microsemi (was Actel)
• Quick Logic. Webs
7. Two programming languages have traditionally accounted for most FPGA

programming in the usual HDL style: VHDL and Verilog.
Verilog was designed in the mid 1980’s, and is somewhat more C-like than VHDL. It is
conceded by some to be easier to use than VHDL because of simpler syntax and fewer
constructs [Verilog08].
VHDL was originally created for the Department of Defense (DoD) to document the
behavior of ASICs that were created by supplier companies. Its syntax is similar to that
of the Ada programming language, also developed for the DoD
8. FPGA Programmers are responsible at the operational level, to develop the

hardware design of a new FPGA platform. As such, they work in conjunction with the
software team to define and implement verification flow. They also provide FPGA
design services for customers when needed.

Name: P.Aswin Bharathi Date: 24-02-2021 Reg - Num: 9519005303 Experiment Number: 1 Study of Embedded Soc in Fpga Aim

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Name: P.Aswin Bharathi Date: 24-02-2021 Reg - Num: 9519005303 Experiment Number: 1 Study of Embedded Soc in Fpga Aim

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Name: P.

ASWIN BHARATHI DATE: 24-02-2021

Reg.Num: 9519005303 Experiment Number: 1

Study of Embedded SoC in FPGA

• Altera Cyclone V -DE I SoC 4

THEORY: (FPGA introduction, block diagram, pin details, components, FPGA

SW: in std_logic_vector(9 downto 0) 10 virtual switches, numerated 0 to 9. You will be

V_SW: in std_logic_vector(9 downto 0)

CLOCK_50: in std_logic Clock that works at 50 MHz.

LEDR: out std_logic_vector(9 downto 10 red LEDs, numerated 0 to 9. They are

G_LEDR: out std_logic_vector(9

HEX0: out std_logic_vector(6 downto Seven-segment display number 0.

G_HEX0: out std_logic_vector(6

HEX1: out std_logic_vector(6 downto Seven-segment display number 1.

G_HEX1: out std_logic_vector(6

HEX2: out std_logic_vector(6 downto Seven-segment display number 2.

G_HEX2: out std_logic_vector(6

HEX3: out std_logic_vector(6 downto Seven-segment display number 3.

G_HEX4: out std_logic_vector(6

HEX5: out std_logic_vector(6 downto Seven-segment display number 5.

G_HEX5: out std_logic_vector(6

FPGA Implementation Steps:

• Open Labsland using the link: https://labsland.com/en/labs/fpga-llstd1

2. The Cyclone II FPGA Starter Development Kit features:

• Cyclone II Starter Development Board

• USB-BlasterTM download cable (embedded)

• Ten switch and four push buttons

• VGA, RS-232, and PS/2 ports

1) Field – Programmable Gate Array, is a 1) Complex programmable logic device, is

3)In terms of architecture, FPGA are 3) In terms of architecture, CPLD are

4) CPLD are better for simpler application.

6) FPGA is RAM-Based digital logic chip.

7) White, CPLD are much cheaper.

7. Two programming languages have traditionally accounted for most FPGA

8. FPGA Programmers are responsible at the operational level, to develop the

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