Part 2 Synchronous Counters

1. Introduction
• Counters discussed so far are called asynchronous or ripple counters. In general they are
constructed with T-FFs and triggered in series.
• Their main advantage is design simplicity.
• Their major disadvantage is the accumulation of flip flop delays. This latter limits the
speed of counting.
• For proper counter operation we need
TClk ≥ n * tpd
Where TClk is the period of the clock, Clk, n is the number of cascaded flip-flops and tpd
the propagation delay of one flip-flop. The maximum frequency of counting is therefore
given by
fmax ≤ 1/(n * tpd)
It is clear that when the number of FFs in the counter increases, the total propagation
delay increases and fmax decreases.
For example, a 10-bit asynchronous counter that uses FFs with a tpd = 50 ns, then the
maximum frequency that can be applied is
fmax ≤ 1/(10 * 50*10-9) = 2 MHz
Asynchronous counters are not suitable at very high frequencies, especially for counters
with a large numbers of bits.
• This limitation can be overcome with the use of synchronous or parallel counters.
• In this arrangement, ALL flip-flops are clocked simultaneously by the same clock signal.
Combinational logic must be provided (calculated) attached to the flip-flop inputs to
produce the desired sequence. Figure 1 illustrates the general block diagram of a
synchronous counter
• Due to its parallel arrangement, a synchronous counter can operate at a much higher
frequency; the circuitry however is more complex compared to a ripple counter.
• Moreover, in this mode, it is possible to design a counter that can scan through any
sequence and possibly have more than 2-different directions of counting.

Q
Counting
Mode
Combinational

Q
Logic

Q’s ●

Q
●

Clock

Figure 1 Arrangement of a synchrnous counter

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In the above arrangement, any type of flip-flop can be involved in the design of synchronous
sequential counters

2. Procedure to design synchronous counters

This section presents a systematic technique for designing synchronous sequential counters that
follow arbitrary sequence(s). The procedure can be used for any flip-flop type.
Procedure
1. Draw a state graph (state diagram) that specifies the desired sequence(s) of the counter
2. Determine the number of flip-flops required.
i- If the counter is a Mod-N, then k ≥ log2 N
ii- If the sequence is irregular, than determine the number of bits required to
represent the largest count in the sequence(s)
3. Select the type of flip-flop to be used
4. Construct a transition table from the state diagram
5. Reduce each flip-flop input variable to its minimal expression using K_Map
6. Draw the corresponding logic circuit
Example 1
Design a synchronous Mod-6 UP counter using negative edge-triggered D-FFs provided with
active LOW PR and CLR.
Provide a mean to preset the counter to 3 at any instant of time.
Show whether the resulting counter is self-starting or not.
Solution
1. State diagram

2. Three D-FFs are required

3. Transition table.

Present States Next State Flip-Flop

P.S N.S Inputs
QA QB QC Q+A Q+B Q+C DA DB DC
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 0 0 0 0 0 0
1 1 0 x x x x x x
1 1 1 x x x x x x
QBQC
QA
0 0 1 0 0 1 0 1 1 0 0 1
1 0 x x 0 0 x x 1 0 x x
DA = Q BQC + Q A QC DB = Q A Q B QC + Q B QC DA = QC

2
6. The logic circuit
Q BQC + Q A QC DA Q QA

● ●

Q A Q B QC + Q B QC
DB Q QB
Provide a mean to preset the counter to 3 at any ●
instant of time.
At any instant of time means independent of the
clock, i.e., asynchronous mode.
3 = 011, we therefore use PR inputs of FF_B and
FF_C (to preset them to 1), and use CLR of FF_C QC DC Q QC
to reset it to 0.
●
When the PB is released, the counter is in the
synchronous mode (counting), when we depress
it, we assert the asynchronous inputs. Clk

Is the above counter self starting?

The above counter has 6 states out of 8. Now, what if the counter falls in either of the 2
forbidden states, that is, 6 or 7. If the counter joints the desired sequence, then the counter is said
to be self-starting or autonomous, otherwise it is not.
To determine whether the counter is self-starting or not, we construct a modified transition table
as follows
P.S FF Inputs N.S
QA QB QC DA DB DC Q+A Q+B Q+C
1 1 0 1 1 1 1 1 1
1 1 1 1 0 0 1 0 0
The table consists of 3 columns. The 1st column is made up of the 2 forbidden states 6 and 7.
To fill the 2nd column, we consider the way cells 6 and 7 have been mapped in the K_maps. In
the above design, cells 6 in then 3 K_maps were mapped as ‘1’s whereas cells 7 were mapped as
‘1’ in K_map of DA and ‘0’s for K_maps DB and DC.
Therefore, for P.S 6, D’s are 111, while for P.S 7, D’s are 100.
The 3rd column is obtained by using state table or state equation of the D-FF.
Q+ = D
We then draw the resulting state diagram of Figure 2. We notice that if the counter falls in state
7, it will join the desired sequence (count 4) after one clock cycle. Similarly, if it falls in state 6,
it will first go to state 7 then join the desired sequence (it will take 2 clock cycles). The counter is
thus autonomous or self starting.

Figure 2 Resulting state diagram

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Example 2 Design a synchronous UP/DN counter
Using positive edge-triggered JK-FFs, design a Mod-5 UP/DN counter.
Solution
1. State diagram

2. Three JK-FFs are required

3. Transition table

Mode Mode P.S N.S Flip-Flop Inputs

UD QA QB QC Q+A Q+B Q+C JA KA JB KB JC KC
0 0 0 0 0 0 1 0 x 0 x 1 x
0 0 0 1 0 1 0 0 x 1 x x 1
0 0 1 0 0 1 1 0 x x 0 1 x
UP 0 0 1 1 1 0 0 1 x x 1 x 1
0 1 0 0 0 0 0 x 1 0 x 0 x
0 1 0 1 x x x x x x x x x
0 1 1 0 x x x x x x x x x
0 1 1 1 x x x x x x x x x
1 0 0 0 1 0 0 1 x 0 x 0 x
1 0 0 1 0 0 0 0 x 0 x x 1
1 0 1 0 0 0 1 0 x x 1 1 x
DN 1 0 1 1 0 1 0 0 x x 0 x 1
1 1 0 0 0 1 1 x 1 1 x 1 x
1 1 0 1 x x x x x x x x x
1 1 1 0 x x x x x x x x x
1 1 1 1 x x x x x x x x x
4. K_Maps QBQC
UDQA
0 0 1 0
x x x x
x x x x
1 0 0 0

JA = UD Q B QC + UD Q B QC
Similarly, we obtain the remaining expressions
KA = 1 JC = Q B + UD Q A + UD Q A

JB= UD Q A + UD QC KC = 1

KB = UD QC + UD QC
Draw the corresponding logic circuit.

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Example 3 Irregular sequence
Using positive edge-triggered D-FFs, design a synchronous counter to cycle through the
following sequence.

Solution
This counter requires 3 FFs (largest count in the sequence is 7 = (111)2.
Transition table

Present State Next State Flip-Flop

P.S N.S Inputs
Q2 Q1 Q0 Q+2 Q+1 Q+0 D2 D1 D0
0 0 0 1 0 0 1 0 0
0 0 1 x x x x x x
0 1 0 0 1 1 0 1 1
0 1 1 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1
1 0 1 x x x x x x
1 1 0 x x x x x x
1 1 1 0 1 0 0 1 0
Simplifying, yields
D2 = Q1
D1 = Q 2 + Q1 Q0
D0 = Q 2 Q0 + Q1 Q0

Q1 D2 Q Q2

Q 2 + Q1 Q0 D1 Q Q1
●

Q 2 Q0 + Q1 Q0 D0 Q Q0
●

Clk

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Exercises
Using positive edge-triggered JK-FFs provided with active LOW asynchronous inputs PR and
CLR, design a synchronous sequential circuit that will cycle through the following sequence.
0, 2, 3, 5, 6, 7, 0, 2, …
Provide a mean to preset your counter to 5 at any instant of time
Check whether your counter is self-staring or not.