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Silicon carbide integrated circuits for extreme environments

Conference Paper · October 2013

DOI: 10.1109/WiPDA.2013.6695562

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 Silicon Carbide Integrated Circuits for Extreme
Environments
Avinash S. Kashyap, Cheng-Po Chen, Reza Ghandi, Kun Fang, Zhenzhen Shen
Amita Patil, Emad Andarawis, Liang Yin, Dave ECE Dept., Auburn University,
Shaddock, Peter Sandvik Auburn, AL, USA
General Electric Global Research Center Wayne Johnson
Niskayuna, NY, USA ECE Dept., Tennessee Tech University,
kashyap@ge.com Cookeville, TN, USA

Abstract— Analog and digital integrated circuits capable of physics of SiC lateral MOSFETs, creating compact device
operating reliably at 300 °C for 2000 hours were designed and models of the FETs, developing design tools (such as process
fabricated in silicon carbide. These circuits are critical for the design kits (PDKs)), designing analog and digital circuits
development of tools and instrumentation for geothermal using the developed models, creating new fabrication
exploration. Lateral MOSFETs and resistors were built on Si- processes for medium scale integration (MSI), advanced
face, 4°-off, N+ 4H-SiC substrates. Compact models of these ceramic packaging and high temperature testing. Each of the
devices were then generated and used to design the circuits, steps outlined above is challenging to implement due to the
including operational amplifiers, ring oscillators, counters, shift fact that most semiconductor processes and tools available
registers and logic gates. The circuits were then fabricated and
commercially are configured for silicon. They will be
packaged using specially developed high temperature packaging
processes. The integrated circuits were designed to interface
discussed in detail in the succeeding sections.
with sensors and transducers to produce analog signals that can
be digitized and transmitted via a telemetry system capable of
sustained operation at 300 °C.

I. INTRODUCTION
The material properties that make silicon carbide (SiC) an
attractive semiconductor for power devices is well known and
has been the focus of major research efforts all over the world
for over 15 years [1]. As this technology matures, SiC based
devices and circuits are increasingly gaining attention from
the extreme environment design community due to their
ability to operate reliably at temperatures over 300 °C. This
includes applications such as down-hole instrumentation,
aviation engine sensors & controls, gas turbine
Fig. 1. Geothermal wellbore monitoring system.
instrumentation and space exploration. While Silicon-on-
insulator (SOI) based circuits can be used at high
temperatures, their reliability may not be sufficient at the
temperature ranges focused in this effort [2]. In certain II. DEVICE PHYSICS AND MODELING
applications such as high impedance sensing circuits, the low A. Device Physics
leakage currents of SiC at elevated temperatures make them
SiC based ICs can be built using MOSFETs [3, 4], JFETs
more suitable than SOI devices, even at moderately high
[5, 6] or BJTs [7, 8]. JFETs are normally-on devices, while
temperatures such as 200 °C. BJTs are current-controlled and difficult to design circuits
with. BJTs also require a larger base current, making them
The overall objective of the program is to enable challenging to use for current-sensing applications. Due to
geothermal wellbore monitoring through the development of improved gate oxide quality [9], lateral MOSFETs (LFETs)
SiC based electronics and ceramic packaging capable of were preferred over other devices. Designing with SiC LFETs
operating reliably at 300 °C for at least 1000 hours (Fig.1). have challenges such as low mobility, negative temperature
Given that SiC integrated circuits (ICs) development is still coefficient of resistance, and the lack of mature p-MOS
nascent, this research effort involved understanding the

This material is based upon work supported by the Department of

Energy – Geothermal Technologies Program under Award DE-EE0002755.
devices that enable CMOS design. Therefore, novel all-nmos because the mobility of the SiC FET devices increase (due to
designs were implemented. greater number of traps being filled), and a higher current
drive is available to the op-amp at elevated temperatures.
B. Compact Modeling
Developing accurate circuit simulation models are the first
and among the most critical steps in realizing integrated
circuits. Developing new model equations for SiC FETs can
be expensive and time consuming. Moreover, some physical
aspects of the device such as relationship of surface density
states with temperature is still under investigation. The
industry standard PSP model for Si FETs was used to model
the SiC devices (transistors and resistors) by modifying the
parameter extraction methodology [10]. At the end of the iso-
thermal parameter extractions (at 25 °C and 300 °C), excellent
fits were observed between the measured data and model as
shown in Fig. 2. The models also exhibited good W/L scaling.
To account for process variations, best and worst case models
were also extracted in addition to the nominal models. These Fig. 3. SiC op-amp frequency response at room temperature and 300 °C.
models predict the device performance on wafers fabricated in High temperature performance of the op-amp is also shown at various time
different lots; and were then used to design the analog and intervals.
digital circuits described in the next section. The op-amps were used in an oscillator circuit that
converts a temperature sensor signal (resistance) to frequency,
and another circuit that converts a pressure sensor signal
(voltage) to frequency. These frequency output signals feed
into the digital telemetry circuit to be digitized and sent to the
well surface.
A few DIP packaged op-amps were tested at Sandia
National Labs and they were shown to be operational at
300 °C for over 2000 hours without failure. The drift of the
open-loop gain during the test can be seen in Fig. 4. Note that
an adjustment of the bias current was required at 1340 hours
to maintain proper biasing of the op-amps.

Fig. 2. PSP based transistor model vs. measured data for a 120u x 3u FET at
300 °C.
III. ANALOG AND DIGITAL CIRCUIT DESIGN

A. Analog – Operational Amplifier

One of the basic analog circuit building blocks designed in
this program was an operational amplifier (op-amp). The
design targets were as follows: (i) 60dB open loop gain, (ii)
20V supply voltage, and (iii) at least 1mA of output current Fig. 4. Open-loop gain at 300 °C for three op-amps during operational test
drive. Variations in design included using implanted resistors for 2000 hours performed at Sandia National Labs.
or diode connected FETs as amplifier loads, and cascading to B. Digital – Telemetry
increase the gain [11]. In general, using all-FET designs was The requirement for the telemetry circuit is to take the
found to be advantageous because the device parameters were frequency outputs from the two analog sensors, digitize and
found to drift in the same direction with temperature. This led then serialize them into a single bit stream. The building
towards a robust design capable of stable operation over a blocks for this circuit include counters, shift registers,
wide temperature range. The frequency response (open loop multiplexers, and buffers. The functions were divided into two
gain vs. frequency) of the op-amp at room temperature and at sections: (i) frequency counter, and (ii) timing generator. The
300 °C is shown in Fig. 3. The op-amp was packaged in a frequency counter converts the frequency input into a bit
ceramic dual inline package (DIP) and biased at normal stream, while the timing generator takes in a clock signal and
operating conditions at 300 °C for 1470 hours, without failure. generates the appropriate timing signals, such as load and reset
The bandwidth of the circuit increases with temperature for the frequency counter to operate. The frequency counter
and timing generator block diagrams are shown in Figs. 5 and IV. HIGH TEMPERATURE PACKAGING
6 respectively. Electronic packaging trials were conducted with alumina,
aluminum nitride (AlN), and low-temperature co-fired
ceramic (LTCC) substrates at 300°C. These materials were
chosen because electronic packages made with these
substrates have been shown to successfully operate at
temperatures of up to 500 °C [12]. Gold in the form of thick
or thin-film was used as the metallization. To enable digital
circuits with higher density inputs/outputs, a flip-chip die
attach process with thin film metal on AlN substrate was
chosen. It was possible to develop fine feature sizes with the
Fig. 5. Digital frequency counter block diagram. thin film process. The AlN substrate was the material of
choice due to its coefficient of thermal expansion
(4.5ppm/°C) being closely matched to that of SiC (4.3
ppm/°C). The flip-chip die attach involves gold wire stud
bumping on the SiC die, aligning it to the AlN substrate, and
then using a thermo-compression bonding process at elevated
temperatures (Fig. 8). Details of the packaging materials and
process were reported previously [13, 14].

Fig. 6. Digital timing generator block diagram.

An optical micrograph of the timing generator is shown in

Fig. 7. There are two 4-bit counters and a sequential logic
section that generates the reset and load signals to be used in
the frequency counter. The timing generator circuit integrates
over 380 SiC transistors on one die – one of the highest
known integration levels for SiC ICs.

Fig.. 8. Assembled timing generator on AlN substrate.

V. RELIABILITY
The long term stability of the frequency counter at 300 °C,
subjected to random vibrations at 20 G RMS level and
mechanical shock at 215 G level was reported previously
[15]. These boards successfully demonstrated full operation
after more than 1000 hours of stress at 300 °C, and also
survived 8 hours of vibration and 1000 shocks at the same
temperature.
The timing generator board successfully remained
operational for 2000 hours at 300 °C with no degradation. In
Fig. 9, CLK is the input clock signal from a function
generator, and R4 is the circuit output from the counter
frequency divider. It divides the CLK frequency by 32. The
telemetry module samples the frequency count from the
Fig..7. Optical micrograph of the timing generator die (6mm x 6mm). counter as per the “Load” signal. “Select” is an output signal
that toggles between two analog sensor channels. The board
output after 2000 hours of stress is seen in Fig.10, with no REFERENCES
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