Unit 4

1
www.studymaterialz.in
UNIT - 4
ELECTRONIC CIRCUITS
Department : Electronics and Communication Engineering

Batch/Year : 2020-2024
Created by :Mrs.J JASMINE HEPHZIPAH
, Ms. Rosaline, Dr.B.Sarala, Mr. Sivakumar,
Ms.A.Iyswariya, Mr.Sathya Vignesh
Date : 01.10.2020
Table of Contents
Electrical Circuit analysis

• PN junction
• VI characteristics of diode
• Zener diode
• Transistor Op-amps
• Op-amp configurations
• Rectifiers
• Differentiator
• Integrator
• Nodal Analysis
• ADC-Types
• Successive appromixation type
• DAC- types
• Weighted Resistor
• R-2R ladder type.
• Voltage regulator IC using LM 723
• Voltage regulator IC using LM 317
2
BE8255 BASIC ELECTRICAL, ELECTRONICS AND MEASUREMENT
ENGINEERING
Unit 4: ELECTRONIC CIRCUITS
4.1 PN JUNCTION DIODE

INTRODUCTON
Based on the electrical conductivity all the materials in nature are classified as
insulators, semiconductors, and conductors.
Insulator: An insulator is a material that offers a very low level (or negligible) of
conductivity when voltage is applied. Eg: Paper, Mica, glass, quartz. Typical
resistivity level of an insulator is of the order of 1010 to 1012 Ω-cm. The energy
band structure of an insulator is shown in the fig.1.1. Band structure of a material
defines the band of energy levels that an electron can occupy. Valance band is the
range of electron energy where the electron remain bended too the atom and do
not contribute to the electric current. Conduction bend is the range of electron
energies higher than valance band where electrons are free to accelerate under
the influence of external voltage source resulting in the flow of charge.
The energy band between the valance band and conduction band is called as
forbidden band
gap. It is the energy required by an electron to move from balance band to
conduction band i.e. the energy required for a valance electron to become a free
electron.
1 eV = 1.6 x 10-19 J
For an insulator, as shown in the fig.1.1 there is a large forbidden band gap of
greater than 5Ev. Because of this large gap there a very few electrons in the CB
and hence the conductivity of insulator is
poor. Even an increase in temperature or applied electric field is insufficient to
transfer electrons from VB to CB.
CB
CB
Forbidden band gap Eo ≈6eV Eo =≈6eV
VB
VB
Fig 4.1 Fig 4.2
CB
VB
Fig 4.3
Conductors:A conductorisa material which supports a generousflowof charge

when a voltageisapplied across its terminals.i.e.ithas very high conductivity.
Eg: Copper, Aluminum, Silver, Gold. The resistivityofa conductorisinthe order
of 10-4and 10-6Ω-cm. The Valance and conduction bands overlap (fig1.1) and
thereisno energy gap for the electronstomovefrom valance bandtoconduction
band. This implies that there are free electronsinCB even at absolute zero
temperature (0K). Thereforeatroom temperature when electricfield isapplied
large current flows through the conductor.
Semiconductor: A semiconductor is a material that has its conductivity
somewhere between the insulator and conductor. The resistivity level is in
the range of 10 and 104 Ω-cm. Two of the most commonly used are Silicon
(Si=14 atomic no.) and germanium (Ge=32 atomic no.). Both have 4 valance
electrons. The forbidden band gap is in the order of 1eV. For eg., the band
gap energy for Si, Ge and GaAs is 1.21, 0.785 and 1.42 eV, respectively at
absolute zero temperature (0K). At 0K and at low temperatures, the valance
band electrons do not have sufficient energy to move from V to CB. Thus
semiconductors act a insulators at 0K. as the temperature increases, a large
number of valance electrons acquire sufficient energy to leave the VB, cross
the forbidden bandgap and reach CB. These are now free electrons as they
can move freely under the influence of electric field. At room temperature
there are sufficient electrons in the CB and hence the semiconductor is
capable of conducting some current at room temperature.
Inversely related to the conductivity of a material is its resistance to the flow
of charge or current. Typical resistivity values for various materials’ are
given as follows.
4.1.1 Semiconductor Types
A pure form of semiconductors is called as intrinsic semiconductor.

Conduction in intrinsic sc is either due to thermal excitation or crystal defects.
Si and Ge are the two most important semiconductors used. Other examples
include Gallium arsenide GaAs, Indium Antimonide (InSb) etc.
Let us consider the structure of Si. A Si atomic no. is 14 and it has 4 valance
electrons. These 4 electrons are shared by four neighboring atoms in the
crystal structure by means of covalent bond. Fig. 1.2a shows the crystal
structure of Si at absolute zero temperature (0K). Hence a pure SC acts has
poor conductivity (due to lack of free electrons) at low or absolute zero
temperature.
Covalent bond
Valence electron
Fig
Fig. 4.4
1.2a crystal structure of Si at 0K
At room temperature some of the covalent bonds break up to thermal energy
as shown in fig 1.2b. The valance electrons that jump into conduction band are
called as free electrons that are available for conduction.
Free electron
Valance electron
hole
Fig. 1.2b crystal structure of Si at room

temperature0K
Fig 4.5
The absence of electrons in covalent bond is represented by a small circle

usually referred to as hole which is of positive charge. Even a hole serves as
carrier of electricity in a manner similar to that of free electron.
The mechanism by which a hole contributes to conductivity is explained as

follows:
When a bond is in complete so that a hole exists, it is relatively easy for a
valance electron in the neighboring atom to leave its covalent bond to fill this
hole. An electron moving from a bond to fill a hole moves in a direction
opposite to that of the electron. This hole, in its new position may now be
filled by an electron from another covalent bond and the hole will
correspondingly move one more step in the direction opposite to the motion
of electron. Here we have a mechanism for conduction of electricity which
does not involve free electrons. This phenomenon is illustrated in fig1.3
Electron movement
Hole movement
Fig 4.6
Fig. 1.3b
Fig 4.7 Fig 4.8

Fig 1.3a show that there is a hole at ion 6.Imagine that an electron from ion
5 moves into the hole at ion 6 so that the configuration of 1.3b results. If
we compare both fig1.3a &fig 1.3b, it appears as if the hole has moved
towards the left from ion6 to ion 5. Further if we compare fig 1.3b and fig
1.3c, the hole moves from ion5 to ion 4. This discussion indicates the
motion of hole is in a direction opposite to that of motion of electron.
Hence we consider holes as physical entities whose movement constitutes
flow of current.
In a pure semiconductor, the number of holes is equal to the number of
free electrons.
4.1.2 EXTRINSIC SEMICONDUCTOR

Intrinsic semiconductor has very limited applications as they conduct very
small amounts of current at room temperature. The current conduction
capability of intrinsic semiconductor can be increased significantly by
adding a small amounts impurity to the intrinsic semiconductor. By adding
impurities it becomes impure or extrinsic semiconductor. This process of
adding impurities is called as doping. The amount of impurity added is 1
part in 106 atoms.
N type semiconductor: If the added impurity is a pentavalent atom then the

resultant semiconductor is called N-type semiconductor. Examples of pentavalent
impurities are Phosphorus, Arsenic, Bismuth, Antimony etc.
A pentavalent impurity has five valance electrons. Fig 1.4a shows the crystal
structure of N-type semiconductor material where four out of five valance
electrons of the impurity atom(antimony) forms covalent bond with the four
intrinsic semiconductor atoms. The fifth electron is loosely bound to the impurity
atom. This loosely bound electron can be easily
Fifth valance electron of SB
Ec CB
Ed
Donor energy level
Ev
VB
Fig 4.10
Fig Fig.
4.9 1.4a crystal structure of N type SC
Excited from the valance band to the conduction band by the application of
electric field or increasing the thermal energy. The energy required to
detach the fifth electron form the impurity atom is very small of the order
of 0.01ev for Ge and 0.05 eV for Si.
The effect of doping creates a discrete energy level called donor energy
level in the forbidden band gap with energy level Ed slightly less than the
conduction band (fig 1.4b). The difference between the energy levels of
the conducting band and the donor energy level is the energy required to
free the fifth valance electron (0.01 eV for Ge and 0.05 eV for Si). At room
temperature almost all the fifth electrons from the donor impurity atom
are raised to conduction band and hence the number of electrons in the
conduction band increases significantly. Thus every antimony atom
contributes to one conduction electron without creating a hole.
In the N-type sc the no. of electrons increases and the no. of holes
decreases compared to those available in an intrinsic sc. The reason for
decrease in the no. of holes is that the larger no. of electrons present
increases the recombination of electrons with holes. Thus current in N type
sc is dominated by electrons which are referred to as majority carriers.
Holes are the minority carriers in N type sc
P type semiconductor: If the added impurity is a trivalent atom then the
resultant semiconductor is called P-type semiconductor. Examples of
trivalent impurities are Boron, Gallium , indium etc.
The crystal structure of p type sc is shown in the fig1.5a. The three valance
electrons of the impurity (boon) forms three covalent bonds with the
neighboring atoms and a vacancy exists in the fourth bond giving rise to
the holes. The hole is ready to accept an electron from the neighboring
atoms. Each trivalent atom contributes to one hole generation and thus
introduces a large no. of holes in the valance band. At the same time the
no. electrons are decreased compared to those available in intrinsic sc
because of increased recombination due to creation of additional holes.
hole
Fig 4.11
Fig. 1.5a crystal structure of P type sc
Thus in P type sc , holes are majority carriers and electrons are minority
carriers. Since each trivalent impurity atoms are capable accepting an
electron, these are called as acceptor atoms. The following fig 1.5b shows
the pictorial representation of P type sc
hole (majority carrier)
Electron (minority carrier)
Acceptor atoms
Fig. 1.5b crystal structure of P type sc

Fig 4.12
The conductivity of N type sc is greater than that of P type sc as the
mobility of electron is greater than that of hole.
For the same level of doping in N type sc and P type sc, the conductivity
of an Ntype sc is around twice that of a P type sc
4.1.3 CONDUCTIVITY OF SEMICONDUCTOR

In a pure sc, the no. of holesCONDUCTIVITY OF SEMICONDUCTOR
In a pure sc, the no. of holes is equal to the no. of electrons. Thermal agitation
continue to produce new electron- hole pairs and the electron hole pairs
disappear because of recombination. with each electron hole pair created , two
charge carrying particles are formed . One is negative which is a free electron
with mobility µn . The other is a positive i.e., hole with mobility µp . The electrons
and hole move in opppsitte direction in a an electric field E, but since they are
of opposite sign, the current due to each is in the same direction. Hence the
total current density J within the intrinsic sc is given by
J = Jn + Jp
=q n µn E + q p µp E
= (n µn + p µp)qE
=ς E
Where n=no. of electrons / unit volume i.e., concentration of is equal to the no.
of electrons. Thermal agitation continue to produce new electron- hole pairs
and the electron hole pairs disappear because of recombination. with each
electron hole pair created , two charge carrying particles are formed . One is
negative which is a free electron with mobility µn . The other is a positive i.e.,
hole with mobility µp . The electrons and hole move in opppsitte direction in a
an electric field E, but since they are of opposite sign, the current due to each is
in the same direction. Hence the total current density J within the intrinsic sc is
given by
J = Jn + Jp
=q n µn E + q p µp E
= (n µn + p µp)qE
=ς E
Where n=no. of electrons / unit volume i.e., concentration of free
electrons P= no. of holes / unit volume i.e., concentration of holes
E=applied electric field strength, V/m
q= charge of electron or hole I n Coulombs
Hence, ς is the conductivity of sc which is equal to (n µn + p µp)q. he resistivity

of sc is reciprocal of conductivity.
Ρ = 1/ ς
It is evident from the above equation that current density with in a sc is
directly proportional to applied electric field E.
For pure sc, n=p= ni where ni = intrinsic concentration. The value of ni is given
by n 2=AT3 exp (-E /KT)
i GO
therefore, J= ni ( µn + µp) q E
Hence conductivity in intrinsic sc is ςi= ni ( µn + µp) q
Intrinsic conductivity increases at the rate of 5% per o C for Ge and 7% per o C

for Si.
Conductivity in extrinsic sc (N Type and P Type):
The conductivity of intrinsic sc is given by ςi= ni ( µn + µp) q = (n µn + p µp)q
For N type , n>>p
Therefore ς= q n µn For P type ,p>>n
Therefore ς= q p µp
4.1.4 CHARGE DENSITIES IN P TYPE AND N TYPE SEMICONDUCTOR:
Mass Action Law:

Under thermal equilibrium for any semiconductor, the product of the no. of holes and
the concentration of electrons is constant and is independent of amount of donor and
acceptor impurity doping.
n.p= n 2
i
where n= eleetron concentration p = hole concentration
n 2= intrinsic concentration
i
Hence in N type sc , as the no. of electrons increase the no. of holes decreases.
Similarly in P type as the no. of holes increases the no. of electrons decreases.
Thus the product is constant and is
2
equal to ni in case of intrinsic as well as extrinsic sc.
The law of mass action has given the relationship between free electrons
concentration and hole concentration. These concentrations are further related by
the law of electrical neutrality as explained below.
Law of electrical neutrality:

Sc materials are electrically neutral. According to the law of electrical neutrality, in
an electrically neutral material, the magnitude of positive charge concentration is
equal to tat of negative charge concentration. Let us consider a sc that has ND donor
atoms per cubic centimeter and NA acceptor atoms per cubic centimeter i.e., the
concentration of donor and acceptor atoms are ND and NA respectively.
Therefore ND positively charged ions per cubic centimeter are contributed

by donor atoms and NA negatively charged ions per cubic centimeter are
contributed by the acceptor atoms. Let n, p is concentration of free
electrons and holes respectively. Then according to the law of neutrality
ND + p =NA + n …………………………………eq1.1
For N type sc, NA =0 and n>>p. Therefore ND ≈ n

………………………………….eq1.2
Hence for N type sc the free electron concentration is approximately equal
to the concentration of donor atoms. In later applications since some
confusion may arise as to which type of sc is under consideration a the
given moment, the subscript n or p is added for Ntype or P type
respectively. Hence eq1.2 becomes ND ≈ nn
Therefore current density in N type sc is J = ND µn q E And conductivity ς=
ND µn q
For P type sc, ND = 0 and p>>n. Therefore NA ≈ p
Or NA ≈ pp
Hence for P type sc the hole concentration is approximately equal to the
concentration of acceptor atoms.
Therefore current density in N type sc is J = NA µp q E And conductivity ς=
NA µp q
Mass action law for N type, nn pn= n 2
i
pn= n 2/ N since (n ≈ N )
i D n D
Mass action law for P type, np pp= ni
2
np= ni / NA since (pp≈ NA)
4.1.5 QUANTITATIVE THEORY OF PN JUNCTION DIODE
PN JUNCTION WITH NO APPLIED VOLTAGE OR OPEN CIRCUIT

CONDITION:
In a piece of sc, if one half is doped by p type impurity and the other half is
doped by n type impurity, a PN junction is formed. The plane dividing the
two halves or zones is called PN junction. As shown in the fig the n type
material has high concentration of free electrons, while p type material
has high concentration of holes. Therefore at the junction there is a
tendency of free electrons to diffuse over to the P side and the holes to
the N side. This process is called diffusion. As the free electrons move
across the junction from N type to P type, the donor atoms become
positively charged. Hence a positive charge is built on the N-side of the
junction. The free electrons that cross the junction uncover the negative
acceptor ions by filing the holes. Therefore a negative charge is developed
on the p –side of the junction..This net negative charge on the p side
prevents further diffusion of electrons into the p side. Similarly the net
positive charge on the N side repels the hole crossing from p side to N
side. Thus a barrier sis set up near the junction which prevents the further
movement of charge carriers i.e. electrons and holes. As a consequence of
induced electric field across the depletion layer, an electrostatic potential
difference is established between P and N regions, which are called the
potential barrier, junction barrier, diffusion potential or contact potential,
Vo. The magnitude of the contact potential Vo varies with doping levels
and temperature. Vo is 0.3V for Ge and 0.72 V for Si.
Fig 4.13: Symbol of PN Junction Diode

The electrostatic field across the junction caused by the positively charged N-
Type region tends to drive the holes away from the junction and negatively
charged p type regions tend to drive the electrons away from the junction. The
majority holes diffusing out of the P region leave behind negatively charged
acceptor atoms bound to the lattice, thus exposing a negatives pace charge in a
previously neutral region. Similarly electrons diffusing from the N region expose
positively ionized donor atoms and a double space charge builds up at the
junction as shown in the fig.
Fig 4.14
It is noticed that the space charge layers are of opposite sign to the majority
carriers diffusing into them, which tends to reduce the diffusion rate. Thus
the double space of the layer causes an electric field to be set up across the
junction directed from N to P regions, which is in such a direction to inhibit
the diffusion of majority electrons and holes as illustrated in fig 1.7b. The
shape of the charge density, ρ, depends upon how diode id doped. Thus
the junction region is depleted of mobile charge carriers. Hence it is called
depletion layer, space region, and transition region. The depletion region is of
the order of 0.5µm thick. There are no mobile carriers in this narrow
depletion region. Hence no current flows across the junction and the system
is in equilibrium. To the left of this depletion layer, the carrier concentration is
p= NA and to its right it is n= ND.
Fig 4.15
4.1.6 FORWARD BIASED JUNCTION DIODE
When a diode is connected in a Forward Bias condition, a negative voltage is

applied to the N- type material and a positive voltage is applied to the P-type
material. If this external voltage becomes greater than the value of the potential
barrier, approx. 0.7 volts for silicon and 0.3 volts for germanium, the potential
barriers opposition will be overcome and current will start to flow. This is because
the negative voltage pushes or repels electrons towards the junction giving them
the energy to cross over and combine with the holes being pushed in the
opposite direction towards the junction by the positive voltage. This results in a
characteristics curve of zero current flowing up to this voltage point,
called the "knee" on the static curves and then a high current flow through the
diode with little increase in the external voltage as shown below.
Forward Characteristics Curve for a Junction Diode
Fig 4.16
Fig 1.8a: Diode Forward Characteristics
The application of a forward biasing voltage on the junction diode results in the
depletion layer becoming very thin and narrow which represents a low
impedance path through the junction thereby allowing high currents to flow. The
point at which this sudden increase in current takes place is represented on the
static I-V characteristics curve above as the "knee" point.
Forward Biased Junction Diode showing a Reduction in the Depletion Layer
Fig 4.17: Diode Forward Bias
This condition represents the low resistance path through the PN junction allowing
very large currents to flow through the diode with only a small increase in bias
voltage. The actual potential difference across the junction or diode is kept
constant by the action of the depletion layer at approximately 0.3v for germanium
and approximately 0.7v for silicon junction diodes. Since the diode can conduct
"infinite" current above this knee point as it effectively becomes a short circuit,
therefore resistors are used in series with the diode to limit its current flow.
Exceeding its maximum forward current specification causes the device to
dissipate more power in the form of heat than it was designed for resulting in a
very quick failure of the device.
4.1.7 PN JUNCTION UNDER REVERSE BIAS CONDITION:
Reverse Biased Junction Diode
When a diode is connected in a Reverse Bias condition, a positive voltage is applied

to the N-type material and a negative voltage is applied to the P-type material. The
positive voltage applied to the N- type material attracts electrons towards the
positive electrode and away from the junction, while the holes in the P-type end
are also attracted away from the junction towards the negative electrode. The net
result is that the depletion layer grows wider due to a lack of electrons and holes
and presents a high impedance path, almost an insulator. The result is that a high
potential barrier is created thus preventing current from flowing through the
semiconductor material.
Fig 4.18: Diode Reverse Bias
This condition represents a high resistance value to the PN junction and

practically zero current flows through the junction diode with an increase in
bias voltage. However, a very small leakage current does flow through the
junction which can be measured in microamperes, (μA). One final point, if the
reverse bias voltage Vr applied to the diode is increased to a sufficiently high
enough value, it will
cause the PN junction to overheat and fail due to the avalanche effect
around the junction. This may cause the diode to become shorted and
will result in the flow of maximum circuit current, and this shown as a
step downward slope in the reverse static characteristics curve below.
Reverse Characteristics Curve for a Junction Diode
Fig 4.19: Diode Reverse Characteristics
Sometimes this avalanche effect has practical applications in voltage stabilizing

circuits where a series limiting resistor is used with the diode to limit this reverse
breakdown current to a preset maximum value thereby producing a fixed voltage
output across the diode. These types of diodes are commonly known as Zener
Diodes
4.1.8 VI CHARACTERISTICS AND THEIR TEMPERATURE DEPENDENCE

Diode terminal characteristics equation for diode junction current:
v
I  I ( e vT  1 )
D 0
Where VT = KT/q;
VD_ diode terminal voltage, Volts
Io _ temperature-dependent saturation current, µA T _ absolute temperature of p-n
junction, K
K _ Boltzmann’s constant 1.38x 10 -23J/K) q _ electron charge 1.6x10-19 C
 = empirical constant, 1 for Ge and 2 for Si
Fig 4.20 Diode Characteristics

4.1.8 Temperature Effects on Diode

Temperature can have a marked effect on the characteristics of a silicon
semiconductor diode as shown in Fig. 11 It has been found experimentally that
the reverse saturation current Io will just
about double in magnitude for every 10°C increase in temperature.
Fig 4.21 Variation in Diode Characteristics with temperature

change
4.1.8 Temperature Effects on Diode

Temperature can have a marked effect on the characteristics of a silicon
semiconductor diode as shown in Fig. 11 It has been found experimentally that
the reverse saturation current Io will just
about double in magnitude for every 10°C increase in temperature.
Fig 4.21 Variation in Diode Characteristics with temperature

change
It is not uncommon for a germanium diode with an Io in the order of 1 or 2 A at
25°C to have a leakage current of 100 A - 0.1 mA at a temperature of 100°C.
Typical values of Io for silicon are much lower than that of germanium for similar
power and current levels. The result is that even at high temperatures the levels
of Io for silicon diodes do not reach the same high levels obtained. For
germanium—a very important reason that silicon devices enjoy a significantly
higher level of development and utilization in design. Fundamentally, the open-
circuit equivalent in the reverse bias region is better realized at any temperature
with silicon than with germanium. The increasing levels of Io with temperature
account for the lower levels of threshold voltage, as shown in Fig. 1.11. Simply
increase the level of Io in and not rise in diode current. Of course, the level of TK
also will be increase, but the increasing level of Io will overpower the smaller
percent change in TK. As the temperature increases the forward characteristics
are actually becoming more “ideal,”
4.1.8 IDEAL VERSUS PRACTICAL RESISTANCE LEVELS
DC or Static Resistance
The application of a dc voltage to a circuit containing a semiconductor diode will
result in an
operating point on the characteristic curve that will not change with time. The
resistance of the diode at the operating point can be found simply by finding the
corresponding levels of VD and ID as shown in Fig. 1.12 and applying the following
Equation:
The dc resistance levels at the knee and below will be greater than the
resistance levels obtained for the vertical rise section of the characteristics.
The resistance levels in the reverse-bias region will naturally be quite high.
Since ohmmeters typically employ a relatively constant-current source, the
resistance determined will be at a preset current level (typically, a few mill
amperes).
Fig 4.22 Determining the dc resistance of a diode at a particular operating

point.
AC or Dynamic Resistance
It is obvious from Eq. 1.3 that the dc resistance of a diode is independent of
the shape of the characteristic in the region surrounding the point of interest.
If a sinusoidal rather than dc input is applied, the situation will change
completely. The varying input will move the instantaneous operating point up
and down a region of the characteristics and thus defines a specific change in
current and voltage as shown in Fig. 1.13. With no applied varying signal, the
point of operation would be the Q- point appearing on Fig. 1.13 determined
by the applied dc levels. The designation Q-point is derived from the word
quiescent, which means “still or unvarying.” A straight-line drawn tangent to
the curve through the Q-point as shown in Fig. 1.13 will define a particular
change in voltage and current that can be used to determine the ac or
dynamic resistance for this region of the diode characteristics. In
equation form,
Fig 4.23: Determining the ac resistance of a diode at a particular operating

point.
DIODE EQUIVALENT CIRCUITS

An equivalent circuit is a combination of elements properly chosen to best
represent the actual terminal characteristics of a device, system, or such in a
particular operating region. In other words, once the equivalent circuit is
defined, the device symbol can be removed from a schematic and the equivalent
circuit inserted in its place without severely affecting the actual behavior of the
system. The result is often a network that can be solved using traditional circuit
analysis techniques.
Piecewise-Linear Equivalent Circuit

One technique for obtaining an equivalent circuit for a diode is to
approximate the characteristics of the device by straight-line segments, as
shown in Fig. 1.31. The resulting equivalent
circuit is naturally called the piecewise-linear equivalent circuit. It should be
obvious from Fig. 1.31 that the straight-line segments do not result in an
exact duplication of the actual characteristics, especially in the knee
region. However, the resulting segments are sufficiently close to the actual
curve to establish an equivalent circuit that will provide an excellent first
approximation to the actual behaviour of the device. The ideal diode is
included to establish that there is only one direction of conduction through
the device, and a reverse-bias condition will result in the open- circuit state
for the device. Since a silicon semiconductor, diode does not reach the
conduction state until VD reaches 0.7 V with a forward bias (as shown in
Fig. 1.14a), a battery VT opposing the conduction direction must appear in
the equivalent circuit as shown in Fig. 1.14b. The battery simply specifies
that the voltage across the device must be greater than the threshold
battery voltage before conduction through the device in the direction
dictated by the ideal diode can be established. When conduction is
established, the resistance of the diode will be the specified value of rav.
Fig: 4.24 Diode piecewise-linear model characteristics

Fig 4.25
Fig: 1.14b Diode piecewise-linear model equivalent circuit
The approximate level of rav can usually be determined from a specified
operating point on the specification sheet. For instance, for a silicon
semiconductor diode, if IF _ 10 mA (a forward conduction
current for the diode) at VD _ 0.8 V, we know for silicon that a shift of 0.7 V is
required before the characteristics rise.
Fig 4.26 Ideal Diode and its characteristics

Fig 4.27 Diode equivalent circuits(models)

4.1.9 TRANSITION AND DIFFUSION CAPACITANCE
Electronic devices are inherently sensitive to very high frequencies. Most
shunt capacitive effects that can be ignored at lower frequencies because the
reactance XC=1/2πfC is very large (open- circuit equivalent). This, however,
cannot be ignored at very high frequencies. XC will become sufficiently small
due to the high value of f to introduce a low-reactance “shorting” path. In
the p-n semiconductor diode, there are two capacitive effects to be
considered. In the reverse-bias region we have the transition- or depletion
region capacitance (CT), while in the forward-bias region we have the
diffusion (CD) or storage capacitance. Recall that the basic equation for the
capacitance of a parallel- plate capacitor is defined by C=€A/d, where € is the
permittivity of the dielectric (insulator) between the plates of area A
separated by a distance d. In the reverse-, bias region there is a depletion
region (free of carriers) that behaves essentially like an insulator between the
layers of opposite charge. Since the depletion width (d) will increase with
increased reverse-bias potential, the resulting transition capacitance will
decrease. The fact that the capacitance is dependent on the applied reverse-
bias potential has application in a number of electronic systems. Although the
effect described above will also be present in the forward-bias region, it is
over shadowed by a capacitance effect directly dependent on the rate at
which charge is injected into the regions just outside the depletion region.
The capacitive effects described above are represented by a capacitor in
parallel with the ideal diode, as shown in Fig. 1.38. For low- or mid-frequency
applications (except in the power area), however, the capacitor is normally
not included in the diode symbol.
Fig 4.28: Including the effect of the transition or diffusion capacitance on the
semiconductor diode
Diode capacitances: The diode exhibits two types of capacitances transition

capacitance and diffusion capacitance.
Transition capacitance: The capacitance which appears between positive ion layer
in n-region and negative ion layer in p-region.
Diffusion capacitance: This capacitance originates due to diffusion of charge carriers
in the
opposite regions.
The transition capacitance is very small as compared to the diffusion capacitance.
In reverse bias transition, the capacitance is the dominant and is given by:
where CT - transition capacitance A

- diode cross sectional area
W - depletion region width
In forward bias, the diffusion capacitance is the dominant and
is given by:
where CD - diffusion capacitance

dQ - change in charge stored in depletion region V - change in applied
voltage
- time interval for change in voltage g - diode conductance
r - diode resistance
The diffusion capacitance at low frequencies is given by the formula:
where CD - diffusion capacitance

dQ - change in charge stored in depletion region V - change in applied
voltage
- time interval for change in voltage g - diode conductance
r - diode resistance
The diffusion capacitance at low frequencies is given by the formula:
Note: The variation of diffusion capacitance with applied voltage is used in the
design of varactor.
4.1.10 BREAK DOWN MECHANISMS
When an ordinary P-N junction diode is reverse biased, normally only very small
reverse saturation current flows. This current is due to movement of minority
carriers. It is almost independent of the voltage applied. However, if the reverse
bias is increased, a point is reached when the junction breaks down and the
reverse current increases abruptly. This current could be large enough to destroy
the junction. If the reverse current is limited by means of a suitable series
resistor, the power dissipation at the junction will not be excessive, and the
device may be operated continuously in its
breakdown region to its normal (reverse saturation) level. It is found that for a
suitably designed diode, the breakdown voltage is very stable over a wide range of
reverse currents. This quality gives the breakdown diode many useful applications
as a voltage reference source.
The critical value of the voltage, at which the breakdown of a P-N junction diode
occurs, is called the breakdown voltage. The breakdown voltage depends on the
width of the depletion region, which, in turn, depends on the doping level. The
junction offers almost zero resistance at the breakdown point.
There are two mechanisms by which breakdown can occur at a reverse biased P-N
junction:
avalanche breakdown and

Zener breakdown.
Avalanche breakdown
The minority carriers, under reverse biased conditions, flowing through the
junction acquire a kinetic energy which increases with the increase in reverse
voltage. At a sufficiently high reverse voltage (say 5 V or more), the kinetic energy
of minority carriers becomes so large that they knock out electrons from the
covalent bonds of the semiconductor material. As a result of collision, the liberated
electrons in turn liberate more electrons and the current becomes very large
leading to the breakdown of the crystal structure itself. This phenomenon is called
the avalanche breakdown. The breakdown region is the knee of the characteristic
curve. Now the current is not controlled by the junction voltage but rather by the
external circuit.
Zener breakdown
Under a very high reverse voltage, the depletion region expands and the potential
barrier increases leading to a very high electric field across the junction. The
electric field will break some of the covalent bonds of the semiconductor atoms
leading to a large number of free minority carriers, which suddenly increase the
reverse current. This is called the Zener effect. The breakdown occurs at a
particular and constant value of reverse voltage called the breakdown voltage, it is
found that Zener breakdown occurs at electric field intensity of about 3 x 107 V/m.
Fig 4.29: Diode characteristics with breakdown

Either of the two (Zener breakdown or avalanche breakdown) may occur

independently, or both of these may occur simultaneously. Diode junctions that
breakdown below 5 V are caused by Zener effect. Junctions that experience
breakdown above 5 V are caused by avalanche effect. Junctions that breakdown
around 5 V are usually caused by combination of two effects. The Zener
breakdown occurs in heavily doped junctions (P-type semiconductor moderately
doped and N-type heavily doped), which produce narrow depletion layers. The
avalanche breakdown occurs in lightly doped junctions, which produce wide
depletion layers. With the increase in junction temperature Zener breakdown
voltage is reduced while the avalanche breakdown voltage increases. The Zener
diodes have a negative temperature coefficient while avalanche diodes have a
positive temperature coefficient. Diodes that have breakdown voltages around 5
V have zero temperature coefficient. The breakdown phenomenon is reversible
and harmless so long as the safe operating temperature is maintained.
4.2 ZENER DIODES
The Zener diode is like a general-purpose signal diode consisting of a silicon PN

junction. When biased in the forward direction it behaves just like a normal signal
diode passing the rated current, but as soon as a reverse voltage applied across
the zener diode exceeds the rated voltage of the device, the diodes breakdown
voltage VB is reached at which point a process called Avalanche Breakdown occurs
in the semiconductor depletion layer and a current starts to flow through the
diode to limit this increase in voltage.
The current now flowing through the zener diode increases dramatically to the
maximum circuit value (which is usually limited by a series resistor) and once
achieved this reverse saturation current remains fairly constant over a wide range
of applied voltages. This breakdown voltage point, VB is called the "zener voltage"
for zener diodes and can range from less than one volt to hundreds of volts.
The point at which the zener voltage triggers the current to flow through the
diode can be very accurately controlled (to less than 1% tolerance) in the
doping stage of the diodes semiconductor construction giving the diode a
specific zener breakdown voltage, (Vz) for example, 4.3V or 7.5V. This zener
breakdown voltage on the I-V curve is almost a vertical straight line.
4.2.1 Zener Diode I-V Characteristics
Fig 4.30 : Zener diode characteristics

The Zener Diode is used in its "reverse bias" or reverse breakdown mode, i.e. the
diodes anode connects to the negative supply. From the I-V characteristics curve
above, we can see that the zener diode has a region in its reverse bias
characteristics of almost a constant negative voltage regardless of the value of
the current flowing through the diode and remains nearly constant even with
large changes in current as long as the zener diodes current remains between
the breakdown current IZ(min) and the maximum current rating IZ(max).
This ability to control itself can be used to great effect to regulate or stabilize a
voltage source against supply or load variations. The fact that the voltage across
the diode in the breakdown region is almost constant turns out to be an
important application of the zener diode as a voltage regulator. The function of
a regulator is to provide a constant output voltage to a load connected in parallel
with it in spite of the ripples in the supply voltage or the variation in the load
current and the zener diode will
continue to regulate the voltage until the diodes current falls below the
minimum IZ(min) value in the reverse breakdown region.
4.3 CONSTRUCTION OF BJT AND ITS SYMBOLS

The Bipolar Transistor basic construction consists of two PN-junctions
producing three connecting terminals with each terminal being given a name
to identify it from the other two. These three terminals are known and
labelled as the Emitter ( E ), the Base ( B ) and the Collector ( C ) respectively.
There are two basic types of bipolar transistor construction, PNP and NPN,
which basically describes the physical arrangement of the P-type and N-type
semiconductor materials from which they are made.
Transistors are three terminal active devices made from different

semiconductor materials that can act as either an insulator or a conductor by
the application of a small signal voltage. The transistor's ability to change
between these two states enables it to have two basic functions: "switching"
(digital electronics) or "amplification" (analogue electronics). Then bipolar
transistors have the ability to operate within three different regions:
1.Active Region - the transistor operates as an amplifier and Ic = β.Ib

2.Saturation - the transistor is "fully-ON" operating as a switch and Ic =
I(saturation)
3.Cut-off - the transistor is "fully-OFF" operating as a switch and Ic = 0
Bipolar Transistors are current regulating devices that control the amount of
current flowing through them in proportion to the amount of biasing voltage
applied to their base terminal acting like a current-controlled switch. The
principle of operation of the two transistor types PNP and NPN, is exactly the
same the only difference being in their biasing and the polarity of the power
supply for each type(fig 1).
4.3.1 Bipolar Transistor Construction
Fig 4.31 Bipolar Junction Transistor Symbol
The construction and circuit symbols for both the PNP and NPN bipolar
transistor are given above with the arrow in the circuit symbol always
showing the direction of "conventional current flow" between the base
terminal and its emitter terminal. The direction of the arrow always points
from the positive P-type region to the negative N-type region for both
transistor types, exactly the same as for the standard diode symbol.
4.3.2 TRANSISTOR CURRENT COMPONENTS:
Fig 4.32 Bipolar Junction Transistor Current Components
The above fig 4.2 shows the various current components, which flow across
the forward biased emitter junction and reverse- biased collector junction.
The emitter current IE consists of hole current IPE (holes crossing from emitter
into base) and electron current InE (electrons crossing from base into
emitter).The ratio of hole to electron currents, IpE / InE , crossing the emitter
junction is proportional to the ratio of the conductivity of the p material to
that of the n material. In a transistor, the doping of that of the emitter is made
much larger than the doping of the base. This feature ensures (in p-n-p
transistor) that the emitter current consists an almost entirely of holes.
Such a situation is desired since the current which results from electrons
crossing the emitter junction from base to emitter do not contribute carriers,
which can reach the collector.
Not all the holes crossing the emitter junction JE reach the the collector
junction JC
Because some of them combine with the electrons in n-type base. If IpC is hole
current at junction JC there must be a bulk recombination current ( IPE- IpC )
leaving the base.
Actually, electrons enter the base region through the base lead to supply those
charges, which have been lost by recombination with the holes injected in to
the base across JE. If the emitter were open circuited so that IE=0 then IpC would
be zero. Under these circumstances, the base and collector current IC would
equal the reverse saturation current ICO. If IE≠0 then
IC= ICO- IpC
For a p-n-p transistor, ICO consists of holes moving across JC from left to right (base
to collector) and electrons crossing JC in opposite direction. Assumed
referenced direction for ICO i.e. from right to left, then for a p-n-p transistor, ICO is
negative. For an n-p-n transistor, ICO is positive.The basic operation will be
described using the pnp transistor. The operation of the pnp transistor is exactly
the same if the roles played by the electron and hole are interchanged.
One p-n junction of a transistor is reverse-biased, whereas the other is forward-

biased.
Fig 4.33 Forward-biased junction of a pnp transistor
Fig 4.34 Reverse-biased junction of a pnp transistor

Fig 4.35 Both biasing potentials have been applied to a pnp transistor and
resulting majority and minority carrier flows indicated.
Majority carriers (+) will diffuse across the forward-biased p-n junction into
the n-type material.
A very small number of carriers (+) will through n-type material to the base
terminal. Resulting IB is typically in order of microamperes.
The large number of majority carriers will diffuse across the reverse-biased
junction into the p-type material connected to the collector terminal
Applying KCL to the transistor :
IE = IC + IB
The comprises of two components – the majority and minority carriers
I
C = ICmajority +ICOminority
ICO – IC current with emitter terminal open and is called leakage current Various
parameters which relate the current components is given below
Emitter efficiency:
  currentofinjectedcar riersatJ E
totalemitt ercurrent
Transport Factor:
 *  injectedca rriercurrentreachingJC
injectedca rrierncurrentatJ E
 *  pC
I
I nE
Large signal current gain:

The ratio of the negative of collector current increment to the emitter current
change from zero (cut- off)to IE the large signal current gain of a common base
transistor.
 (IC  ICO )

IE
Since IC and IE have opposite signs, then α, as defined, is always positive. Typically
numerical values of α lies in the range of 0.90 to 0.995
I pC I pC I pE
  *
The transistor alpha is the product of the transport factor and the emitter
efficiency. This statement assumes that the collector multiplication ratio  * is
unity.  * is the ratio of total current crossing JC to hole arriving at the junction.
4.3.3 Bipolar Transistor Configurations
As the Bipolar Transistor is a three terminal device, there are basically three
possible ways to connect it within an electronic circuit with one terminal
being common to both the input and output. Each method of connection
responding differently to its input signal within a circuit as the static
characteristics of the transistor vary with each circuit arrangement.
The transistor alpha is the product of the transport factor and the emitter
efficiency. This statement assumes that the collector multiplication ratio 
*
is unity.  * is the ratio of total current crossing JC to hole arriving at the
junction.
4.3.4 Bipolar Transistor Configurations
As the Bipolar Transistor is a three terminal device, there are basically three
possible ways to connect it within an electronic circuit with one terminal
being common to both the input and output. Each method of connection
responding differently to its input signal within a circuit as the static
characteristics of the transistor vary with each circuit arrangement.
4.3.5 COMMON-BASE CONFIGURATION

Common-base terminology is derived from the fact that the : base is common to
both input and output of t configuration. base is usually the terminal closest to
or at ground potential. Majority carriers can cross the reverse-biased junction
because the injected majority carriers will appear as minority carriers in the n-
type material. All current directions will refer to conventional (hole) flow and the
arrows in all electronic symbols have a direction defined by this convention.
Note that the applied biasing (voltage sources) are such as to establish current in
the direction indicated for each branch.
Fig 4.36 CB Configuration

To describe the behavior of common-base amplifiers requires two set of

characteristics:
Input or driving point characteristics.

Output or collector characteristics
The output characteristics has 3 basic regions:
Active region –defined by the biasing arrangements

Cutoff region – region where the collector current is 0A
 Saturation region- region of the characteristics to the left of VCB = 0V
Fig 4.37 CB Input-Output Characteristics

The curves (output characteristics) clearly indicate that a first approximation to the
relationship between IE and IC in the active region is given by
IC ≈IE
Once a transistor is in the ‘on’ state, the base-emitter voltage will be assumed to
beVBE = 0.7V
Fig 4.38
In the dc mode the level of IC and IE due to the majority carriers are related by a
quantity called alpha
= αdc
IC = IE + ICBO
It can then be summarize to IC = IE (ignore ICBO due to small value)

For ac situations where the point of operation moves on the characteristics curve,
an ac alpha defined by αac
Alpha a common base current gain factor that shows the efficiency by calculating
the current percent from current flow from emitter to collector. The value of  is
typical from 0.9 ~ 0.998.
Biasing:Proper biasing CB configuration in active region by approximation IC  IE (IB

 0 uA)
Fig 4.39 CE Configuration

4.3.6 TRANSISTOR AS AN AMPLIFIER
Fig 4.40
Common-Emitter Configuration
It is called common-emitter configuration since : emitter is common or
reference to both input and output terminals.emitter is usually the terminal
closest to or at ground potential.
Almost amplifier design is using connection of CE due to the high gain for
current and voltage.
Two set of characteristics are necessary to describe the behavior for CE ;input
(base terminal) and output (collector terminal) parameters.
Proper Biasing common-emitter configuration in active region

Fig 4.41 CE Configuration
IB is microamperes compared to miliamperes of IC.

IB will flow when VBE > 0.7V for silicon and 0.3V for germanium Before this
value IB is very small and no IB.
Base-emitter junction is forward bias Increasing VCE will reduce IB for different
values.
Fig 4.42 Input characteristics for common-emitter npn transistor
Fig 4.43 Output characteristics for common-emitter npn transistor

For small VCE (VCE < VCESAT, IC increase linearly with increasing of VCE
VCE > VCESAT IC not totally depends on VCE  constant IC

IB(uA) is very small compare to IC (mA). Small increase in IB cause big increase in
IC IB=0 A  ICEO occur.
Noticing the value when IC=0A. There is still some value of current flows.
Fig 4.44
4.3.7 Beta () or amplification factor

The ratio of dc collector current (IC) to the dc base current (IB) is dc beta (dc )
which is dc current gain where IC and IB are determined at a particular operating
point, Q-point (quiescent point). It’s define by the following equation:
30 < dc < 300  2N3904

On data sheet,  dc=hfe with h is derived from ac hybrid equivalent cct. FE are
derived from forward- current amplification and common-emitter configuration
respectively.
Fig 4.45
For ac conditions, an ac beta has been defined as the changes of collector

current (IC) compared to the changes of base current (IB) where IC and IB are
determined at operating point. On data sheet,
 ac=hfe It can defined by the following equation:
Fig 4.46
From output characteristics of commonemitter configuration, find  ac and  dc

with an
Operating point at IB=25 A and VCE =7.5V

Fig 4.47
Relationship analysis between α and β
4.3.8 COMMON – COLLECTOR CONFIGURATION

Also called emitter-follower (EF). It is called common-emitter configuration since
both the signal source and the load share the collector terminal as a common
connection point.The output voltage is obtained at emitter terminal. The input
characteristic of common-collector configuration is
similar with common-emitter. configuration.Common-collector circuit

configuration is provided with the load resistor connected from emitter to
ground. It is used primarily for impedance- matching purpose since it has high
input impedance and low output impedance.
Fig 4.48 CC Configuration
For the common-collector configuration, the output characteristics are a plot

of IE vs VCE for a range
of values of IB.
Fig 4.49 Output Characteristics of CC Configuration for npn Transistor

4.3.9 Limits of opearation

Many BJT transistor used as an amplifier. Thus it is important to notice the limits
of operations.At least 3 maximum values is mentioned in data sheet.
There are:
Maximum power dissipation at collector: PCmax or PD
Maximum collector-emitter voltage: VCEmax sometimes named as VBR(CEO) or VCEO.
Maximum collector current: ICmax
There are few rules that need to be followed for BJT transistor used as an
amplifier. The rules are: transistor need to be operate in active region!
IC < ICmax PC < PCmax
Fig 4.50
Note: VCE is at maximum and IC is at minimum (ICMAX=ICEO) in the cutoff region.

IC is at maximum and VCE is at minimum (VCE max = Vcesat = VCEO) in the saturation
region. The transistor
operates in the active region between saturation and cutoff.
Fig 4.51
Refer to the fig. Example; A derating factor of 2mW/°C indicates the power
dissipation is reduced 2mW each degree centigrade increase of temperature.
Step1:
The maximum collector power dissipation,
PD=ICMAX x VCEmax= 18m x 20 = 360 mW
Step 2:
At any point on the characteristics the product of and must be equal to 360
mW. Ex. 1. If choose ICmax= 5 mA, substitute into the (1), we get
VCEmaxICmax= 360 mW VCEmax(5 m)=360/5=7.2 V
Ex.2. If choose VCEmax=18 V, substitute into (1), we get
VCEmaxICmax= 360 mW
(10) ICMAX=360m/18=20 mA
Derating PDmax
PDMAX is usually specified at 25°C.
The higher temperature goes, the less is PDMAX

Example;A derating factor of 2mW/°C indicates the power dissipation is reduced
2mW each degree centigrade increase of temperature.
BJT HYBRID MODEL

Small signal low frequency transistor Models:
All the transistor amplifiers are two port networks having two voltages and two
currents. The positive directions of voltages and currents are shown in fig. 1.
4.4 Rectifiers
 The electronic circuits require a D.C source of power. For transistor, A.C
amplifier cirucuit for biasing, D.C supply is required. The input signal can
be A.C and so the output signal will be amplified A.C signal. But without
biasing with D.C supply, the circuit will not work. So more or less all
electronic A.C instruments, required D.C power. To get this, D.C batteries
can be used.But they will get dried quickly and replacing them every time
is a costly affair. Hence it is economical to convert A.C power into
D.C.Such circuits, their efficiency etc will be discussed further.
 Rectifier is a circuit which offers low resistance to the current in one

direction and high resistance in the opposite direction.
 Rectifier converts sinusoidal signal to unidirectional flow and not pure

D.C
Filter converts unidirectional flow into pure D.C
 If the input to the rectifier is a pure sinusoidal wave, the average value of
such a wave is zero, since the positive half cycle and negative half cycle
are exactly equal.
4.4.1 HALF WAVE RECTIFIERS
Rectifiers are the circuits used to convert alternating current (AC) into direct
current (DC). Half-Wave Rectifiers are designed using a diode (D) and a load
resistor (RL) as shown in
Figure 1. In these rectifiers, only one-half of the input waveform is obtained at

the output i.e. the output will comprise of either positive pulses or the negative
pulses only. The polarity of the output voltage so obtained (across RL) depends on the direction of the
diode used in the circuit of half-wave rectifier. This is evident from the figure as
Figure 1a shows the output waveform consisting of only positive pulses while
the Figure 1b has only negative pulses in its output waveform.
Fig 4.52
This is because, in Figure 1a the diode gets forward biased only during
the positive pulse of the input which causes the current to flow
across RL, producing the output voltage.Further for the same
case, if the input pulse becomes negative, then the diode will be
reverse biased and hence there will be no current flow and no output
voltage. Similarly for the circuit shown in Figure 1b, the diode will be
forward biased only when the input pulse is negative, and thus the
output voltage will contain only the negative pulses. Further it is to be
noted that the input to the half-wave rectifier can be supplied even via
the transformer. This is advantageous as the transformer provides
isolation from the power line as well as helps in obtaining the desired
level of DC voltage. Next, one can connect a capacitor across the
resistor in the circuit of half wave rectifier to obtain a smoother DC
output (Figure 2).
Fig 4.53
Different parameters associated with the half wave rectifiers are

1. Peak Inverse Voltage (PIV): This is the maximum voltage which should be
withstood by the diode under reverse biased condition and is equal to the peak of
the input voltage, Vm.
Average Voltage: This is the DC content of the voltage across the load and
is given by Vm/π. Similarly DC current is given as Im/π, where Im is the
maximum value of the current.
Ripple Factor (r): It is the ratio of root mean square (rms) value of AC
component to the DC component in the output and is given by
Further, for half-wave rectifier, rms voltage is given as Vm/2 which

results in the ripple factor of 1.21.
Efficiency: It is the ratio of DC output power to the AC input power

and is equal to 40.6%.
Transformer Utilization Factor: It is the ratio of DC power delivered to

the load to the AC rating of the transformer secondary and is equal to
0.287.
terminals.
Form Factor: This is the ratio of rms value to the average value and is
thus equal to 1.57
for half-wave rectifier.
Peak Factor: It is the ratio of peak value to the rms value and is equal to
2.
Half wave rectifiers are advantageous as they are cheap, simple and easy
to construct. These are quite rarely used as they have high ripple content
in their output. However they can be used in non-critical applications like
those of charging the battery. They are also less preferred when
compared to other rectifiers as they have low output power, low
rectification efficiency and low transformer utilization factor. In addition, if
AC input is fed via the transformer, then it might get saturated which inturn
results in magnetizing current, hysteresis loss and/or result in the
generation of harmonics. Lastly it is important to note that the explanation
provided here applies only for the case where the diode is ideal. Although
for a practical diode, the basic working remains the same, one will have to
consider the voltage drop across the diode as well as its reverse
saturation current into consideration during the analysis.
4.4.2 FULL WAVE RECTIFIERS

The circuits which convert the input alternating current (AC) into direct
current (DC) are referred to as rectifiers. If such rectifiers rectify both the
positive as well as negative pulses of the input waveform, then they are
called Full-Wave Rectifiers. Figure 1 shows such a rectifier designed using
a multiple winding transformer whose secondary winding is equally divided
into two parts with a provision for the connection at its central point (and
thus referred to as the centre-tapped transformer), two diodes (D1 and D2) and a load resistor (RL).
Here the AC input is fed to the primary winding of the transformer while an
arrangement of diodes and the load resistor which yields the DC output, is
made across its secondary
Fig 4.54
The circuit can be analyzed by considering its working during the positive
and the negative input pulses separately.
Figure 2a shows the case where the AC pulse is positive in nature i.e. the
polarity at the top of the primary winding is positive while its bottom will be
negative in polarity. This causes the top part of the secondary winding to
acquire a positive charge while the common centre-tap terminal of the
transformer will become negative.
Fig 4.55
This causes the diode D1 to be forward biased which inturn causes the
flow of current through RL along the direction shown in Figure 2a.
However at the same time, diode D2 will be reverse biased and hence
acts like an open circuit. This causes the appearance of positive
pulse across the RL, which will be the DC output. Next, if the input
pulse becomes negative in nature, then the top and the bottom of the
primary winding will acquire the negative and the positive
polarities respectively. This causes the bottom of the secondary
winding to become positive while its centre-tapped terminal will
become negative. Thus the diode D2 gets forward biased while the D1
will get reverse biased which allows the flow of current as shown in the
Figure 2b. Here the most important thing to note is the fact that the
direction in which the current flows via R L will be identical in
either case (both for positive as well as for negative input
pulses). Thus we get the positive output pulse even for the case of
negative
input pulse (Figure 3), which indicates that both the half
cycles of the input AC are rectified.
Fig 4.56
Such circuits are referred to as (i) Centre-Tapped Full Wave

Rectifiers as they use a centre- tapped transformer, (ii) Two-Diode
Full-Wave Rectifiers because of the use of two diodes and/or (iii)
Bi-Phase Circuits due to the fact that in these circuits, the output
voltage will be the phasor addition of the voltages developed across
the load resistor due to two individual diodes, where each of them
conducts only for a particular half-cycle. However as evident from
Figure 3, the output of the rectifier is not pure DC but pulsating in
nature, where the frequency of the output waveform is seen to be
double of that at the input. In order to smoothen this, one can
connect a capacitor across the load resistor as shown by the Figure 4.
This causes the capacitor to charge via the diode D1 as long as the
input positive pulse increases in its magnitude. By the time the
input pulse reaches the positive maxima, the capacitor would have
charged to the same magnitude. Next, as long as the input positive
pulse keeps on decreasing, the capacitor tries to hold the charge
acquired (being an energy-storage element).
Fig 4.57
However there will be voltage-loss as some amount of charge

gets lost through the path provided by the load resistor
(nothing but discharging phenomenon). Further, as the input
pulse starts to go low to reach the negative maxima, the
capacitor again starts to charge via the path provided by the
diode D2 and acquires an almost equal voltage but with
opposite polarity. Next, as the input voltage starts to move
towards 0V, the capacitor slightly discharges via RL. This
charge-discharge cycle of the capacitor causes the ripples to
appear in the output waveform of the full-wave rectifier
with RC filter as shown in Figure 4.
Different parameters and their values for the centre-tapped full-

wave rectifiers are
1. Peak Inverse Voltage (PIV): This is the maximum voltage

which occurs across the diodes when they are reverse biased.
Here it will be equal to twice the peak of the input voltage,
2Vm.
2. Average Voltage: It is the DC voltage available across the

load and is equal to 2Vm/π. The corresponding DC current
will be 2Im/π, where Im is the maximum value of the current.
3. Ripple Factor (r): This is the ratio of the root mean square
(rms) value of AC component
to the dc component at the output. It is given by
and will be equal to 0.482 as the rms voltage for a full-wave rectifier is
given as
Efficiency: This is the ratio of DC output power to the AC input

power and is equal to 81.2
%.
Transformer Utilization Factor (TUF): This factor is expressed as
the ratio of DC power delivered to the load to the AC rating of the
transformer secondary. For the full-wave rectifier this will be 0.693.
Form Factor: This is the ratio of rms value to the average value and
is equal to 1.11.
Peak Factor: It is the ratio of peak value to the rms value and is equal
to √2 for the full- wave rectifiers.
Further it is to be noted that the two-diode full-wave rectifier shown

in Figure 1 is costly and bulky in size as it uses the complex centre-
tapped transformer in its design. Thus one may resort to another type
of full-wave rectifier called Full-Wave Bridge Rectifier (identical to
Bridge Rectifier) which might or might not involve the transformer
(even if used, will not be as complicated as a centre-tap one). It also
offers higher TUF and higher PIV which makes it ideal for high
power applications. However it is to be noted that the full wave bridge
rectifier uses four diodes instead of two, which in turn increases the
magnitude of voltage drop across the diodes, increasing the heating
loss. Full wave rectifiers are used in general power supplies, to
charge a battery and to provide power to the devices like motors,
LEDs, etc.
However due to the ripple content in the output waveform, they are
not preferred for audio applications. Further these are advantageous
when compared to half-wave rectifiers as they have higher DC output
power, higher transformer utilization factor and lower ripple content,
which can be made more smoother by using π-filters. All these merits
mask-up its demerit of being costly in comparison to the half-wave
rectifiers due to the use of increased circuit elements. At last, it is to
be noted that the explanation provided here considers the diodes to be
ideal in nature. So, incase of practical diodes, one will have to consider
the voltage drop across the diode, its reverse saturation current and
other diode characteristics into account and reanalyze the circuit.
Nevertheless the basic working remains the same.
4.4.3 BRIDGE RECTIFIERS
Bridge Rectifiers are the circuits which convert alternating current

(AC) into direct current (DC) using the diodes arranged in the bridge
circuit configuration. They usually comprise of four or more number
of diodes which cause the output generated to be of the same polarity
irrespective of the polarity at the input. Figure 1 shows such a bridge
rectifier composed of four diodes D1, D2, D3 and D4 in which the
input is supplied across two terminals A and B in the figure while
the output is collected across the load resistor RL connected between
the terminals C and D.
Fig 4.58
Now consider the case wherein the positive pulse appears at the AC
input i.e. the terminal A is positive while the terminal B is negative.
This causes the diodes D1 and D3 to get forward biased and at the
same time, the diodes D2 and D4 will be reverse biased.
As a result, the current flows along the short-circuited path created

by the diodes D1 and D3 (considering the diodes to be ideal), as
shown by Figure 2a. Thus the voltage developed across the load
resistor RL will be positive towards the end connected to terminal D
and negative at the end connected to the terminal C.
Fig 4.59
Next if the negative pulse appears at the AC input, then the

terminals A and B are negative and positive respectively.
This forward biases the diodes D2 and D4, while reverse
biasing D1 and D3 which causes the current to flow in the
direction shown by Figure 2b. At this instant, one has to
note that the polarity of the voltage developed across RL
is identical to that produced when the incoming AC pulse
was positive in nature. This means that for both positive and
negative pulse, the output of the bridge rectifier will be
identical in polarity as shown by the wave forms in Figure
3.
Fig 4.60
However it is to be noted that the bridge rectifier's DC will be pulsating

in nature. In order to obtain pure form of DC, one has to use capacitor
in conjunction with the bridge circuit (Figure 4).
Fig 4.61
In this design, the positive pulse at the input causes the capacitor to
charge through the diodes D1 and D3. However as the negative pulse
arrives at the input, the charging action of the capacitor ceases
and it starts to discharge via RL. This results in the
generation of DC output which will have ripples in it as shown in
the figure. This ripple factor is defined as the ratio of AC component
to the DC component in the output voltage. In addition, the
mathematical expression for the ripple voltage is given by the
equation
Where, Vr represents the ripple voltage.

Il represents the load current.
f represents the frequency of the ripple which will be
twice the input frequency. C is the Capacitance.
Further, the bridge rectifiers can be majorly of two types, viz.,

Single-Phase Rectifiers and Three-Phase Rectifiers. In addition,
each of these can be either Uncontrolled or Half- Controlled or
Full-Controlled. Bridge rectifiers for a particular application are
selected by considering the load current requirements. These bridge
rectifiers are quite advantageous as they can be constructed with or
without a transformer and are suitable for high voltage applications.
However here two diodes will be conducting for every half-cycle
and thus the voltage drop across the diodes will be higher. Lastly
one has to note that apart from converting AC to DC, bridge
rectifiers are also used to detect the amplitude of modulated radio
signals and to supply polarized voltage for welding applications.
4.5 Basic information about operational amplifiers
An operational amplifier is a direct coupled high gain amplifier consisting of

one or more differential amplifiers, followed by a level translator and an
output stage.
It is a versatile device that can be used to amplify ac as well as dc input
signals & designed for computing mathematical functions such as addition,
subtraction ,multiplication, integration & differentiation
4.5.1 Ideal operational Amplifiers
Fig 4.62
 Infinite voltage gain A.

 Infinite input resistance Ri, so that almost any signal source can
drive it and there is no
 loading of the proceeding stage.
 Zero output resistance Ro, so that the output can drive an infinite
number of other devices.
 Zero output voltage, when input voltage is zero.
 Infinite bandwidth, so that any frequency signals from o to ∞ HZ can
be amplified with out attenuation.
 Infinite common mode rejection ratio, so that the output common
mode noise voltage is zero.
 Infinite slew rate, so that output voltage changes occur
simultaneously with input voltage
4.5.2 General Operational Amplifier stages and internal circuit

diagrams of IC 741
An operational amplifier generally consists of three stages, namely

A differential amplifier
Additional amplifier stages to provide the required voltage gain and dc
level shifting.
An emitter-follower or source follower output stage to provide current gain
and low output resistance.
A low-frequency or dc gain of approximately 104 is desired for a general
purpose op-amp and hence, the use of active load is preferred in the
internal circuitry of op-amp.
The output voltage is required to be at ground, when the differential input
voltages are zero, and this necessitates the use of dual polarity supply
voltage. Since the output resistance of op-amp is required to be low, a
complementary push-pull emitter – follower or source follower output
stage is employed. Moreover, as the input bias currents are to be very
small of the order of pico amperes, an FET input stage is normally
preferred.
Input stage:
The input differential amplifier stage uses p-channel JFETs M1 and M2. It
employs a three- transistor active load formed by Q3, Q4, and Q5. The bias
current for the stage is provided by a two-transistor current source using
PNP transistors Q6 and Q7. Resistor R1 increases the o utput resistance
seen looking into the collector of Q4 as indicated by R04. This is necessary
to provide bias current stability against the transistor parameter variations.
Resistor R2 establishes a definite bias current through Q5. A single ended
output is taken out at the collector of Q4.
MOSFET‘s are used in place of JFETs with additional devices in the circuit
to prevent any damage for the gate oxide due to electrostatic discharges.
Gain stage:
The second stage or the gain stage uses Darlington transistor pair formed
by Q8 and Q9 as shown in figure. The transistor Q8 is connected as an
emitter follower, providing large input resistance.
Therefore, it minimizes the loading effect on the input differential amplifier
stage. The transistor Q9 provides an additional gain and Q10 acts as an
active load for this stage. The current mirror
formed by Q7 and Q10 establishes the bias current for Q9. The VBE drop
across Q9 and drop across R5 constitute the voltage drop across R4, and
this voltage sets the current through Q8. It can be set to a small value,
such that the base current of Q8 also is very less.
Fig.4.63
Fig 1.17 Internal stages of Op-amp
Output stage:
The final stage of the op-amp is a class AB complementary push-pull
output stage. Q11 is an
emitter follower, providing a large input resistance for minimizing the
loading effects on the gain stage. Bias current for Q11 is provided by the
current mirror formed by Q7 and Q12, through Q13 and Q14 for minimizing
the cross over distortion. Transistors can also be used in place of the two
diodes.
The overall voltage gain AV of the op-amp is the product of voltage gain of
each stage as given by
AV=|Ad| |A2||A3|
Where Ad is the gain of the differential amplifier stage, A2 is the gain of the
second gain stage and A3 is the gain of the output stage.
4.6 Amplifier (Open – loop op-amp Configuration:)
The term open-loop indicates that no feedback in any form is fed to the
input from the output. When connected in open – loop the op-amp
functions as a very high gain amplifier. There are three open – loop
configurations of op-amp namely,
 Differential amplifier
 Inverting amplifier
 Non-inverting amplifier
The above classification is made based on the number of inputs used and
the terminal to which the input is applied. The op-amp amplifies both ac
and dc input signals. Thus, the input signals can be either ac or dc
voltage.
4.6.1 Loop Differential Amplifier:
In this configuration, the inputs are applied to both the inverting and the
non- inverting input terminals of the op-amp and it amplifies the
difference between the two input voltages. Figure shows the open-loop
differential amplifier configuration.
The input voltages are represented by Vi1 and Vi2. The source resistance
Ri1 and Ri2 are
negligibly small in comparison with the very high input resistance offered
by the op-amp, and thus the voltage drop across these source
resistances is assumed to be zero. The output voltage V0 is given by
V0 = A (Vi1 – Vi2)
where A is the large signal voltage gain. Thus the output voltage is equal
to the voltage gain A times the difference between the two input
voltages. This is the reason why this configuration is called a differential
amplifier. In open – loop configurations, the large signal voltage gain A is
also called open-loop gain A.
Fig 4.64
4.6.4 Non-inverting Amplifier:
Figure shows the open – loop non- inverting amplifier. The input signal is
applied to the non-inverting input terminal of the op-amp and the inverting
input terminal is connected to the ground. The input signal is amplified by
the open – loop gain A and the output is in-phase with input signal. V0 = AVi
Fig 4.66
In all the above open-loop configurations, only very small values of input
voltages can be applied. Even for voltages levels slightly greater than
zero, the output is driven into saturation, which is observed from the
ideal transfer characteristics of op-amp shown in figure. Thus, when
operated in the open-loop configuration, the output of the op-amp is
either in negative or positive saturation, or switches between positive
and negative saturation levels. This prevents the use of open – loop
configuration of op-amps in linear applications.
4.6.2 Inverting amplifier:

In this configuration the input signal is applied to the inverting input
terminal of the op- amp and the non-inverting input terminal is connected
to the ground. Figure shows the circuit of an open
– loop inverting amplifier. The output voltage is 180 out of phase with
respect to the input and hence, the output voltage V0 is given by, V0 = -
AVi. Thus, in an inverting amplifier, the input signal
is amplified by the open-loop gain A and in phase shifted by 180
Fig 4.65
4.6.3 Non-inverting Amplifier:
Figure shows the open – loop non- inverting amplifier. The input signal is
applied to the non-inverting input terminal of the op-amp and the inverting
input terminal is connected to the ground. The input signal is amplified by
the open – loop gain A and the output is in-phase with input signal. V0 = AVi
Fig 4.66
In all the above open-loop configurations, only very small values of input
voltages can be applied. Even for voltages levels slightly greater than
zero, the output is driven into saturation, which is observed from the
ideal transfer characteristics of op-amp shown in figure. Thus, when
operated in the open-loop configuration, the output of the op-amp is
either in negative or positive saturation, or switches between positive
and negative saturation levels. This prevents the use of open – loop
configuration of op-amps in linear applications.
4.7 OSCILLATORS
4.7.1 Introduction about Oscillators
An oscillator is a circuit that produces a repetitive signal from a dc voltage.

The feedback type oscillator which rely on a positive feedback of the output to
maintain the oscillations. The relaxation oscillator makes use of an RC timing
circuit to generate a non-sinusoidal signal such as square wave.
Fig 4.67
Fig 4.68
 The requirements for oscillation are described by the

Baukhausen criterion:

 The magnitude of the loop gain Aβ must be 1


 The phase shift of the loop gain A β must be 0o or 360o or

integer multiple of 2pi
Amplitude stabilization:
In both the oscillators above, the loop gain is set by component values
In practice the gain of the active components is very variuable
If the gain of the circuit is too high it will saturate
If the gain of the circuit is too low the oscillation will die
Real circuits need some means of stabilizing the magnitude of the oscillation
to cope with variability in the gain of the circuit
4.7.2 Barkhausan criterion
The conditions for oscillator to produce oscillation are given by Barkhausan

criterion. They are :
The total phase shift produced by the circuit should be 360o or 0o

The Magnitude of loop gain must be greater than or equal to 1 (ie)|Aβ|≥1
In practice loop gain is kept slightily greater than unity to ensure that oscillator
work even if there is a slight change in the circuit parameters
4.7.3 Basic Oscillator Feedback

Circuit
Without feedback:
With feedback:
4.7.4 RC Phase-Shift Oscillator
In a RC Oscillator the input is shifted 180 through the amplifier stage and180
again through a second inverting stage giving us "180 + 180 = 360 " of phase
shift which is the same as o thereby giving us the required positive feedback.
In other words, the phase shift of the feedback
loop should be "0".
In a Resistance-Capacitance Oscillator or simply an RC Oscillator, we make
use of the fact that a phase shift occurs between the input to a RC network
and the output from the same network by using RC elements in the feedback
branch, for example.
RC phase shift network:
Fig 4.69
RC phase shift network:
Fig 4.70
RC Phase-Shift Network
The RC Oscillator which is also called a Phase Shift Oscillator, produces a

sine wave output signal using regenerative feedback from the resistor-
capacitor combination. This regenerative feedback from the RC network is
due to the ability of the capacitor to store an electric charge, (similar to the
LC tank circuit).
This resistor-capacitor feedback network can be connected as shown above

to produce a leading phase shift (phase advance network) or interchanged
to produce a lagging phase shift (phase retard network) the outcome is still
the same as the sine wave oscillations only occur at the frequency at which
o
the overall phase-shift is 360 . By varying one or more of the resistors or
capacitors in the
phase-shift network, the frequency can be varied and generally this is done
using a 3-ganged variable capacitor
If all the resistors, R and the capacitors, C in the phase shift network are
equal in value, then the
frequency of oscillations produced by the RC oscillator is given as:

where
ƒr is the oscillators output frequency in Hertz
R is the feedback resistance in Ohms
C is the feddback capacitance in Farads
N is the number of RC feedback stages.
4.8 Rectifier:
The ordinary diodes cannot rectify voltages below the cut-in-voltage of the
diode. A circuit which can act as an ideal diode or precision signal –
processing rectifier circuit for rectifying voltages which are below the level
of cut-in voltage of the diode can be designed by placing the diode in the
feedback loop of an op-amp.
Fig 4.71
Fig 4.72
Figure shows the arrangement of a precision diode. It is a single diode

arrangement and functions as a non-inverting precision half– wave
rectifier circuit. If V1 in the circuit of figure is positive, the op-amp output
VOA also becomes positive. Then the closed loop condition is achieved
for the op-amp and the output voltage V0 = Vi . When Vi < 0, the voltage
V0A becomes negative and the diode is reverse biased. The loop is then
broken and the output V0 = 0.
Consider the open loop gain AOL of the op-amp is approximately 104 and
the cut-in voltage Vγ for silicon diode is ≈ 0.7V. When the input voltage Vi
> Vγ / AOL, the output of the op-amp VOA exceeds Vγ and the diode D
conducts.
Then the circuit acts like a voltage follower for input voltage level Vi >
Vγ / AOL ,(i.e.
when Vi > 0.7/104 = 70μV), and the output voltage V0 follows the input
voltage during the positive half cycle for input voltages higher than 70μV
as shown in figure.
When Vi is negative or less than Vγ / AOL, the output of op-amp VOA

becomes negative, and the diode becomes reverse biased. The loop is
then broken, and the op-amp swings down to negative saturation.
However, the output terminal is now isolated from both the input signal
and the output of the op-amp terminal thus V0 =0.
No current is then delivered to the load RL except for the small bias
current of the op-amp and the reverse saturation current of the diode.
This circuit is an example of a non-linear circuit, in which linear

operation is achievedover the remaining region (Vi < 0). Since the
output swings to negative saturation level when Vi <
0, the circuit is basically of saturating form. Thus the frequency response
is also limited.
Applications:
The precision diodes are used in
 half wave rectifier,
 Full-wave rectifier,
 peak value detector,
 Clipper and clamper circuits.
 Disadvantage:
It can be observed that the precision diode as shown in figure
operated in the first quadrant with Vi
> 0 and V0 > 0.
The operation in third quadrant can be achieved by connecting the
diode in reverse direction.
4.8.1 Half – wave Rectifier:
A non-saturating half wave precision rectifier circuit is shown in figure.

When Vi > 0V, the voltage at the inverting input becomes positive,
forcing the output VOA to go negative. This results in forward biasing
the diode D1 and the op-amp output drops only by ≈ 0.7V below the
inverting input voltage. Diode D2 becomes reverse biased. The output
voltage V0 is zero when the input is positive.
When Vi > 0, the op-amp output VOA becomes positive, forward

biasing the diode D2 and reverse biasing the diode D1. The circuit
then acts like an inverting amplifier circuit with a non- linear diode in
the forward path. The gain of the circuit is unity when Rf = Ri.
Fig 4.73
Fig 4.74
The circuit operation can mathematically be

expressed as
V 0= 0 when V i > 0 and

V 0 = Rf/RiV1 forV i <0
The voltage VoA at the op amp output is VOA= - 0.7V for V i>0
VOA= Rf/RiV1 + 0.7V for V i<0
Advantages:
it is a precision half wave rectifier and
it is a non saturating one.
The inverting characteristics of the output V0 can be circumvented by the
use of an additional inversion for achieving a positive output.
4.8.2 Full wave Rectifier:
The first part of the Full wave circuit is a half wave rectifier circuit. The
second part of the circuit is an inverting amplifier.
Fig 4.75
Fig 4.76
For positive input voltage Vi > 0V and assuming that RF =Ri = R, the
output voltage VOA
= Vi. The voltage V0 appears as (-) input to the summing op-
amp circuit formed by A2, The gain for the input V‘0 is R/(R/2), as shown
in figure.
The input Vi also appears as an input to the summing amplifier. Then, the
net output is V0
characteristics in first quadrant. For negative input Vi < 0V, the output V‘0
of the first part of rectifier circuit is zero. Thus, one input of the summing
circuit has a value of zero. However, Vi is also applied as an input to the
summer circuit formed by the op-amp A2.
The gain for this input id (-R/R) = -1, and hence the output is V0 = -
Vi. Since Vi is
negative, V0 will be inverted and will thus be positive. This corresponds
to the second quadrant of the circuit.
To summarize the operation of the circuit, V0 = Vi when Vi < 0V and
V0 = Vi for Vi > 0V, and hence V0 = |Vi |
4.9 Integrator:
A circuit in which the output voltage waveform is the integral of the input
voltage waveform is the integrator or Integration Amplifier. Such a circuit is
obtained by using a basic inverting amplifier configuration if the feedback
resistor RF is replaced by a capacitor CF.
The expression for the output voltage V0 can be obtained by KVL eqn. at
node V2.
Fig 4.77
Fig 2.21 Integrator Circuit
i1 = I B + i f Since I B is negligible small, i1 =iF
Relation between current through and
voltage across the capacitor is
iC (t) = Cdvc(t)/dt
V 1=0 because A is very large,
The output voltage can be btained by integrating both sides with respect
to time
V (jw) = V (jw)
Indicates that the output is directly proportional to the negative integral of

the input volts and inversely proportional to the time constant R 1 CF.
Ex: If the input is sine wave -> output is cosine wave. If the input is
square wave -> output is triangular wave.
Fig 4.78
Fig.4.79 Waveforms from Integrator
These waveform with assumption of R1 Cf = 1, Vout =0V (i.e) C =0.

When Vin = 0 the integrator works as an open loop amplifier because
the capacitor CF acts an open circuit to the input offset voltage Vio.
The Input offset voltage Vio and the part of the input is charging
capacitor CF produce the error
voltage at the output of the integrator.
4.10 Differentiator:
The circuit performs the mathematical operation of differentiation (i.e.) the

output waveform is the
derivative of the input waveform. The differentiator may be constructed
from a basic inverting amplifier if an input resistor R1is replaced by a
capacitor C1. Since the differentiator performs the reverse of the
integrator function. Thus the output V0 is equal to RF C1 times the
negative rate
of change of the input voltage Vin with time. The –sign indicates a 180
phase shift of the output waveform V0 with respect to the input signal.
The below circuit will not do this because it has some practical
problems.
The gain of the circuit (RF /XC1) R with R in frequency at a rate of
20dB/decade. This makes the circuit unstable. Also input impedance
XC1s with R in frequency which makes the circuit very susceptible to
high frequency noise.
Fig 4.80 Basic Differentiator

Fig. 4.81 Frequency response of differentiator
From the above fig. fa = frequency at which the gain is 0dB and is
given by
1
2
Both stability and high frequency noise problems can be corrected by the addition of
two components. R1 and CF. This circuit is a practical differentiator.
From Frequency fa to feedback the gain Rs at 20dB/decade after feedback the gain
S at 20dB/
48 DEPT. OF ECE
decade. This 40dB/ decade change in gain is caused by the R1

C1 and RF CF combinations. The gain limiting frequency fb is
given by,
1
=
2
Where R1 C1 = RF CF
R1 C1 and RF CF help to reduce the effect of high frequency input,
amplifier noise and offsets. All R1 C1 and RF CF make the circuit
more stable by preventing the R in gain with frequency.
The input signal will be differentiated properly, if the time period T of the
input signal is larger than
or equal to RF C1 (i.e) T > RF C1 generally, the value of Feedback
and in turn R1 C1 and RF CF values should be selected such that
RF C1>> R1 C1
Fig 4.82
4.11 Digital To Analog Conversion
A DAC converts an abstract finite-precision number (usually a fixed-point

binary number) into a concrete physical quantity (e.g., a voltage or a
pressure). In particular, DACs are often used to convert finite-precision
time series data to a continually-varying physical signal.
A typical DAC converts the abstract numbers into a concrete sequence of
impulses that are then processed by a reconstruction filter using some
form of interpolation to fill in data between the impulses.
Other DAC methods (e.g., methods based on Delta-sigma modulation)
produce a pulse- density modulated signal that can then be filtered in a
similar way to produce a smoothly-varying signal.By the Nyquist–Shannon
sampling theorem, sampled data can be reconstructed perfectly provided
that its bandwidth meets certain requirements (e.g., a baseband signal with
bandwidth less than the Nyquist frequency). However, even with an ideal
reconstruction filter, digital sampling introduces quantization that makes
perfect reconstruction practically impossible. Increasing the digital
resolution (i.e., increasing the number of bits used in each sample) or
introducing sampling dither can reduce this error.
DACs are at the beginning of the analog signal chain, which makes them
very important to
system performance. The most important characteristics of these
devices are:
Specifications:
This is usually stated as the number of bits it uses, which is the base two
logarithm of the number of levels. For instance a 1 bit DAC is designed to
reproduce 2 (21) levels while an 8 bit DAC is designed for 256 (28) levels.
Resolution is related to the
This is usually stated as the number of bits it uses, which is the base two
logarithm of the number of levels. For instance a 1 bit DAC is designed to
reproduce 2 (21) levels while an 8 bit DAC is designed for 256 (28) levels.
Resolution is related to the
Effective number of bits (ENOB) which is a measurement of the actual

resolution attained by the DAC
.
 Maximum sampling frequency: This is a measurement of the
maximum speed at which the DACs circuitry can operate and still
produce the correct output. As stated in the Nyquist–Shannon
sampling theorem, a signal must be sampled at over twice the
frequency of the desired signal. For instance, to reproduce signals in
all the audible spectrum, which includes frequencies of up to 20 kHz, it
is necessary to use DACs that operate at over 40 kHz. The CD
standard samples audio at kHz, thus DACs of this frequency are often
used. A common frequency in cheap computer sound cards is 48
kHz—many work at only this frequency, offering the use of other
sample rates only through (often poor) internal resampling.
 Monotonicity: This refers to the ability of a DAC's analog output to

move only in the direction that the digital input moves (i.e., if the input
increases, the output doesn't dip before asserting the correct output.)
This characteristic is very important for DACs used as a low frequency
signal source or as a digitally programmable trim element.
 THD+N: This is a measurement of the distortion and noise introduced

to the signal by the DAC. It is expressed as a percentage of the total
power of unwanted harmonic distortion and noise that accompany the
desired signal. This is a very important DAC characteristic for dynamic
and small signal DAC applications.
 Dynamic range: This is a measurement of the difference between the
largest and smallest signals the DAC can reproduce expressed in
decibels. This is usually related to DAC resolution and noise floor.
Other measurements, such as phase distortion and sampling period
instability, can also be very important for some applications.
4.11.1 Binary-Weighted Resistor DAC
The binary-weighted-resistor DAC employs the characteristics of the

inverting summer Op Amp circuit. In this type of DAC, the output voltage
is the inverted sum of all the input voltages. If the input resistor values
are set to multiples of two: 1R, 2R and 4R, the output voltage would be
equal to the sum of V1, V2/2 and V3/4. V1 corresponds to the most
significant bit (MSB) while V3 corresponds to the least significant bit
(LSB).
Fig. 4.83 Binary weighted DAC
The circuit for a 4-bit DAC using binary weighted resistor network
is shown below:
Fig. 4.84 weighted resistor DAC using Op-amp

The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1.

The value, 0, represents an open switch while 1 represents a closed switch.
The operational amplifier is used as a summing amplifier, which gives a
weighted sum
of the binary input based on the voltage, Vref.
For a 4-bit DAC, the relationship between Vout and the binary input is as follows:
summing amplifier, which is a polarity-inverting amplifier. When a signal

is applied to the latter type of amplifier, the polarity of the signal is
reversed (i.e. a + input becomes -, or vice versa).
For a n-bit DAC, the relationship between Vout and the binary input is as follows:
The LSB, which is also the incremental step, has a value of - 0.625
V while the MSB or the full scale has a value of - 9.375 V.
Practical Limitations:
o The most significant problem is the large difference in resistor

values required between the LSB and MSB, especially in the
case of high resolution DACs (i.e. those that has large number
of bits). For example, in the case of a 12-bit DAC, if the MSB is
1 k Ω, then the LSB is a staggering 2 MΩ.
o The maintenance of accurate resistances over a large range of
values is problematic. With the current IC fabrication
technology, it is difficult to manufacture resistors over a wide
resistance range that maintains an accurate ratio especially
with variations in temperature.
4.11.2 R-2R Ladder DAC
An enhancement of the binary-weighted resistor DAC is the R-

2R ladder network. This type of DAC utilizes Thevenin’s theorem in
arriving at the desired output voltages.
A disadvantage of the former DAC design was its
requirement of several different precise input resistor values:
one unique value per binary input bit.
The R-2R network consists of resistors with only two values - R
and 2xR. If each input is supplied either 0 volts or reference voltage,
the output voltage will be an analog equivalent of the
binary value of the three bits. VS2 corresponds to the most
significant bit (MSB) while VS0 corresponds to the least significant bit
(LSB).
Fig.4.85 Ladder type DAC circuit

Vout = - (VMSB + Vn + VLSB) = - (VRef + VRef/2 + VRef/ 4)
4.11.3 Inverted Or Current Mode DAC
Current mode DACs operates based on the ladder currents. The ladder is
formed by resistance R in the series path and resistance 2R in the shunt
path. Thus the current is divided into i1 , i2, i3 …………in. in each arm. The
currents are either diverted to the ground bus (io) or to the Virtual-ground bus
( io ).
Fig.4.86 Current mode DAC
The currents are given as

i1 = VREF/2R = (VREF/R) 2-1, i2 = (VREF)/2)/2R = (VREF/R) 2-
2………in = (VREF/R) 2-n.
And the relationship between the currents are given as
i2 = i1/2 i3 = i1/4
i4 = i1/8
in = i1/ 2n-1
Using the bits to identify the status of the switches, and letting V0 = -
Rf io gives V0 = - (Rf/R) VREF (b12-1 + b22-2+ ……….. + bn2-n)
The two currents io and io are complementary to each other and the
potential of io bus must be sufficiently close to that of the io bus.
Otherwise, linearity errors will occur. The final op- amp is usedas current
to voltage converter.
Advantages
The major advantage of current mode D/A converter is that the voltage
change across each switch is minimal. So the charge injection is virtually
eliminated and the switch driver design is made simpler.
In Current mode or inverted ladder type DACs, the stray capacitance do not
affect the
Speed of response of the circuit due to constant ladder node voltages. So
improved speed performance.
4.11.4Voltage Mode DAC
This is the alternative mode of DAC and is called so because the 2R

resistance in the shunt path is switched between two voltages named
as VL and VH. The output of this DAC is obtained from the leftmost
ladder node. As the input is sequenced through all the possible binary
state starting from
All 0s (0…..0) to all 1s (1…..1). The voltage of this node changes in
steps of 2-n (VH - VL) from the minimum voltage of Vo = VL to the
maximum of Vo = VH - 2-n (VH - VL).
Fig. 4.87 Voltage mode DAC
Advantages
The major advantage of this technique is that it allows us to interpolate

between any two voltages, neither of which need not be a zero.
More accurate selection and design of resistors R and 2R are possible
and simple construction.
The binary word length can be easily increased by adding the required
number or R-2R sections.
4.12 A to D Converter- Specifications
Like DAC, ADCs are also having many important specifications. Some of
them are Resolution, Quantization error, Conversion time, Analog error,
Linearity error, DNL error, INL error & Input voltage range.
Resolution:
The resolution refers to the finest minimum change in the signal which is
accepted for conversion,
and it is decided with respect to number of bits. It is given as 1/2n, where ‘n’
is the number of bits in the digital output word. As it is clear, that the
resolution can be improved by increasing the number of bits or the number
of bits representing the given analog input voltage.
Resolution can also be defined as the ratio of change in the value of
input voltage Vi, needed to change the digital output by 1 LSB. It is given
as
Resolution = ViFS / (2n – 1)
Where ‘ViFS’ is the full-scale input voltage. ‘n’ is the number of output
bits.
Quantization error:
If the binary output bit combination is such that for all the values of
input voltage Vi between any
two voltage levels, there is a unavoidable uncertainty about the exact value of Vi
when the output is a particular binary combination. This uncertainty is termed as
quantization error. Its value is ± (1/2) LSB. And it is given as,
QE = ViFS / 2(2n – 1)
Where ‘ViFS’ is the full-scale input voltage ‘n’ is the number of output bits.
Maximum the number of bits selected, finer the resolution and smaller the quantization
error.
Conversion Time:
It is defined as the total time required for an A/D converter to convert an analog signal to
digital output. It depends on the conversion technique and propagation delay of the circui
components.
Analog error: www.studymaterialz.in
An error occurring due to the variations in DC switching point of the

comparator, resistors, reference voltage source, ripples and noises
introduced by the circuit components is termed as Analog error.
Linearity Error:
It is defined as the measure of variation in voltage step size. It indicates the

difference between the transitions for a minimum step of input voltage
change. This is normally specified as fraction of LSB.
Differential Non-Linearity(DNL) Error:
The analog input levels that trigger any two successive output codes should
differ by 1 LSB. Any deviation from this 1 LSB value is called as DNL error.
Integral Non-Linearity (INL) Error:
The deviation of characteristics of an ADC due to missing codes causes INL

error. The maximum deviation of the code from its ideal value after nulling
the offset and gain errors is called as Integral Non-Linearity Error.
Input Voltage Range:
It is the range of voltage that an A/D converter can accept as its input
without causing any overflow in its digital output.
Analog Switches
There were two types of analog switches. Series and Shunt switch. The
Switch operation is shown for both the cases VGS=0 VGS= VGs (off)
Fig 4.88 Series and shunt Analog switches

4.12.1 Direct-conversion ADC/Flash type

ADC:
Fig 4.89
This process is extremely fast with a sampling rate of up to 1 GHz. The

resolution is however, limited because of the large number of
comparators and reference voltages required. The input signal is fed
simultaneously to all comparators. A priority encoder then generates a
digital output that corresponds with the highest activated comparator.
4.12.2 Successive-approximation ADCs
Successive-approximation ADC is a conversion technique based on a

successive- approximation register (SAR). This is also called bit-
weighing conversion that employs a comparator to weigh the applied
input voltage against the output of an N-bit digital-to-analog converter
(DAC).
The final result is obtained as a sum of N weighting steps, in which

each step is a single-bit conversion using the DAC output as a
reference. SAR converters sample at rates up to 1Mbps, requires a
low supply current, and the cheapest in terms of production cost.
A successive-approximation ADC uses a comparator to reject ranges
of voltages, eventually settling on a final voltage range. Successive
approximation works by constantly comparing the input voltage to the
output of an internal digital to analog converter (DAC, fed by the
current value of the approximation) until the best approximation is
achieved.
At each step in this process, a binary value of the approximation is

stored in a successive approximation register (SAR). The SAR uses a
reference voltage (which is the largest signal the ADC is to convert)
for comparisons.
For example if the input voltage is 60 V and the reference voltage is

100 V, in the 1st clock cycle, 60 V is compared to 50 V (the reference,
divided by two. This is the voltage at the output of the internal DAC
when the input is a '1' followed by zeros), and the voltage from the
comparator is positive (or '1') (because 60 V is greater than 50 V). At
this point the first binary digit (MSB) is set to a '1'. In the 2nd clock
cycle the input voltage is compared to 75 V (being halfway between
100 and 50 V:
This is the output of the internal DAC when its input is '11' followed by zeros)
because 60 V is less than 75 V, the comparator output is now negative (or
'0'). The second binary digit is therefore set to a '0'. In the 3rd clock cycle, the
input voltage is compared with 62.5 V (halfway between 50 V and 75 V: This
is the output of the internal DAC when its input is '101' followed by zeros).
The output of the comparator is negative or '0' (because 60 V is less than
62.5 V) so the third binary digit is set to a 0. The fourth clock cycle similarly
results in the fourth digit being a '1' (60 V is greater than 56.25 V, the DAC
output for '1001' followed by zeros). The result of this would be in the binary
form 1001. This is also called bit-weighting conversion, and is similar to a
binary.
The analogue value is rounded to the nearest binary value below, meaning
this converter type is mid-rise (see above). Because the approximations are
successive (not simultaneous), the conversion takes one clock-cycle for
each bit of resolution desired.
The clock frequency must be equal to the sampling frequency multiplied by
the number of bits of resolution desired. For example, to sample audio at
44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be
required.
ADCs of this type have good resolutions and quite wide ranges. They are
more complex than some other designs.
Fig.4.90 Successive approximation ADC

4.12.3 Dual slope ADC (Integrating ADCs)
In an integrating ADC, a current, proportional to the input voltage,

charges a capacitor for a fixed time interval T charge. At the end of this
interval, the device resets its counter and applies an opposite-polarity
negative reference voltage to the integrator input. Because of this, the
capacitor is discharged by a constant current until the integrator output
voltage zero again.
The T discharge interval is proportional to the input voltage level and the
resultant final count provides the digital output, corresponding to the
input signal. This type of ADCs is extremely slow devices with low input
bandwidths. Their advantage, however, is their ability to reject high-
frequency noise and AC line noise such as 50Hz or 60Hz. This makes
them useful in noisy industrial environments and typical application is in
multi-meters.
An integrating ADC (also dual-slope or multi-slope ADC) applies the
unknown input voltage to the input of an integrator and allows the
voltage to ramp for a fixed time period (the run-up period). Then a
known reference voltage of opposite polarity is applied to the integrator
and is allowed to ramp until the integrator output returns to zero (the run-
down period). The input voltage is computed as a function of the
reference voltage, the constant run-up time period, and the measured
run-down time period.
The run-down time measurement is usually made in units of the
converter's clock, so longer integration times allow for higher
resolutions. Likewise, the speed of the converter can be improved by
sacrificing resolution.
Use: Converters of this type (or variations on the concept) are used in
most digital voltmeters for their linearity and flexibility.
4.14 The 555 Timer IC

The 555 is a monolithic timing circuit that can produce accurate & highly
stable time delays or oscillation. The timer basically operates in one of two
modes: either
Monostable (one - shot) multivibrator or
Astable (free running) multivibrator The important features of the 555 timer
are these:
It operates on +5v to +18 v supply voltages It has an adjustable duty
cycle
Timing is from microseconds to hours It has a current o/p
Fig. 4.91. Pin configuration of 555

timer
Pin description:
Pin 1: Ground:
All voltages are measured with respect to this terminal.
Pin 2: Trigger:
The o/p of the timer depends on the amplitude of the external trigger pulse
applied to this pin.
Pin 3: Output:
There are 2 ways a load can be connected to the o/p terminal either
between pin3 & ground or between pin 3 & supply voltage
(Between Pin 3 & Ground ON load) (Between Pin 3 &+ Vcc OFF load)
When the input is low:
The load current flows through the load connected between Pin 3 &
+Vcc in to the output terminal & is called the sink current.
When the output is high:
The current through the load connected between Pin 3 & +Vcc (i.e. ON
load) is zero. However the output terminal supplies current to the normally
OFF load. This current is called the source current.
Pin 4: Reset:
The 555 timer can be reset (disabled) by applying a negative pulse to this
pin. When the reset function is not in use, the reset terminal should be
connected to +Vcc to avoid any false triggering.
Pin 5: Control voltage:
An external voltage applied to this terminal changes the threshold as well as
trigger voltage. In other words by connecting a potentiometer between this
pin & GND, the pulse width of the output waveform can be varied. When not
used, the control pin should be bypassed to ground with 0.01 capacitor to
prevent any noise problems.
Pin 6: Threshold: his is the non inverting input terminal of upper comparator
which monitors the voltage across the external capacitor.
Pin 7: Discharge:
This pin is connected internally to the collector of transistor Q1. When the
output is high Q1 is OFF.
When the output is low Q is (saturated) ON. Pin 8: +Vcc:
The supply voltage of +5V to +18V is applied to this pin with respect to
ground.
Fig.4.92 Block Diagram of 555 Timer IC

From the above figure, three 5k internal resistors act as voltage divider
providing bias voltage of 2/3 Vcc to the upper comparator & 1/3 Vcc to the
lower comparator. It is possible to vary time electronically by applying a
modulation voltage to the control voltage input terminal (5).
In the Stable state:
The output of the control FF is high. This means that the output is low
because of power amplifier which is basically an inverter. Q = 1; Output = 0
At the Negative going trigger pulse:
The trigger passes through (Vcc/3) the output of the lower comparator
goes high & sets the FF. Q = 1; Q = 0
At the Positive going trigger pulse: It passes through 2/3Vcc, the output of
the upper comparator goes high and resets the FF. Q = 0; Q = 1
The reset input (pin 4) provides a mechanism to reset the FF in a
manner which overrides
the effect of any instruction coming to FF from lower comparator.
4.14.1 Monostable Operation:
Fig. 4.93 555 connected as a Monostable

Multivibrator
Fig. 4.94 Waveforms of monostable multivibrators
Initially when the output is low, i.e. the circuit is in a stable state,
transistor Q1 is ON & capacitor C is shorted to ground. The output
remains low. During negative going trigger pulse, transistor Q1 is OFF,
which releases the short circuit across the external capacitor C & drives
the output high. Now the capacitor C starts charging toward Vcc through
RA. When the voltage across the capacitor equals 2/3 Vcc, upper
comparator switches from low to high. i.e. Q = 0, the transistor Q1 =
OFF ; the output is high.
Since C is unclamped, voltage across it rises exponentially through R
towards Vcc with a time constant RC (fig b) as shown in below. After the
time period, the upper comparator resets the FF,
i.e. Q = 1, Q1 = ON; the output is low.[i.e discharging the capacitor C to
ground potential (fig c)]. The voltage across the capacitor as in fig (b) is
given by
Vc = Vcc (1-e-t/RC)……. (1) t = T, Vc = 2/3 Vcc

2/3 Vcc = Vcc(1-e-T/RC) or
T = RC ln (1/3)
Or
T = 1.1RC seconds ……………. (2)
If the reset is applied Q2 = OFF, Q1 = ON, timing capacitor C immediately

discharged. The output now will be as in figure (d & e). If the reset is
released output will still remain low until a negative going trigger pulse is
again applied at pin 2.
4.15 IC Voltage Regulators:
They are basically series regulators.
Important features of IC Regulators:
Programmable output
Facility to boost the voltage/current
Internally provided short circuit current limiting
Thermal shutdown
Floating operation to facilitate higher voltage output
 Classifications of IC voltage regulators:

 Fixed Volt Reg. Positive/negative
 Adjustable O/P Volt Reg
 Switching Reg
Fixed & Adjustable output Voltage Regulators are known as Linear

Regulator.
A series pass transistor is used and it operates always in its active region.
Switching Regulator:
Series Pass Transistor acts as a switch.

The amount of power dissipation in it decreases considerably.
Power saving result is higher efficiency compared to that of linear.
Advantages of Adjustable Voltage Regulator over fixed voltage

regulator are,
Adjustable output voltage from 1.2v to 57 v
Output current 0.10 to 1.5 A
Better load & line regulation
Improved overload protection
Improved reliability under the 100% thermal overloading
:
4.15.1 Adjustable Positive Voltage Regulator

(LM317)
Fig. 4.95 Circuit diagram of LM317 regulator
LM317 series adjustable 3 terminal positive voltage regulator, the three terminals
are Vin, Vout & adjustment (ADJ).
LM317 requires only 2 external resistors to set the output voltage.
LM317 produces a voltage of 1.25v between its output & adjustment terminals.
This voltage is called as Vref.
Vref (Reference Voltage) is a constant, hence current I1 flows through R1 will
also be constant. Because resistor R1 sets current I1. It is called “current set” or
“program resistor”.
Resistor R2 is called as “Output set” resistors, hence current through this resistor
is the sum of I1 & Iadj
LM317 is designed in such as that Iadj is very small & constant with changes in
line voltage & load current. Vo = (Vref/R1) R1 + Vref/R1 + Iadj R2
= Vref + (Vref/R1) R2 + Iadj R2
Vo = Vref [1 + R2/R1] + Iadj R2 ------------- (2)
R1 = Current (I1) set resistor R2 = output (Vo) set

resistor.
Vref = 1.25v which is a constant voltage between output and
ADJ terminals.
 Current Iadj is very small. Therefore the second term in (2) can be neglected.
 Thus the final expression for the output voltage is given by
Vo= 1.25v[1 + R2/R1] --------------(3)
Eqn (3) indicates that we can vary the output voltage by varying the resistance R2.
The value of R1 is normally kept constant at 240 ohms for all practical applications.
4.15.2 Practical Regulator using

LM317:
Fig.4.96 Practical regulator
If LM317 is far away from the input power supply, then 0.1μf disc type or 1μf
tantalum capacitor should be used at the input of LM317.
The output capacitor Co is optional. Co should be in the range of 1 to 1000μf.
The adjustment terminal is bypassed with a capacitor C2 this will improve the
ripple rejection ratio as high as 80 dB is obtainable at any output level.
When the filter capacitor is used, it is necessary to use the protective diodes.
These diodes do not allow the capacitor C2 to discharge through the low current
point of the regulator.
These diodes are required only for high output voltages (above 25v) & for
higher values of output capacitance 25μf and above.
4.15.3 IC 723 – General Purpose Regulator www.studymaterialz.in
Disadvantages of fixed voltage regulator:

Do not have the shot circuit
Output voltage is not adjustable These limitations can be
overcomes in IC723.
Features of IC723:
Unregulated dc supply voltage at the input between 9.5V & 40V
Adjustable regulated output voltage between 2 to 3V.
Maximum load current of 150 mA (ILmax = 150mA).
With the additional transistor used, ILmax upto 10A is
obtainable.
Positive or Negative supply operation
Internal Power dissipation of 800mW.
Built in short circuit protection.
Very low temperature drift.
High ripple rejection.
The simplified functional block diagram can be divided in to 4 blocks.
Reference Generating block:

The temperature compensated Zener diode, constant current source &
voltage reference amplifier together from the reference generating
block. The Zener diode is used to generate a fixed reference voltage
internally. Constant current source will make the Zener diode to
operate at affixed point & it is applied to the Non – inverting terminal
of error amplifier. The Unregulated input voltage ±Vcc is applied to
the voltage reference amplifier as well as error amplifier.
Error Amplifier:
Error amplifier is a high gain differential amplifier with 2 input
(inverting & Non- inverting). The Non-inverting terminal is
connected to the internally generated reference voltage. The Inverting
terminal is connected to the full regulated output voltage.
Fig. 4.97 Functional block diagram of

IC723
Fig.4.98 Pin diagram of IC723
Series Pass Transistor:

Q1 is the internal series pass transistor which is driven by the error amplifier. This
transistor actually acts as a variable resistor & regulates the output voltage. The
collector of transistor Q1 is connected to the Un-regulated power supply. The
maximum collector voltage of Q1 is limited to 36Volts. The maximum current which
can be supplied by Q1 is 150mA.
Circuitry to limit the current:
The internal transistor Q2 is used for current sensing & limiting. Q2 is normally OFF
transistor. It turns ON when the IL exceeds a predetermined limit.
Low voltage, Low current is capable of supplying load voltage which is equal to or
between 2 to 7Volts.
Vload = 2 to 7V and Iload= 50mA
1. IC723 as a LOW voltage LOW current:

Fig.4.99 Typical circuit connection diagram

 RThe
1 & R2 from a potential divider between Vref & Gnd.
Voltage across R2 is connected to the Non – inverting
terminal of the regulator IC
Vnon-inv = R2/(R1+R2) Vref
Gain of the internal error amplifier is large

Vnon-inv = Vin
Therefore the Vo is connected to the Inverting terminal through
R3 & RSC be equal to Vnon-inv
Vo = Vnon-inv =R2/(R1+R2) Vref

R1 & R2 can be in the range of 1 KΩ to 10KΩ & value of R3 is given by
R3 = R1ll R2 =R1R2/(R1+R2)
Rsc (current sensing resistor) is connected between Cs & CL. The voltage
drop across Rsc is proportional to the IL.
This resistor supplies the output voltage in the range of 2 to 7 volts, but the load
current can be higher than 150mA.
The current sourcing capacity is increased by including a transistor Q in the circuit.
The output voltage , Vo =R2/(R1+R2) Vref
2. IC723 as a HIGH voltage LOW Current:

This circuit is capable of supplying a regulated output voltage between the ranges
of 7 to 37 volts with a maximum load current of 150 mA.
The Non – inverting terminal is now connected to Vref through resistance R3.
The value of R1 & R2 is adjusted in order to get a voltage of Vref at
the inverting terminal at the desired output.
Vin = Vref =R2 /(R1+R2) V0 Vo = [1+R1/R2] Vin
Rsc is connected between CL & Cs terminals as before & it provides the
short
Circuit current limiting Rsc =0.6/Ilimit
The value of resistors R3 is given by ,
R3= R1ll R2 =R1R2/(R1+R2)
3. IC723 as a HIGH voltage HIGH Current:

An external transistor Q is added in the circuit for high voltage low current
For this
regulator to circuit
improve theitsoutput voltage
current varies
sourcing between 7 & 37V.
capacity.
Transistor Q increase the current sourcing capacity thus IL (MAX)
is greater than 150mA.
The output voltage Vo is given by ,
V0= Vo = [1+R1/R2] Vin
Rsc =0.6/Ilimit
Fig.4.100Typical circuit connection

diagram
Assignment
6.4 Assignments ( For higher level learning and Evaluation - Examples: Case
study, Comprehensive design, etc.,)
UNIT IV – ELECTRONIC CIRCUITS
Q.No Questions CO BT
Level Level
1. Write a neat diagram and explaint he working CO4 K3
of PN junction diode in forward bias and
reverse bias and show tht effect of
temperature on its VI characteristics.
2. Explain the characteristics of zener diode and CO4 K3

compare zener diode with ordinary diode
3. Discuss the switching characteristics of a CO4 K3
transistor with neat sketch
4. Describe the static input and output CO4 K3

characteristics of CB configuration of a
transistor with neat diagram.
135
Assignment
6.4 Assignments ( For higher level learning and Evaluation - Examples: Case
study, Comprehensive design, etc.,)
UNIT Iv – ELECTRONIC CIRCUITS
Q.No Questions CO BT
Level Level
5. Compose the expression of current gain, input CO K3
impedance and voltage gain og CE transistor
amplifier.
6. Discuss the most commonly used transistor CO1 K3

configuration? Why? And explaint he
configuration?
7. Illustrate the types of differential amplifiers and CO1 K3

power amplifier along with its types.
8. Discuss the different oscillator circuit to CO1 K3
produce sustained oscillations bridge

rectificer and derive the bridge rectififer and
derive the expression for average output
current and rectification efficiency.
9 Describe ADC and its type in detail.
Describe DAC and its types in detail.
136
Part A Question and Answer
Unit-IV Electronic Circuits
1.Define Semiconductor. (K1, CO1)
A semiconductor material has an electrical conductivity value falling

between that of a conductor, such as metallic copper, and an insulator,
such as glass. Its resistivity falls as its temperature rises; metals are the
opposite. Its conducting properties may be altered in useful ways by
introducing impurities ("doping") into the crystal structure. When two
differently-doped regions exist in the same crystal, a semiconductor
junction is created. The behavior of charge carriers, which include
electrons, ions and electron holes, at these junctions is the basis of
diodes, transistors and all modern electronics. Some examples of
semiconductors are silicon, germanium, gallium
2.Define knee voltage of diode.(K1, CO1)
The forward voltage at which the flow of current during the PN Junction
begins increasing quickly is known as knee voltage. This voltage is also
known as cut-in voltage. ... The diode's breakdown voltage can be
defined as the least reverse voltage which is used to make the diode
perform in reverse.
3.Define forward and reverse bias. (K1, CO1)
Forward Bias
In the forward bias condition, the negative terminal of the battery is

connected to the N-type material and the positive terminal of the battery
is connected to the P-Type material. This connection is also called as
giving positive voltage. Electrons from the N-region cross the junction
and enters the P-region. Due to the attractive force that is generated in
the P-region the electrons are attracted and move towards the positive
terminal. Simultaneously the holes are attracted to the negative terminal
of the battery. By the movement of electrons and holes current flows. In
this condition, the width of the depletion region decreases due to the
reduction in the number of positive and negative ions.
137
Reverse Bias
In the forward bias condition, the negative terminal of the battery is

connected to the N-type material and the positive terminal of the
battery is connected to the P-type material. This connection is also
known as giving positive voltage. Hence, the electric field due to
both the voltage and depletion layer is in the same direction. This
makes the electric field stronger than before. Due to this strong
electric field, electrons and holes want more energy to cross the
junction so they cannot diffuse to the opposite region. Hence, there
is no current flow due to the lack of movement of electrons and
holes.
4.Describe the types of biasing of PN junction diode. (K1, CO1)
There are two operating regions: P-type and N-type. And based on
the applied voltage, there are three possible “biasing” conditions for
the P-N Junction Diode, which are as follows:
Zero Bias – No external voltage is applied to the PN junction diode.
Forward Bias– The voltage potential is connected positively to the

P-type terminal and negatively to the N-type terminal of the Diode.
Reverse Bias– The voltage potential is connected negatively to the

P-type terminal and positively to the N-type terminal of the Diode.
5.Illustrate by dynamic resistance of a diode. (K1, CO1)
The dynamic resistance is the resistance offered by the p-n junction

diode when AC voltage is applied. When forward biased voltage is
applied to a diode that is connected to AC circuit, an AC or
alternating current flows though the diode.
138
6.What is Zener diode and its VI characteristics. (K1, CO1)
Zener diodes are widely used as voltage references and as shunt

regulators to regulate the voltage across small circuits. When
connected in parallel with a variable voltage source so that it is
reverse biased, a Zener diode conducts when the voltage reaches
the diode's reverse breakdown voltage.
When reverse biased voltage is applied to a zener diode, it allows

only a small amount of leakage current until the voltage is less than
zener voltage. When reverse biased voltage applied to the zener
diode reaches zener voltage, it starts allowing large amount of
electric current.
7.Distinguish between zener breakdown and avalanche

breakdown. (K1, CO1)
The difference between Zener and avalanche breakdown include

the following.
 The Zener breakdown can be defined as the flow of electrons

across the p kind material barrier of the valence band to the
evenly filled n-type material conduction band.
 The avalanche breakdown is an occurrence of raising the flow

of electric current or electrons in insulating material or
semiconductor by giving the high voltage.
 The depletion region of the Zener is thin whereas the avalanche

is thick.
 The connection of the Zener is not-destroy whereas the

avalanche is destroyed.
 The electric field of the Zener is strong whereas the avalanche

is weak.
 The Zener breakdown generates electrons whereas the 139

avalanche generates holes as well as electrons.
8.When does transistor act as a switch? (K1, CO1)
A transistor works in active region when worked as an Amplifier.

When a transistor works as a Switch it works in Cutoff and
Saturation Regions. In the Cutoff State both Emitter Base Junction
and Collector Base junctions are reverse biased. But in saturation
region both junctions are forward biased
9.What is biasing?(K1, CO1)
Biasing is the process of providing DC voltage which helps in the

functioning of the circuit. A transistor is based in order to make the
emitter base junction forward biased and collector base junction
reverse biased, so that it maintains in active region, to work as an
amplifier.
10.Classify the different configurations of transistor? (K1, CO1)
The three types of configurations are Common Base, Common

Emitter and Common Collector configurations. In every
configuration, the emitter junction is forward biased and the
collector junction is reverse biased.
11.Compose the advantages of Push pull amplifier. (K1, CO1)
The advantages of
 push pull amplifier are low distortion, cancellation of power

supply ripples and absence of
 magnetic saturation in the coupling transformer core which

results in the absence of hum while
 the disadvantages are the need of two identical transistors and

the requirement of bulky and
 costly coupling transformers.

140
12.Explain the operation of oscillator. (K1, CO1)
Oscillators convert a DC input (the supply voltage) into an AC output

(the waveform), which can have a wide range of different wave shapes
and frequencies that can be either complicated in nature or simple sine
waves depending upon the application.
13.Define Rectifiers. List the types of Rectifiers. (K1, CO1)
A rectifier is a device that converts an oscillating two-directional

alternating current (AC) into a single-directional direct current (DC).
Rectifiers can take a wide variety of physical forms, from vacuum tube
diodes and crystal radio receivers to modern silicon-based designs.
The Different Types of Rectifiers
 Single Phase & Three Phase Rectifiers.
 Half Wave & Full Wave Rectifiers.
 Bridge Rectifiers.
 Uncontrolled & Controlled Rectifiers.
 14.Define differentiator. (K1, CO1)
 A differentiator circuit is used to produce trigger or spiked typed

pulses for timing circuit applications. When a square wave step
input is applied to this RC circuit, it produces a completely different
wave shape at the output.
 15.Define integrator. (K1, CO1)
 An integrator in measurement and control applications is an

element whose output signal is the time integral of its input signal.
It accumulates the input quantity over a defined time to produce a
representative output. Integration is an important part of many
engineering and scientific applications.
141
Part B Questions
Unit-IV Electronic Circuits
1. Write a neat diagram and explaint he working of PN junction diode in forward

bias and reverse bias and show tht effect of temperature on its VI
characteristics.
2. Explain the characteristics of zener diode and compare zener diode with
ordinary diode
3. Discuss the switching characteristics of a transistor with neat sketch.
4. Describe the static input and output characteristics of CB configuration of a
transistor with neat diagram.
5. Compose the expression of current gain, input impedance and voltage gain og
CE transistor amplifier.
6. Discuss the most commonly used transistor configuration? Why? And explaint
he configuration?
7. Illustrate the types of differential amplifiers and power amplifier along with its
types.
8. Discuss the different oscillator circuit to produce sustained oscillations bridge
rectificer and derive the bridge rectififer and derive the expression for average
output current and rectification efficiency.
9. Describe ADC and its type in detail.
10. Describe DAC and its types in detail.
11. Illustrate in detail about different types of Multivibrator using 555 timers.
12. Briefly explain the voltage regulator using LM723.
13. Briefly explain the voltage regulator using LM317.
142
Supportive online Certification courses (NPTEL, Swayam, Coursera, Udemy,

etc.,)
ONLINE COURSE NPTEL:
https://nptel.ac.in/courses/117/103/117103063/
Basic Electronics
By Prof. Chitralekha Mahanta
Department of Electronics and Communication Engineering
Guwahati | IIT Madras
Semiconductor Diodes-Semiconductor materials- intrinsic and extrinsic types, Ideal Diode, Terminal
characteristics of diodes,p-n junction under open circuit condition,p-n junction under forward bias and
reverse bias conditions,p-n junction in breakdown region,Diode small signal mode, Zener diode and
applications,Rectifier Circus
Bipolar Junction Transistors (BJT)- Biasing the BJT: fixed bias, emitter feedback bias, collector
feedback bias and voltage divider bias, Basic BJT amplifier configuration: common emitter, common
base and common collector amplifiers, Transistor as a switch: cut-off and saturation modes, High
frequency model of BJT amplifier
Operation Amplifier (Op-amps)-Ideal Op-amp, Differential amplifier: differential and common mode
operation, common mode rejection ratio (CMRR), Practical op-amp circuits: inverting amplifier, non -
inverting amplifier, weightedsummer, integrator, differentiator, Large signal operation of op-amps,
Other applications of op-amps: instrumentation circuits, active filters, controlled sources, logarithmic
amplifiers, waveform generators, Schmitt triggers, comparators
143
Supportive Link to Videos
S.No Link
Topic
1 PN Junction diode, VI https://www.youtube.com/watch?v=USr
characteristics of diode Y0JspDEg
2 Zener diode https://www.youtube.com/watch?v=MZ

PeRlst8rQ
3 Transisitor op-amps, https://www.youtube.com/watch?v=kiiA

configuration
6WTCQn0
4 Rectifiers https://www.youtube.com/watch?v=Ll0
IOk_Ltfc
5 Differentiator https://www.youtube.com/watch?v=aU
24RWIgJVs
6 Integrator https://www.youtube.com/watch?v=OP
vs7A554Rw
7 ADC Types: Successive https://www.youtube.com/watch?v=MM

Approximation
Qwa416Cmo
8 DAC , Types: R-2R Ladder type, https://www.youtube.com/watch?v=Po

Weighted Resistor DAC
Om_G4s1dE
9 Voltage regulator IC using LM https://www.youtube.com/watch?v=veX

723, LM 317
ShWaCliA
144
Real time Applications in day to day life and to Industry
1. Usage of diodes in electric cables (CO1,K2)
2. Rectifier Circuits for Cell Phone or Laptop Chargers . (CO1,K3)
3. Usage of DAC in Digital Potentiometer. (CO1,K3)
145
Contents beyond the Syllabus

FIELD-EFFECT TRANSISTOR
In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and, therefore,
its current-carrying capability, is varied by the application of an electric field (thus, the name field-effect
transistor). As such, a FET is a “voltage-controlled” device. The most widely used FETs are Metal-
Oxide-Semiconductor FETs (or MOSFET). MOSFET can be manufactured as enhancement-type or
depletion-type MOSFETs. Another type of FET is the Junction Field-Effect Transistors (JFET) which
is not based on metal-oxide fabrication technique. FETs in each of these three categories can be
fabricated either as a n-channel device or a p-channel device. As transistors in these 6 FET
categories behave in a very similar fashion, we will focus below on the operation of enhancement
MOSFETs that are the most popular.
n-Channel E nhanceme nt - Type M O S F E T ( N M O S )

The physical structure of a n-Channel Enhancement-Type MOSFET (NMOS) is shown. The device is
fabricated on a p-type substrate (or Body). Two heavily doped n-type regions (Source and Drain)
are created in the substrate. A thin (fraction of micron) layer of SiO2, which is an excellent electrical
insulator, is deposited between source and drain region. Metal is deposited on the insulator to form
the Gate of the device (thus, metal-oxide semiconductor). Metal contacts are also made to the
source, drain, and body region.
To see the operation of a NMOS, let’s ground the source and the body and apply a voltage vGS between
the gate and the source, as is shown above. This voltage repels the holes in the p-type substrate near the
gate region, lowering the concentration of the holes. As v GS increases, hole concentration decreases, and
the region near gate behaves progressively more like intrinsic semiconductor material (excess hole
concentration zero) and then, finally, like
a n-type material as electrons from n+ electrodes (source and drain) enter this region. As a result,
when vGS become larger than a threshold voltage, Vt, a narrow layer between source and drain
regions is created that is populated with n-type charges (see figure). The thickness of this channel is
controlled by the applied v GS (it is really controlled by v GS − Vt).
As can be seen, this device works as a channel is induced in the semiconductor and this channel
contains n-type charges (thus, n-channel MOSFET). In addition, increasing v GS increases channel
width (enhances it). Therefore, this is an Enhancement-type MOSFET.
Now for a given values of v GS > Vt (so that the channel is formed), let’s apply a small and positive
voltage v DS between drain and source. Then, electrons from n+ source region enter the channel and
reach the drain. If v DS is increased, current i D flowing through the channel increases. Ef- fectively,
the device acts like a resistor; its resistance is set by the dimension of the channel and its n-type
charge concentration. In this regime, plot of i D versus v DS is a straight line (for a given values of
vGS > Vt) as is shown.
The slope of i D versus v DS line is the conductance of the channel. Changing the value of vGS ,
changes dimension of the channel and its n-type charge concentration and, therefore, its
conductance. As a result, changing v GS , affects the the slope of i D versus v DS line as is shown
above (at cut-off conductance is zero and conductance increases with v GS − Vt).
The above description is correct for small values of v DS as in that case, v GD = vGS −
than vGS . As such the size of channel near drain becomes smaller compared to itssize near the
source, as is shown. As the size of channel become smaller, its resistance increases and the curve
of i D versus v DS starts to roll over, as is shown below.
For values of v GD = Vt (or v DS = vGS − Vt), width of the channel approaches zero near the drain (channel is
“pinched” off). Increasing v DS beyond this value has little effect (no effect in our simple picture) on the
channel shape, and the current through the channel remains constant at the value reached when v DS =
vGS − Vt. So when the channel is pinched off, i D only depends on vGS (right figure below).
In sum, a FET can operate in three regimes:

Cut-off regime in which no channel exists (vGS < Vt for NMOS) and i D = 0 for any v DS .
Ohmic or Triode regime in which the channel is formed and not pinched off (vGS > Vt
and v DS ≤ vGS − Vt for NMOS) and FET behaves as a “voltage-controlled”resistor.
Active or Saturation regime in which the channel is pinched off (vGS ≥ Vt and v DS > vGS − Vt for NMOS)
and i D does not change with v DS .
Several important point should be noted. First, no current flows into the gate, i G = 0 (note the insulator
between gateand the body). Second, FET acts as a “voltage-controlled” resistor in the ohmic region.
In addition, when v DS vGS , FET would act as a linear resistor. Third, If i D = 0, this does not mean that
FET is in cut-off. FET is in cut-off when a channel does not exist (vGS < Vt) and i D = 0 for any applied
v DS . On the other hand, FET can be in ohmic region, i.e., a channel is formed, but i D = 0 because
v DS = 0. Lastly, the third regime is called “saturation” in most electronic books because i D is
“saturated” in this regime and does not increase further. This is a rather unfortunate name as
“saturation” regime in a FET means very different thing than it does in a BJT. Some newer books call
this regime “active” (as it equivalent to “active-linear” regime of a BJT). Note that the
transition between ohmic and active region is clearly defined by v DS = vGS − Vt the point where the
channel is pinched off.
The i D versus v DS characteristic curves of a FET look very similar to i C versus v CE characteristics
curves of a BJT. In fact, as there is a unique relationship between i B and v BE , the i C versus v CE
characteristic curves of a BJT can be “labeled” with different values of v BE instead of i B making the
characteristic curves of the two devices even more similar. In FET vGS control device behavior and
in BJT v BE . Both devices are in cut-off when the “input” voltage is below a threshold value: v BE <
vγ for BJT and vGS < Vt for NMOS. They exhibit an “active” regime in which the “output” current (i C
or i D ) is roughly constant as the “output” voltage (v CE or v DS ) is changed. There are, however,
major differences. Most importantly, a BJT requires i B to operate but in a FET i G = 0 (actually very
small). These differences become clearer as we explore FETs.
and source can be replacedwithout any change in device properties. The circuit symbol for a
NMOS is shown on the right. For most applications, however, the body is connected to the
source, leading to a 3-terminal element. In that case, source and drain are not
interchangeable. A simplified circuit symbol for this configuration is usually used. By convention,
current i D flows into the drain for a NMOS (see figure). As i G = 0, the same current will flow out
of the source.
Direction of “arrows” used to identify semiconductor types in a transistor may appear con- fusing. The
arrows do NOT represent the direction of current flow in the device. Rather, they denote the direction of
the underlying pn junction. For a NMOS, the arrow is placed on the body and pointing inward as the
body is made of p-type material. (Arrow is not on source or drain as they are interchangeable.) In the
simplified symbol for the case when body and source is connected, arrow is on the source (device is
not symmetric now) and is pointing outward as the source is made of n-type materials. (i.,e. arrow
pointing inward for p-type, arrow pointing outward for n-type).
N M O S i D versus v DS Ch aract eri st i cs Eq u a t i o ns

Like BJT, a NMOS (with source connected to body) has six parameters (three voltages and three
currents), two of which (i S and v GD ) can be found in terms of the other four by KVL and KCL. NMOS is
simpler than BJT because i G = 0 (and i S = i D ). Therefore, three parameters describe behavior of a NMOS
(vGS , i D , and v DS ). NMOS has one characteristics equation that relates these three parameters. Again,
situation is simpler than BJT assimple but accurate characteristics equations exist.
Cut-off: vGS < Vt, i D = 0 for any v DS
vGS > Vt, i = K[2v

vGS > Vt, i D = K(v GS − Vt)2 for v DS > vGS −Vt
How t o Solve N M O S Circuit s:

Solution method is very similar to BJT circuit (actually simpler because i G = 0). To solve, we assume
that NMOS is in a particular state, use NMOS model for that state to solve the circuit and check the
validity of our assumption by checking the inequalities in the model for that state. A formal procedure
is:
Write down a KVL including the GS terminals (call it GS-KVL).
Write down a KVL including DS terminals (call it DS-KVL).
From GS-KVL, compute v GS (using i G = 0)

3a) If vGS < Vt, NMOS is in cut-off. Let i D = 0, solve for v DS from DS-KVL. We are done. 3b) If vGS >
Vt, NMOS is not in cut-off. Go to step 4.
Assume NMOS is in active region. Compute i D from i D = K(v GS − Vt)2. Then, use DS-KVL to compute
v DS . If v DS > vGS − Vt, we are done. Otherwise go to step5.
2
in DS-KVL. You will get a quadratic equation in v DS . Find v DS (one of the two roots of the equation
will be unphysical). Check to make sure that v DS < vGS − Vt. Substitute v DS in DS-KVL to find i D .
B od y Effect
In deriving NMOS (and other MOS) i D versus v DS characteristics, we had assumed that the body and
source are connected. This is not possible in an integrated chip which has a common body and a large
number of MOS devices (connection of body to source for all devices means that all sources are
connected). The common practice is to attach the body of the chip to the smallest voltage available from
the power supply (zero or negative). In this case, the pn junction between the body and source of all
devices will be reversed biased. The impact of this to lower threshold voltage for the MOS devices
slightly and its called the body effect. Body effect can degrade device performance. For analysis here,
we will assume that body effect is negligible.
p-Channel En h an cemen t - Typ e M O S F E T ( P M O S )

The physical structure of a PMOS is identical to a NMOS except that the semiconductor types
are in-
terchanged, i.e., body and gate are made of n-type material and source and drain are made of p-type ma-
terial and a p-type channel is formed. As the sign of the charge carriers are reversed, all voltages and
currents in a PMOS are reversed. By convention, the drain current is flowing out of the drain as is
shown. With this, all of the NMOS discussion above applies to PMOS as long as we multiply all voltages
by a minus sign:
Note that Vt is negative for a PMOS.
Comp lemen t ary M O S ( C M O S )

Complementary MOS technology employs MOS transistors of both polarites as is shown below.
CMOS devices are more difficult to fabricate than NMOS, but many more powerful circuits are
possible with CMOS configuration. As such, most of MOS circuits todayemploy CMOS
configuration and CMOS technology is rapildy taking over many applications that were possible
only with bipolar devices a few years ago.
S2
G2
Assessment Schedule
15. ASSESSMENT SCHEDULE ( PROPOSED DATE & ACTUAL DATE)
ASSESSMENT PROPOSED ACTUAL DATE

DATE
UNIT TEST 1
FIAT
SIAT
REVISION TEST
MODEL
152
Prescribed Text Books & Reference Books
TEXT BOOK:
• S.K.Bhattacharya, Basic Electrical and Electronics Engineering, Pearson
• C L Wadhwa, Generation Distribution and Utilization of Electrical Energy, New Age International
REFERENCES:
• S.B. Lal Seksena and Kaustuv Dasgupta, Fundaments of Electrical Engineering, Cambridge, 2016
• B.L Theraja, Fundamentals of Electrical Engineering and Electronics. Chand & Co
• S.K.Sahdev, Basic of Electrical Engineering, Pearson
• John Bird, ―Electrical and Electronic Principles and Technology‖, Fourth Edition, Elsevier,
• Mittle,Mittal, Basic Electrical Engineering‖, 2nd Edition, Tata McGraw-Hill Edition, 2016.
• R.S Khurmi and J K Gupta, Textbook of Refrigeration and Air-conditioning (M.E.), S Chand& Co
153
9. Mini Project suggestions
S.No Name of The Project

1. Try to find diode in electric cables and design it.
2. Try to find DAC and its conversion in digital potentiometer.
3. Design a Voltage regulator for charger
154

Unit 4

Uploaded by

Copyright:

Available Formats

Unit 4

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Unit 4

Uploaded by

Copyright:

Available Formats

1

Department : Electronics and Communication Engineering

Electrical Circuit analysis

4.1 PN JUNCTION DIODE

Forbidden band gap Eo ≈6eV Eo =≈6eV

Fig 4.1 Fig 4.2

Conductors:A conductorisa material which supports a generousflowof charge

4.1.1 Semiconductor Types

A pure form of semiconductors is called as intrinsic semiconductor.

Fig. 1.2b crystal structure of Si at room

The absence of electrons in covalent bond is represented by a small circle

The mechanism by which a hole contributes to conductivity is explained as

Fig 4.7 Fig 4.8

4.1.2 EXTRINSIC SEMICONDUCTOR

N type semiconductor: If the added impurity is a pentavalent atom then the

Fifth valance electron of SB

hole (majority carrier)

Electron (minority carrier)

Fig. 1.5b crystal structure of P type sc

4.1.3 CONDUCTIVITY OF SEMICONDUCTOR

E=applied electric field strength, V/m

q= charge of electron or hole I n Coulombs

Hence, ς is the conductivity of sc which is equal to (n µn + p µp)q. he resistivity

Hence conductivity in intrinsic sc is ςi= ni ( µn + µp) q

Intrinsic conductivity increases at the rate of 5% per o C for Ge and 7% per o C

4.1.4 CHARGE DENSITIES IN P TYPE AND N TYPE SEMICONDUCTOR:

Mass Action Law:

Law of electrical neutrality:

Therefore ND positively charged ions per cubic centimeter are contributed

For N type sc, NA =0 and n>>p. Therefore ND ≈ n

Mass action law for P type, np pp= ni

4.1.5 QUANTITATIVE THEORY OF PN JUNCTION DIODE

PN JUNCTION WITH NO APPLIED VOLTAGE OR OPEN CIRCUIT

Fig 4.13: Symbol of PN Junction Diode

4.1.6 FORWARD BIASED JUNCTION DIODE

When a diode is connected in a Forward Bias condition, a negative voltage is

Forward Characteristics Curve for a Junction Diode

Fig 1.8a: Diode Forward Characteristics

Forward Biased Junction Diode showing a Reduction in the Depletion Layer

Fig 4.17: Diode Forward Bias

4.1.7 PN JUNCTION UNDER REVERSE BIAS CONDITION:

Reverse Biased Junction Diode

When a diode is connected in a Reverse Bias condition, a positive voltage is applied

Fig 4.18: Diode Reverse Bias

This condition represents a high resistance value to the PN junction and

Reverse Characteristics Curve for a Junction Diode

Fig 4.19: Diode Reverse Characteristics

Sometimes this avalanche effect has practical applications in voltage stabilizing

4.1.8 VI CHARACTERISTICS AND THEIR TEMPERATURE DEPENDENCE

 = empirical constant, 1 for Ge and 2 for Si

Fig 4.20 Diode Characteristics

4.1.8 Temperature Effects on Diode

Fig 4.21 Variation in Diode Characteristics with temperature

4.1.8 Temperature Effects on Diode

Fig 4.21 Variation in Diode Characteristics with temperature

4.1.8 IDEAL VERSUS PRACTICAL RESISTANCE LEVELS

Fig 4.22 Determining the dc resistance of a diode at a particular operating

Fig 4.23: Determining the ac resistance of a diode at a particular operating