Assignment No #01

Submitted To:
Engr. M Ubaidullah
Submitted By:
Muhammad Usama Saghar
Roll Number:
2019-CPE-27
Subject:
Microprocessor Systems (CPE-312)

Department of Computer Engineering

UCE&T
Bahauddin Zakariya University, Multan.
Q: What are the control signal necessary in the memory mapped I/O in 8086
microprocessor?

Memory Mapped I/O:

Memory-mapped I/O uses the same address space to address both memory and I/O devices. The memory
and registers of the I/O devices are mapped to (associated with) address values. So when an address is
accessed by the CPU, it may refer to a portion of physical RAM, or it can instead refer to memory of the
I/O device. Thus, the CPU instructions used to access the memory can also be used for accessing devices.
Each I/O device monitors the CPU's address bus and responds to any CPU access of an address assigned
to that device, connecting the data bus to the desired device's hardware register. To accommodate the I/O
devices, areas of the addresses used by the CPU must be reserved for I/O and must not be available for
normal physical memory. The reservation may be permanent, or temporary (as achieved via bank
switching). An example of the latter is found in the Commodore 64, which uses a form of memory
mapping to cause RAM or I/O hardware to appear in the 0xD000-0xDFFF range.

Port-mapped I/O often uses a special class of CPU instructions designed specifically for performing I/O,
such as the in and out instructions found on microprocessors based on the x86 and x86-64 architectures.
Different forms of these two instructions can copy one, two or four bytes ( outb , outw and outl ,
respectively) between the EAX register or one of that register's subdivisions on the CPU and a specified
I/O port which is assigned to an I/O device. I/O devices have a separate address space from general
memory, either accomplished by an extra "I/O" pin on the CPU's physical interface, or an
entire bus dedicated to I/O. Because the address space for I/O is isolated from that for main memory, this
is sometimes referred to as isolated I/O.

Control Signals:
The control signals are provided to support the 8086 memory 1/0 interfaces. They control functions such
as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when
valid write data are on the bus and when to put read data on the system bus.

ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This
address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.

Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on this
used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These
lines also serves a second function, which is as the S, status line.

Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which
direction data are to be transferred over the bus. The logic level of M/IO tells external circuitry whether a
memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and
logic 0 an 1/0 operation.

The direction of data transfer over the bus is signaled by the logic level output at DT/R. When this line is
logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are
either written into memory or output to an I/O device. On the other hand, logic 0 at DT/R signals that the
bus is in the receive mode. This corresponds to reading data from memory or input of data from an input
port.

The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The
8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. On
the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations,
one other control signal is also supplied. This is DEN ( data enable) and it signals external devices when
they should put data on the bus.

There is one other control signal that is involved with the memory and I/O interface. This is the READY
signal.

READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock
periods. This signal is provided by an external clock generator device and can be supplied by the memory
or 1/0 sub-system to signal the 8086 when they are ready to permit the data transfer to be completed.

Q: Draw and explain the block diagram of a microprocessor 8086?

Definition:
8086 is a 16-bit microprocessor and was designed in 1978 by Intel. Unlike, 8085, an 8086 microprocessor
has 20-bit address bus. Thus, is able to access 220 i.e., 1 MB address in the memory.
As we know that a microprocessor performs arithmetic and logic operations. And an 8086 microprocessor
is able to perform these operations with 16-bit data in one cycle. Hence is a 16-bit microprocessor.
Thus the size of the data bus is 16-bit as it can carry 16-bit data at a time. The architecture of 8086
microprocessor, is very much different from that of 8085 microprocessor.

Features of Microprocessor:
It is a 16-bit Microprocessor.
8086 has a 20 bit address bus that can access up to 220 = 1 MB memory locations.
8086 has a 16 bit data bus. It can read or write data to a memory/port either 16 bits or 8 bit at a time.
It can support 64 K I/O ports.
The frequency range of 8086 is 6-10 MHz
It has multiplexed address and data bus AD0- AD15 and A16 – A19.
It can pre-fetch up to 6 instruction bytes from memory and queues them in order to speed up instruction
execution.
It requires +5V power supply.
A 40 pin dual inline package. 8086 is designed to operate in two modes, Minimum mode and Maximum
mode.
The minimum mode is selected by applying logic 1 to the MN/MX input pin. This is a single
microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN/ MX input pin. This is a multi
microprocessors configuration.
Internal Structure of 8086 Microprocessor The following figure shows the internal block diagram of the
8086 microprocessor.
Block diagram of 8086 microprocessor

The architecture of 8086 microprocessor is composed of 2 major units, the BIU i.e., Bus Interface Unit
and EU i.e., Execution Unit.

The figure below shows the block diagram of the architectural representation of the 8086 microprocessor:

Bus Interface Unit(BIU)

The Bus Interface Unit (BIU) manages the data, address and control buses.

The BIU functions in such a way that it:

• Fetches the sequenced instruction from the memory,

• Finds the physical address of that location in the memory where the instruction is stored and
• Manages the 6-byte pre-fetch queue where the pipelined instructions are stored.
An 8086 microprocessor exhibits a property of pipelining the instructions in a queue while performing
decoding and execution of the previous instruction.
This saves the processor time of operation by a large amount. This pipelining is done in a 6-byte queue.
Also, the BIU contains 4 segment registers. Each segment register is of 16-bit. The segments are present
in the memory and these registers hold the address of all the segments. These registers are as follows:
1.Code segment register: It is a 16-bit register and holds the address of the instruction or program
stored in the code segment of the memory.
Also, the IP in the block diagram is the instruction pointer which is a default register that is used by the
processor in order to get the desired instruction. The IP contains the offset address of the next byte that is
to be taken from the code segment.
2. Stack segment register: The stack segment register provides the starting address of stack segment in
the memory. Like in stack pointer, PUSH and POP operations are used in this segment to give and take
the data to/from it.
3. Data segment register: It holds the address of the data segment. The data segment stores the data in
the memory whose address is present in this 16-bit register.
4. Extra segment register: Here the starting address of the extra segment is present. This register
basically contains the address of the string data.
It is to be noteworthy that the physical address of the instruction is achieved by combining the segment
address with that of the offset address.

6-byte pre-fetch queue: This queue is used in 8086 in order to perform pipelining. As at the time of
decoding and execution of the instruction in EU, the BIU fetches the sequential upcoming instructions
and stores it in this queue.
The size of this queue is 6-byte. This means at maximum a 6-byte instruction can be stored in this queue.
The queue exhibits FIFO behaviour., first in first out.

Execution Unit (EU)

The Execution Unit (EU) performs the decoding and execution of the instructions that are being fetched
from the desired memory location.

Control Unit:
Like the timing and control unit in 8085 microprocessor, the control unit in 8086 microprocessor
produces control signal after decoding the opcode to inform the general purpose register to release the
value stored in it. And it also signals the ALU to perform the desired operation.

ALU:
The arithmetic and logic unit carries out the logical tasks according to the signal generated by the CU.
The result of the operation is stored in the desired register.

Flag:
Like in 8085, here also the flag register holds the status of the result generated by the ALU. It has several
flags that show the different conditions of the result.

Operand:
It is a temporary register and is used by the processor to hold the temporary values at the time of
operation.

The reason behind two separate sections for BIU and EU in the architecture of 8086 is to perform fetching
and decoding-executing simultaneously.

Q: Explain the maximum mode configuration of 8086?

Maximum Mode 8086

In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives
the control signal using this status information.

In the maximum mode, there may be more than one microprocessor in the system configuration. The
components in the system are same as in the minimum mode system.

The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR (for
memory and I/O devices),

DEN, DT/R, ALE etc. using the information by the processor on the status lines. The bus controller chip
has input lines S2, S1, S0 and CLK.

These inputs to 8288 are driven by CPU.

It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The
AEN, IOB and CEN pins are specially useful for multiprocessor systems.

AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the
MCE/PDEN output depends upon the status of the IOB pin.

INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting
device.

IORC, IOWC are I/O read command and I/O write command signals respectively . These signals enable
an IO interface to read or write the data from or to the address port.

The MRDC, MWTC are memory read command and memory write command signals respectively and
may be used as memory read or write signals.

All these command signals instructs the memory to accept or send data from or to the bus.
Here the only difference between in timing diagram between minimum mode and maximum mode is the
status signals used and the available control and advanced command signals.

Maximum Mode Configuration For 8086

When MN/MX' is connected to low logic, then 8086 is selected in maximum mode of operation. Now

8086 can operate in its full capacity for inter processor communication. The command and control signals
are now generated by 8288. The connection with 8288 Bus controller, 8289 Bus arbiter and other
components such as latches and transceivers is shown in figure. As seen the PIN S2', S1', s0' is connected
to 8288 bus controller. Depending on the status of the signal on S2', S1', so' pins the command signals are
generated by 8288. The control signals generated by 8288 are M/IO', WR', DEN, DT/R', ALE etc and are
not available on the 8086 microprocessor chip. Table below shows the commands in response to S2', S1',
s0' at the 8288 outputs.

Figure in maximum mode

configuration shows the connection to the 8289 bus arbiter. The inputs to the bus arbiter is LOCK' and the
status control signal S2', S1' and SO'.

The output signals generated by 8289 are:

• Bus Busy (BUSY')

• Common Bus Request (CBRQ')

• Bus Priority Output (BPRO)

• Bus Priority In (BPRN)

• Bus Priority Out(BREQ)

• Bus Clock (BCLK)

All these above signals correspond to the bus exchange signals of the multi bus and are used to lock other
processors off the system bus during the execution of an instruction by the 8086. This way, processor can
be assured of uninterrupted access to common system resources such as memory.

Maximum Mode pin

(RQ' / GT 0) and (RQ’ / GT 1)

These two pins are used for bus request and grant purpose. Through these pins, a connection is
established between the external peripheral devices and the 8086 microprocessor. Among these two pins,
the pin- (RT / GT 0) has higher priority over (RT / GT 1).

LOCK'

This pin is used to lock the internal buses of the microprocessor. When the control of buses is handed
over to an external peripheral device, then the microprocessor is locked through this pin. It is an active
low signal.

QS0 and QS1

QS stands for Queue status, and as the name suggests, these two pins are used to tell the status of the
queue. The status of the queue form the values of these pins is decided as follows:

S2, S1 and S0
Here, the S in each of these pins stands for Status. These three pins: S2, S1, and S0 together tell about the
CPU cycle. The different of the values of these pins taken together tell about which CPU cycle is
currently running.

Q: Explain the concept of segmented memory? What are its advantages?

Segmentation
Is the process in which the main memory of the computer is divided into different segments and each
segment has its own base address. It is basically used to enhance the speed of execution of the computer
system, so that processor is able to fetch and execute the data from the memory easily and fast. –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as
Segment Registers.
• Code segment register (CS): is used for addressing memory location in the code segment of
the memory, where the executable program is stored.
• Data segment register (DS): points to the data segment of the memory where the data is
stored.
• Extra Segment Register (ES): also refers to a segment in the memory which is another data
segment in the memory.
• Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack
segment is that segment of memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the
1MB memory locations. The four segment registers actually contain the upper 16 bits of the starting
addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of
time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up
of contiguous memory locations. It is independent, separately addressable unit. Starting address will always
be changing. It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time. However it works only with
four 64KB segments within the whole 1MB memory.
Bellow is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an
8086.

Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its maximum size can go
up to 64kilobytes. But if another segment starts along this 64kilobytes location of the first
segment, then the two are said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its maximum size
can go up to 64kilobytes. But if another segment starts before this 64kilobytes location of the first
segment, then the two segments are said to be Non-Overlapped Segment.
Advantages of the Segmentation
The main advantages of segmentation are as follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different segments.
 • Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit
registers to give an addressing capability of 1 Megabytes. Without segmentation, it would require
20 bit registers.
• It is possible to enhance the memory size of code data or stack segments beyond 64 KB by
allotting more than one segment for each area.

Q: Explain the concept of pipelining in 8086? Discuss its advantages and disadvantages?

Pipelining

1. The process of fetching the next instruction when the present instruction is being executed is
called as pipelining.
2. Pipelining has become possible due to the use of queue.
3. BIU (Bus Interfacing Unit) fills in the queue until the entire queue is full.
4. BIU restarts filling in the queue when at least two locations of queue are vacant.

Advantages of pipelining:
• The execution unit always reads the next instruction byte from the queue in BIU. This is faster
than sending out an address to the memory and waiting for the next instruction byte to come.
• In short pipelining eliminates the waiting time of EU and speeds up the processing. -The 8086
BIU will not initiate a fetch unless and until there are two empty bytes in its queue. 8086 BIU
normally obtains two instruction bytes per fetch.

Disadvantages of pipelining:
1. While pipelining can severely cut the time taken to execute a program, there are problems that
cause it to not work as well as it perhaps should.
2. The three stages of the instruction execution process do not necessarily take an equal amount of
time, with the time taken for 'execute' being generally longer than 'fetch'. This makes it much
harder to synchronise the various stages of the different instructions.
3. Also, some instructions may be dependent on the results of other earlier instructions. This can
arise when data produced earlier needs to be used or when a conditional branch based on a
previous outcome is used.