INDEX

EX. PAGE
NAME OF THE EXPERIMENTS
NO NO
INVERTING, NON-INVERTING AND DIFFERENTIAL
1 2
AMPLIFIER USING OP-AMP

2 INTEGRATOR AND DIFFERENTIATOR USING OP-AMP 9

3 INSTRUMENTATION AMPLIFIER 17

ACTIVE LOWPASS, HIGHPASS AND BANDPASS FILTER

4 20
USING OP-AMP

ASTABLE AND MONOSTABLE MULTIVIBRATOR USING

5 29
OP-AMP

6 SCHMITT TRIGGER USING OP-AMP 36

RC PHASE SHIFT AND WIEN BRIDGE OSCILLTORS USING

7 40
OP-AMP
ASTABLE AND MONOSTABLE MULTIVIBRATORS USING
8 46
555 TIMER

9 DC POWER SUPPLY USING LM317 53

10 STUDY OF SMPS 58

11 R-2R LADDER TYPE D-A CONVERTER USING OP-AMP 61

1
INVERTING AND DIFFERENTIAL AMPLIFIER USING OP-AMP

EXP.NO: 01
AIM:
To design the Inverting, Non-Inverting and Differential Amplifiers using
Op-amp IC741 and test their performance.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 01
1KΩ, 33KΩ EACH 01
2. RESISTORS
10KΩ, 100KΩ EACH 02
3. POT 10KΩ 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-20)MHz 01
6. DUAL POWER SUPPLY (0-30)V 01
7. CONNECTING WIRES --- FEW

THEORY:
Op-amp in open-loop configuration has a very few application because
of its enormous open-loop gain. Controlled gain can be can be achieved by taking a
part of output signal to the input with the help of feedback. This is called as Closed-
Loop Configuration. The three basic types of closed-loop amplifier configuration
are: 1. Inverting amplifier.
2. Non-inverting amplifier.
3. Differential amplifier.
The entire configuration can be operated with either AC or DC input.
INVERTING AMPLIFIER:

If the input signal is applied to the inverting terminal through an input

resistance, a part of output is feedback to the inverting terminal through feedback
resistance Rf and the non-inverting terminal grounded, then the configuration is said
to be Inverting Amplifier. It provides 1800 phase shift or polarity reversal for the

 Rf
given input. The circuit closed-loop voltage gain is Avcl  .
R1

2
 PIN DIAGARAM:

INVERTING AMPLIFIER:
CIRCUIT DIAGRAM:

TABULATION:
Time Period = 1ms
Frequency=1KHz
Theoretical Gain Practical Gain
S.No Rf (KΩ) Vin (Volts) Vout (Volts)
A = -Rf / R1 A = V0 / Vin

1. 1K 2 2mv -0.1 -0.1

2. 10K 2 2 -1 -1
3. 20K 2 4 -2 -2

3
 MODEL GRAPH:

NON-INVERTING AMPLIFER:
CIRCUIT DIAGRAM:

TABULATION:
Time Period = 1ms
Vin Vout Theoretical Gain Practical Gain
S.No Rf (KΩ)
(Volts) (Volts) A = 1+(Rf / R1) A = V0 / Vin
1. 1K 2 2.2 1.1 1.1
2. 10K 2 4 2 2
3. 15K 2 5 2.5 2.5

4
THEORY – (NON-INVERTING AMPLIFIER):

If the input signal is given to non inverting terminal & the feedback
from output is connected to inverting terminal of an op-amp through a potential
divider network, then it is called as Non-Inverting Amplifier Configuration. It
operates in a same way as a voltage follower (unity gain buffer), except that the
output voltage is potentially divided before it is fedback to the inverting input
terminal. No phase shift or change in the circuit closed loop polarity occurs voltage

Rf
gain is Avcl  1  R1

THEORY-(DIFFERENTIAL AMPLIFIER):
A configuration which combines inverting & non-inverting
configuration with both input terminals are supplied with Vin1 & Vin2, then it is
called as Differential Amplifier configuration. This circuit amplifies the difference
between the two inputs. Differential amplifier with a single op-amp has the exact gain
of an inverting amplifier and it is given as

Vo Rf
AD (Using One Op-Amp)  AVCL  
(Vin 2  Vin1) R1

PROCEDURE-(INVERTING & NON-INVERTING AMPLIFIER):

1. Select R1 as a constant value and choose a value of Rf.

2. Connect the circuit as per as the circuit diagram.
3. Apply the constant amplitude input voltage to the circuit.
4. Measure the output voltage amplitude for different value of Rf from CRO.
5. Calculate the practical gain for different value of Rf & compare it with
theoretical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for practical case.

DIFFERENTIAL AMPLIFIER:

1. Select the value of R1, R2, R3 & Rf such that R1=R2 and R3=Rf.
2. Connect the circuit as per as the circuit diagram.
3. Provide constant input voltage Vin1 to Non-inverting terminal of op-amp
through R1 & constant input voltage Vin2 to inverting terminal of op-amp
through R2.

5
 MODEL GRAPH:

DIFFERENTIAL AMPLIFIER:
CIRCUIT DIAGRAM:

TABULATION:
Time Period = 1ms

Vin1 Vin2 Vin2 - Vin1 V0 Theoretical Gain Practical Gain

(Volts) (Volts) (Volts) (Volts) A = Rf / R1 A=V0 / (Vin2 - Vin1)

0.1 0.2 0.1 1.1 10 11

6
 4. Measure the output voltage using CRO.
5. Calculate the theoretical gain and compare it with practical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for practical case.

EXERCISE:

1. A non-inverting amplifier has R1 of 1KΩ of 100KΩ. Determine V f and β

(Feedback voltage and feedback fraction), if VO = 5V.
2. Find the value of Rf that will produce closed-loop gain of 300 in each
amplifier shown in fig.

3. Determine the most likely faults for each of the following symptoms in
fig. with a 100mV signal applied.
• no output signal
• output severely clipped on both +ve & -ve swings.

4. Design a Differential Amplifier of gain 100.

5. The typical voltage gain Ad of an LM 741 op-amp is 200,000 and the

typical CMRR is 90dB. Use these values to calculate the common mode gain
Acm of the 741 op-amp.

7
 OUTPUT:

RESULT:
Thus the Inverting, Non-Inverting and Differential Amplifiers are
designed and their performance was successfully tested using op-amp IC 741.

8
 INTEGRATOR AND DIFFERENTIATOR USING OP-AMP

EXP.NO: 02
AIM:
To design an Integrator and Differentiator using op-amp IC 741 and to test their
performance.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 01
1.5KΩ 02
2. RESISTORS
15KΩ 01
3. CAPACITOR 0.1μf, 0.01μf Each 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-20)MHz 01
6. CONNECTING WIRES --- FEW

THEORY – (INTEGRATOR):

A circuit in which the output voltage waveform is the integral of the

input voltage waveform is the integrator or integration amplifier; Such a circuit is
obtained by using basic inverting amplifier configuration, if the feed back resistor R f
is replaced by a capacitor Cf. The Output voltage expression is given as
t
1
VO  
R1C f V
o
in dt  C . The frequency of input at which the gain is 0 db is given as

fb  1 . The point up to which the gain is constant & maximum is called as gain
2R1C f

limiting frequency & given as fa  1 Where Rf is the feedback resistor used to

2R f C f

correct the stability & roll-off problems. Between fa & fb the circuit acts as an
integrator and it is similar to a LPF. Integrator is most commonly used in analog
computers, A/D converter & signal wave shaping circuits.

9
PIN DIAGARAM:

INTEGRATOR:
CIRCUIT DIAGRAM:

TABULATION:

Input Output

Amplitude (V) Time Period (ms) Amplitude (V) Time Period (ms)

1 1ms 1 1ms

10
MODELGRAPH:

DESIGN PROCEDURE-(INTEGRATOR):
Design of integrator to integrate at cut-off frequency 100Hz.
1
Take fa =
2R f C f
= 100Hz.
Always take Cf < 1μf and

Let Cf = 0.1μf

1
Rf =
2C f f a

Rf = 15.9KΩ ≡

Rf = 15KΩ

1
Take fb = = 1KHz.
2R1C f

1
R1 = = 1.59KΩ.
2f b C f

R1 ≡ 1.5KΩ

11
 R1 R f
Rcomp = R1 // Rf = ≡ R1, Assume RL = 10KΩ
R1  R f

Rcomp = 1.5K

THEORY- (DIFFERENTIATOR):

A differentiator or differentiation amplifier is a circuit which performs

the mathematical operation of differentiation; that is, the output waveform is the
derivative of the input waveform. The differentiator may be constructed from the
basic inverting amplifier if an input resistor R1 is replaced by capacitor C1. The
differentiation is very useful to find the rate at which a signal varies with time. For
maintaining the stability of differentiator, a series resistor R1 is connected with input
capacitor C1. the circuit will provide differentiation function but only over a limited
frequency range & over this range differentiator tend to oscillate (or) poor stability

dVin
results. The expression for output voltage is Vo   R f C1 dt

DIFFERENTIATOR:
CIRCUIT DIAGRAM:

12
TABULATION:

Input Output

Amplitude (V) Time Period (ms) Amplitude (V) Time Period (ms)

1V 10ms 800mv 10ms

MODEL GRAPH:

13
DESIGN PROCEDURE-(DIFFERENTIATOR):
Design an op-amp differentiator that will differentiate an input signal with
fmax = 100HZ
Select fa = fmax = 100 HZ = 1 / 2πRFC1
Let C1 = 0.1µF
Then RF = 1 / 2π(102)(10-7)
= 15.9KΩ
Now choose fb = 10fa = 1 / 2πR1C1
Therefore, R1 = 1 / 2π(103)(10-7)
= 1.59KΩ
Since RFCF = R1C1
We get, CF = (1.59*103*10-7) / 15.9*103
= 0.01µF

PROCEDURE:
INTEGRATOR:

1. From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are
calculated as given in the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the sinusoidal input as the constant amplitude to the inverting terminal
of op-amp.
4. Gradually increase the frequency & observe the output amplitude.
5. Calculate the gain with respect to frequency & plot its graph.

DIFFERENTIATOR:

1. Select fa equal to the highest frequency of the input signal to be differentiated.

Calculate the component values of C1 & Rf.
2. Choose fb = 10fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of op-amp
through R1 C1.
5. Observe the shape of the output signal for the given input in CRO.
6. Note down the reading and plot the graph of input versus output wave for both
cases.

14
EXERCISE:

1) Design a differentiator circuit to differentiate an input signal that varies in

frequency from 10 Hz to about 1KHz. If a sine wave of 1V peak at 1000Hz is
applied to the differentiator, draw its output waveform.

2) Determine the useful range for differentiation in the circuit of Figure. Also
determine the output voltage if the input signal is a 2 V peak sine wave at 3
kHz.

3) For a maximum frequency of 100 Hz , design a differentiator circuit

and draw the frequency response for the same. Draw the output
waveform of differentiator for square wave of 2 V peak to peak of
100 Hz.

4) Assemble a differentiator circuit with R=10KΩ and C=0.05µf.

Connect a resistor R1 of value 470Ω between the source and the
capacitor. Feed + 0.1V, 5 KHz triangular wave input. Observe the
input and output voltages on a CRO.

15
OUTPUT:

RESULT:
Thus an Integrator and Differentiator using op-amp are designed and their
performance was successfully tested using op-amp IC 741.

16
 INSTRUMENTATION AMPLIFIER

EXP.NO: 03

AIM:
To construct an instrumentation amplifier using op-amp IC741.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 03
2. RESISTORS 1KΩ. 07
3. DUAL POWER SUPPLY (0-30)V 02
4. DIGITAL MULTIMETER --- 01
5. CONNECTING WIRES --- FEW

THEORY:

An instrumentation amplifier is the intermediate stage of a instrumentation

system. The signal source of the instrumentation amplifier is the output of the
transducer. Many transducers output do not have the ability or sufficient strength to
drive the next following stages. Therefore, instrumentation amplifiers are used to
amplify the low-level output signal of the transducer so that it can drive the following
stages such as indicator or displays.
The major requirements of an instrumentation amplifier are precise,
low-level signal amplification where low-noise, low thermal and time drifts, high
input resistance & accurate closed-loop gain, low power consumption, high CMRR &
high slew rate for superior performance.

17
PIN DIAGARAM:

CIRCUIT DIAGRAM:

TABULATION:
Frequency=1KHz
Practical Output
THEORITICAL
V1 V2 voltage
Vo = (Rf/R1)(1+2R2/RG) (V1-V2)
(Volts) (Volts) VO
(Volts)
(Volts)

4V 2V 6V 6V

18
PROCEDURE:

1. Select the entire resistor with same value of resistance R. Let RG be the gain
varying resistor with different values of resistance for simplicity let R G, be a
constant value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & V2 to the non-inverting terminals of first & second
op-amp respectively.

OUTPUT:

RESULT:
Thus an instrumentation amplifier was constructed and tested using
op-amp IC 741.

19
 ACTIVE LOWPASS, HIGH PASS AND BAND PASS FILTER
USING OP-AMP

EXP.NO: 04
AIM:
To design an Active Lowpass and Band Pass Filter using op-amp and to test
their performance.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 02
22KΩ EACH 04
2. RESISTORS
1.5KΩ 02
3. CAPACITORS 0.1μf, 0.01μf 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-20)MHz 01
6. DUAL POWER SUPPLY (0-30)V 01
7. CONNECTING WIRES --- FEW

THEORY – (ACTIVE LPF):

A filter circuit which allows only low frequency range up to a higher

cut-off frequency fH is called as Low Pass Filter. An active filter uses transistor and
components such as resistor & capacitor for its design. An active filter offers the
following advantages over a passive filter.
1. Gain & frequency adjustment flexibility.
2. No loading problem because of high input impedance & low output impedance.
3. More economical because of variety of op-amps and absence of inductors.
From the frequency response, when f<fH; the gain is maximum lAl. When f=fH; the
A
gain is 70.7% of the maximum gain and when f  fH; the gain drops or rolls off.
2
The frequency range from 0 to fH is called as Passband & fH to  is called as
Stopband. Out of Butterworth, chebyshev & cauer filters, Butterworth filter is
preferred because it has flat pass band as well as flat stop band (flat-flat) filter.

20
THEORY- (ACTIVE HPF):

An active high pass filter is simply formed by interchanging the

frequency determining resistor and capacitor in lowpass filter. A filter circuit which
allows only high frequency range greater then a lower cut-off frequency fL is called
as HIGH PASS FILTER. From the frequency response, when f<fL; the gain
gradually increases from the lowest value. When f = fL; the gain reaches 70.7% of the
A
maximum gain and when f > fL, the gain is maximum lAl. The frequency range
2
from 0 to fL is called as Stopband & fL to  is called as Passband. (This is exactly
opposite to active LPF)The order of the filter tells the roll-off rate at stop band. Order
n = 1 indicates -20dB / dec (-6db / octave); Order n = 2 indicates -40dB / dec & so on.
Higher the order of the filter, better the quality will be & complex the circuit will be.

DESIGN PROCEDURE: (ACTIVE HPF):

Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same
procedure as LPF & interchange the R & C position with capacitor first & resistor in
parallel.
Vo Af ( f / f L )
In high pass filter Theoretical gain is given as =
Vin 1  ( f / f H )2

THEORY – (ACTIVE BANDPASS FILTER):

A filter which has a pass band between two cut-off frequencies fH & fL
is called as Bandpass filter. Where fH > fL BPF is basically of two types
(i) Wide band pass filter. (ii) Narrow band pass filter.
Based on figure of merit or quality factor Q, the types are classified as follows. If
Q<10, selectivity is poor & allows higher bandwidth & such BPF is called as wide
BPF.
If Q > 10, selective is more and allows only narrow bandwidth & such
BPF is called as Narrow BPF. Relationship between Q & center frequency fC is
given as

fc fc
Q  & fc  fH fL
BW fH  fL

When frequency fL < f < fH then gain is maximum. At f < fL the gain is
gradually increasing (positive roll-off) from lower value & at f > fH the gain is
gradually decreasing (Negative roll-off) & exactly when f = fL & f = fH the gain is
A
70.7% of maximum gain .
2
21
 PIN DIAGARAM:

LOWPASS FILTER:
CIRCUIT DIAGRAM:

TABULATION:
Vin =1V
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1. 1Hz 2V 6
2. 10 2V 6
3. 100 2V 6
4. 500 2V 6
5. 1K 1.8V 5

22
MODEL GRAPH:

DESIGN PROCEDURE (ACTIVE LPF):

Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.
1. Choose the given value of fH = 1KHz.
2. Select the value of C < 1μf
1
3. Assume C = 0.1μf. Calculate R from FH =
2RC
1
R=
2f H C

1
R= = 1.5KΩ
2X 1X 10 3 X 0.1f
R = 1.5KΩ C = 0.1μf
4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + = 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ

23
 CIRCUIT DIAGRAM - (HIGH PASS FILTER):

TABULATION:
Vin =1V
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1. 1KHZ 1.8V 0.25
2. 3KHZ 2V 6
3. 10KHZ 2V 6
4. 100KHZ 2V 6
5. 500KHZ 2V 6
6. 1MHZ 2V 6
7. 5MHZ 2V 6
8. 10MHZ 2V 6

MODEL GRAPH:

24
 DESIGN PROCEDURE (ACTIVE HPF):
Design a HPF at cutoff frequency fL of 1KHz with a passband gain of 2.
1. Choose the given value of fL = 1KHz.
2. Select the value of C < 1μf
1
3. Assume C = 0.1μf. Calculate R from FL =
2RC
1
R=
2fLC
1
R= = 1.5KΩ
2X 1X 10 3 X 0.1f
R = 1.5KΩ C = 0.1μf
4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + = 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ

CIRCUIT DIAGRAM: (BANDPASS FILTER)

TABULATION:
Vin =1V
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1. 1KHZ 2.7V 8.6
2. 3KHZ 3.6V 11.13
3. 10KHZ 3.6V 11.13
4. 20KHZ 2V 6
5. 30KHZ 1.5V 3.5

25
MODEL GRAPH:

DESIGN PROCEDURE - (ACTIVE BPF):

Design a BPF to pass a band of 1KHz to 10KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as fH = 10 KHz and the lowest cut-
off frequency of HPF as fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
FL = ; Therefore R =
2RC 2f L C
1
R= ;
2 (1KHz )(0.1X 10 6 )
R = 1.59KΩ ≡ R=1.5KΩ
4. Then design the LPF by taking fH = 10KHz. Assume the value of C3 < 1μf. Let
C3 = 0.01μf.
1 1
5. Calculate R from the expression fH = ; Therefore R3 =
2RC 2f H C

1
R3 = ;
2 (10 KHz )(0.01X 10 6 )
R3 = 1.59KΩ ≡ R3=1.5KΩ

6. Calculate the values of Rf & R1 with the use of pass band gain.
Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF)

Therefore for both HPF & LPF the value of Rf = R1 to obtain a individual
Rf
P.B gain of 2. Af = (1+ ) = 2 (for HPF)
R1

26
 Rf
Af = (1+ ) = 2 (for LPF)
R1
Let Rf = R1 = 22KΩ.

PROCEDURE - (LPF & HPF):

1. Connect the circuit as shown in the circuit diagram.

2. Select the corresponding cut-off frequency (higher or lower) and determine the
value of C&R. select the value of R1 & Rf depending on desired passband
gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
4. Tabulate the output voltage Vo with respect to different values of input
frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.

PROCEDURE:

1. Select the lower and higher cut-off frequency and calculate the value of R & C
for the given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing
the HPF followed by a LPF (i.e) HPF in series with LPF.
3. Connect the circuit as shown in the circuit diagram.
4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
5. Tabulate the output voltage Vo with respect to different values of input
frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.

27
 OUTPUT:
LPF:

HPF:

BPF

RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed
and tested using op-amp IC 741.
28
 ASTABLE MULTIVIBRATOR AND MONOSTABLE
MULTIVIBRATOR USING OP-AMP

EXP.NO: 05
AIM:
To design an Astable and Monostable multivibrator using op-amp IC
741 and to test their characteristics.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 741 --- 01
100Ω, 47KΩ,
EACH 01
2. RESISTORS 1.5 KΩ
10KΩ 02
3. CAPACITORS 0.01μf, 0.1μf 01
4. SIGNAL GENERATOR (0-3)MHz 01
5. CATHODE RAY OSCILLOSCOPE (0-20)MHz 01
6. DIODE IN4148 02
8. DUAL POWER SUPPLY (0-30)V 01
9. CONNECTING WIRES --- FEW

THEORY-(ASTABLE MULTIVIBRATOR):

An op-amp Astable multivibrator is also called as free running

oscillator. The basic principle of generation of square wave is to force an op-amp to
R2
operate in the saturation region (±Vsat). A fraction β = of the output is
R1  R 2
feedback to the positive input terminal of op-amp. The charge in the capacitor
increases & decreases upto a threshold value called ±βVsat. This charge in the
capacitor triggers the op-amp to stay either at +Vsat or –Vsat. Asymmetrical square
wave can also be generated with the help of zener diodes. Astable multivibrator do
not require an external trigger pulse for its operation & output toggles from one state
to another and does not contain a stable state. Astable multivibrator is mainly used in
timing applications & waveforms generators.

29
 PIN DIAGARAM:

CIRCUIT DIAGRAM - (ASTABLE):

TABULATION:

DESIGN VALUE OBSERVED VALUE

Amplitude T T
Waveforms tH tL F tH tL F
(volts) (tH+tL) (tH+tL)
(ms) (ms) (Hz) (ms) (ms) (Hz)
(ms) (ms)

Output
15V 0.5 0.5 1 1 1 1 1 1 KHz
waveform

Capacitive
6V 0.5 0.5 1 1 1 1 1 1 KHz
waveform

30
MODEL GRAPH:

CIRCUIT DIAGRAM - (MONOSATBLE):

TABULATION:

Amplitude Time period

S.No Waveforms
(volts) (ms)

tH = 0.5
1. Input waveform 5V
tL= 0.5

tH = 0.65
2. Output waveform 15V
tL = 0.35

31
THEORY - (MONOSTABLE MULTIVIBRATOR):
A multivibrator which has only one stable and the other is quasi-stable
state is called as Monostable multivibrator or one-short multivibrator. This circuit is
useful for generating single output pulse of adjustable time duration in response to a
triggering signal. The width of the output pulse depends only on the external
components connected to the op-amp. Usually a negative trigger pulse is given to
make the output switch to other state. But, it then returns to its stable state after a time
interval determined by circuit components. The pulse width T can be given as T =
0.69RC. For Monostable operation the triggering pulse width Tp should be less then
T, the pulse width of Monostable multivibrator. This circuit is also called as time
delay circuit or gating circuit.
DESIGN PROCEDURE:
ASTABLE MULTIVIBRATOR:
Design of square wave generator at f0 = 1 KHz.
1. The expression of fo is obtained from the charging period t1 & t2 of capacitor

1
as fo =
2 RC ln[ 1  (2 R1 / R2 )]

2. To simplify the above expression, the value of R1 & R2 should be taken as R2

1
= 1.16R1, such that fo simplifies to fo =
2 RC

3. Assume the value of R1 = 10KΩ and find R2. R2 = 11.6KΩ

1
4. Assume the value of C & Determine R from fo =
2 RC
Let C = 0.01μf
1 1
R= =
2 f oC 2 X (1X 10 )(0.01X 10 6 )
3

R = 50KΩ ≡ R = 47KΩ

5. Calculate the threshold point from

R1
lVT l or lβVSAT l = lβVSAT l where β is the feedback ratio.
R1  R 2

32
MODEL GRAPH:

MONOSTABLE MULTIVIBRATOR:

1. Assume R1 = R2 = 10KΩ & calculate β from expression

R1 10 K
β= = = 0.5.
R1  R 2 20 K
2. Find the value of R & C from the pulse width time expression.
(1  VD / Vsat )
T = RC ln
1 
(1  VD / Vsat )
T = RC ln
0.5
T ≡0.69RC.

3. Assume c = 0.01μf and R = 50KΩ ≡ 47KΩ. Find T where Rf = R3 = R

T = 0.69 (50X103) (0.01X10-6)
T = 0.345ms.
4. Triggering pulse width Tp must be much smaller than T. T p < T.
5. Assume a HPF in the input session with C1=0.1μf (Assumption) & R4 = 100Ω

33
PROCEDURE:
ASTABLE MULTIVIBRATOR:

1. Calculate the value of components using the design procedure given.

2. Connect the circuit as per as the circuit diagram.
3. As there is no specific input signal for this circuit switch ON the power
supply.
4. Note down the reading for output square wave (i.e) time & amplitude and
tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.

MONOSTABLE MULTIVIBRATOR:

1. Calculate the value of components using the design procedure given.

2. Connect the circuit as per as the circuit diagram.
3. Apply the negative trigger voltage to the non-inverting terminal.
4. Note down the reading for output voltage Vo & ON & OFF time period &
tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.

OUTPUT:
ASTABLE MULTIVIBRATOR:

34
MONOSTABLE MULTIVIBRATOR:

RESULT:

Thus an Astable, Monostable multivibrator and Schmitt trigger are

designed and tested using op-amp IC 741.

35
 SCHMITT TRIGGER USING OP-AMP

EXP.NO: 06
AIM:
To design a schmitt trigger using op-amp IC 741 and to test their
characteristics.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1 IC 741 --- 01
100 KΩ 01
2 RESISTORS
10KΩ 02
3 SIGNAL GENERATOR (0-3)MHz 01
4 CATHODE RAY OSCILLOSCOPE (0-20)MHz 01
5 DUAL POWER SUPPLY (0-30)V 01
6 CONNECTING WIRES --- FEW

THEORY-(SCHMITT TRIGGER):

A circuit which converts a irregular shaped waveform to a square wave

or pulse is called a Schmitt trigger or squaring circuit. The input voltage Vin triggers
the output Vo every time it exceeds certain voltage levels called upper threshold
voltage VUT and lower threshold voltage VLT. The threshold voltages are obtained by
using the voltage divider. A comparator with positive feedback is said to exhibit
hysteresis, a dead band condition. The hysteresis voltage is the difference between
VUT & VLT.
There are two types of Schmitt trigger based on where the irregular wave is
given. They are, Inverting & non-inverting Schmitt trigger. Schmitt trigger finds
application in wave shaping circuits. The other name given to Schmitt trigger is
regenerative comparator.

36
MODEL GRAPH:

PIN DIAGARAM:

SCHMITT TRIGGER:

37
TABULATION:

O/P
I/P Voltage I/P Time VUT (UTP) VLT (LTP) O/P Time
Voltage
(Volts) (ms) (Volts) (Volts) (ms)
(Volts)

5V 1ms 1V -1V 15V 1ms

DESIGN PROCEDURE:

1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity.
Let Vut = 1V & Vlt = -1V.
2. For Op-amp 741C ± Vsat ≡ ±13V to ± 14V. And assume Vref = 0, Since the
another end of R1 is grounded.
3. if Vo = +Vsat the voltage at the positive terminal will be (voltage from
potential divider R1 & R2).
R1
Vut = Vref + (Vsat - Vref )
R1  R 2
Therefore Vref = 0.
R1
Vut = (+ Vsat).
R1  R 2
R1
4. Similarly Vlt will be Vlt = ( ) – Vsat.
R1  R 2
5. Sub Vut & assume R1 or R2 & find the other component value.
R1
1V = (13)
R1  R 2
R1 + R2 = 13R1
R2 = 12R1 if R1 = 10K then R2 = 120K ≡100K.

6. Calculate ROM by
R1R 2 (10 K)(100 K)
ROM = R1 // R2 = .
R1  R 2 110 K
1000 K
ROM = ≡ 10KΩ. & select RL = 10KΩ (Assumption)
110 K
7. Calculate hystersis voltage
Vhy = Vut – Vlt

38
 R1
= [+Vsat – (-Vsat)]
R1  R 2
10 K
= [26V] Since Vsat = 13V
110 K
= 0.0909 [26V]
Vhy = 2.363V

PROCEDURE:

1. Design the value of circuit components and select VUT & VLT as given in the
design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the input signal to the input terminal of op-amp & set VUT & VLT
values.
4. Note down the readings from the output waveform.
5. Plot the graph & show the relationship between Input sine wave & Output
square wave.

OUTPUT:

RESULT:

Thus a Schmitt trigger is designed and tested using op-amp IC 741.

39
 RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR
USING OP-AMP

EXP.NO: 07
AIM:
To design RC Phase Shift and Wien Bridge Oscillator using op-amp IC
741 and to test its performance.
APPARATUS REQUIRED:
S.NO COMPONENTS RANGE QUANTITY
1. IC 741 --- 01
1.5KΩ 03
2. RESISTORS
15KΩ 02
3. CAPACITORS 0.1μf 03
4. POT 1MΩ,47KΩ EACH 01
5. DUAL POWER SUPPLY (0-30)V 01
6. CATHODE RAY OSCILLOSCOPE (0-20)MHz 01
7. CONNECTING WIRES --- FEW

THEORY:(RC PHASE SHIFT OSCILLATOR)

RC phase shift oscillator produces 360° of phase shift in two parts. Firstly,
each and every RC pair in the feedback network produces 60° phase shift and totally
there were three pairs, thus producing 180° Phase shift and secondly, the feedback
input is given to the inverting terminal of op-amp to produce another 180° phase shift
and a total phase shift of 360°.
The frequency of oscillation is given by f0 = 1 ; If an inverting
2 6 RC
amplifier is used, the gain must be atleast equal to 29 to ensure the oscillations with
constant amplitude that is, AV  < 1. Otherwise the oscillation will die out.
THEORY :(WIEN BRIDGE)
A bridge circuit with two components connected in series and parallel
combination is used to archived the required of phase shift of 0 0. When the bridge is
balanced the phase shift of 00 is achieved and the feedback signal is connected to the
positive terminal; of Op-amp. So the Op-amp is acting as a non-inverting amplifier
and the feedback network do not provide any phase shift.

40
PIN DIAGARAM:

RC PHASE SHIFT OSCILLATOR:

CIRCUIT DIAGRAM:

TABULATION:.

OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)

15V 2.4ms 417Hz 400Hz

41
MODEL GRAPH:

WIEN BRIDGE OSCILLATOR:

CIRCUIT DIAGRAM:

TABULATION:

OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)

15V 1ms 1KHz 1KHz

42
The major drawback of wien bridge oscillator is difficulty in balancing the bridge
circuit. This occurs because of drift in component values due to external and internal
1
disturbances. The frequency of oscillation is given as f0 = .
2RC
PROCEDURE- (RC PHASE SHIFT):
1. Select the given frequency of oscillation f0 = 400Hz.
1
2. Assume either R or C to find out the other using formula f0 = .
2 6 RC
3. The gain is selected such that Rf / R1 = 29K. Assume Rf or R1 to find the other.
4. Connect the circuit as per as the circuit diagram.
5. Measure the amplitude frequency of the output signal plot the graph.

WEIN BRIDGE OSCILLATOR:

1. Select the given frequency of oscillation f0 = 1 KHz.

1
2. Assume either R or C to find out the other using formula . Also
2RC
determine the value of other components as given in design procedure.
3. Connect the circuit as per as the circuit diagram.
4. Measure the amplitude and frequency of the output signal to plot the graph.

43
MODEL GRAPH:

DESIGN :
RC PHASE SHIFT OSCILLATOR:

Design a RC phase shift oscillator to oscillate at 400Hz.

1. Select fo = 400Hz.
2. Assume C = 0.1μf & determine R from fo.
1 1
fo = =R= = 1.6K Use (1.5K)
2 6 RC 2 6 f oc
3. To prevent the loading of amp because it is necessary that R1>>10R.
Therefore R1=10R=15K.
4. At this frequency the gain must be atleast 29 (i.e)Rf / R1 =29.
Therefore Rf = 29R1.
Rf = 29 (15K) = 435KΩ.(Use 1M Pot)

WEIN BRIDGE OSCILLATROR:

(i) Select frequency f0 = 1KHz.

1
(ii) Use f0 = , A = 1+(Rf / R1) = 3. To find R & Rf.
2RC
(iii) Therefore Rf = 2R1 & assume C = 0.1μf & find R from
1
R= = 1.59KΩ.
2f o C
(iv) Assume R1 = 10R & find Rf from R f = 2R1
Therefore R1 = 15K
Rf = 30 (Use 47K Pot)

44
OUTPUT:

RC PHASE SHIFT OSCILLATOR:

WEINBRIDGE OSCILLATOR:

RESULT:
Thus RC Phase Shift and Wien Bridge Oscillator were designed and
tested using op-amp IC 741.

45
 ASTABLE & MONOSTABLE MULTIVIBRATOR
USING IC 555 TIMER

EXP.NO: 08
AIM:
To Design and test Astable and Monostable multivibrator using 555 timer IC.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. IC 555 --- 01

2. RESISTORS 6.8KΩ,390Ω,3.3KΩ,300Ω,10KΩ EACH 01

3. CAPACITORS 0.1μf, 0.01μf. EACH01

4. SIGNAL GENERATOR (0-3)MHz 01
CATHODE RAY
5. (0-20)MHz 01
OSCILLOSCOPE
6. DUAL POWER SUPPLY (0-30)V 01
7. CONNECTING WIRES --- FEW

THEORY:(ASTABLE)
When the power supply V CC is connected, the external timing capacitor ‘C”
charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high
(≈VCC) as Reset R=0, Set S=1 and this combination makes Q = 0 which has
unclamped the timing capacitor ‘C’.
When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the
control flip flop on that Q =1. It makes Q1 ON and capacitor ‘C’ starts discharging
towards ground through RB and transistor Q1 with a time constant RBC. Current also
flows into Q1 through RA. Resistors RA and RB must be large enough to limit this
current and prevent damage to the discharge transistor Q1. The minimum value of R A
is approximately equal to VCC/0.2 where 0.2A is the maximum current through the
ON transistor Q1.
During the discharge of the timing capacitor C, as it reaches V CC/3, the lower
comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0
unclamps the external timing capacitor C. The capacitor C is thus periodically
charged and discharged between 2/3 VCC and 1/3 VCC respectively. The length of
time that the output remains HIGH is the time for the capacitor to charge from 1/3
VCC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of V CC
volts is given by VC = VCC [1- exp (-t/RC)]
Total time period T = 0.69 (RA + 2 RB) C
f = 1/T = 1.45/ (RA + 2RB) C

46
 PIN DIAGRAM:

CIRCUIT DIAGRAM:
ASTABLE MULTIVIBRATOR:

TABULATION:

DESIGN VALUE OBSERVED VALUE

Amplitud T= T=
Waveforms e THigh THigh
(volts) THigh TLow F THigh TLow F
(ms) (ms)
+ (KHz) (ms) (ms)
+ (KHz)
TLow TLow
(ms) (ms)
Output 0.25m 0.75m 0.25m
5V 0.75ms 1 1` 1 1`
waveform s s s
VCC/3=
Capacitor 1.7V 0.25m 0.75m 0.25m
0.75ms 1 1` 1 1`
waveform 2VCC/3= s s s
3.4V

47
MODEL GRAPH:

MONOSATBLE MULTIVIBRATOR:

48
MONOSATBLE MULTIVIBRATOR:
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-
generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand by mode the output of the
circuit is approximately Zero or at logic-low level. When an external trigger pulse is
given, the output is forced to go high (  VCC). The time for which the output remains
high is determined by the external RC network connected to the timer. At the end of
the timing interval, the output automatically reverts back to its logic-low stable state.
The output stays low until the trigger pulse is again applied. Then the cycle repeats.
The Monostable circuit has only one stable state (output low), hence the name
Monostable. Normally the output of the Monostable Multivibrator is low.

DESIGN PROCEDURE:
ASTABLE MULTIVIBRATOR:

Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 25%
using 555 timer IC.
Given Frequency=1000Hz
Duty cycle=25%
D= T low/T = RB/RA+2RB*100
100RB = 25(RA+2RB)
50RB – 25RA = 0 -----------------------------------(1)
given f=1khz we know that T=1/f
T=1ms
T= T high + T low
0.69(RA+2RB)C = 1*10-3
0.69(RA+2RB) = 1*10-3/C
Let C=0.1μF
0.69RA+1.38RB = 1*10-3/0.1*10-6
0.69RA+1.38RB = 10 4 ------------------------------------(2)
Solving equation 1 & 2 we get
RA=7.2K
RB= 3.6K

49
TABULATION:

Amplitude Time period

S.No Waveforms
(volts) (ms)

tH = 0.5ms
1. Input waveform 5V
tL = 0.5ms

tH = 1.1ms
2. Output waveform 5V
tL = 0.4ms

tH = 1.1ms
3. Capacitive waveform 3.4V
tL = 0.4ms

MODEL GRAPH:

50
MONOSTABLE MULTIVIBRATOR:

T = 1.1RAC
Assume RA = 10KΩ
C=0.1μF
T = 1.1 * 10000 * 0.1*10-6
= 1.1ms

PROCEDURE:
ASTABLE MULTIVIBRATOR:

1. Calculate the component values using the design procedure.

2. Connect the circuit as shown in the circuit diagram.
3. Observe and note down the output waveform.
4. Measure the frequency of oscillations and duty cycle and then compare with
the given values.
5. Plot both the waveforms to the same time scale in a graph.

MONOSTABLE MULTIVIBRATOR:

1. Calculate the value of R & C using design procedure.

2. Connect the circuit as shown in the circuit diagram.
3. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
4. Observe the output waveform and measure the pulse duration.
5. Theoretically calculate the pulse duration as T=1.1 RAC

51
OUTPUT:
Astable multivibrator:

MONOSTABLE MULTIVIBRATOR:

RESULT:
Thus the Astable and Monostable multivibrator is designed and tested using
555 timer IC.

52
 DC POWER SUPPLY USING LM317

EXP.NO: 10

AIM:
To design and test the power supply voltage regulator using LM317 .

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. LM317 --- EACH 01

2. RESISTORS 220Ω, 1KΩ EACH 01

3. CAPACITOR 0.022µf 01
4. DIGITAL MULTIMETER --- 01
5. DUAL POWER SUPPLY (0-30)V 01
6. CONNECTING WIRES --- FEW

THEORY:
CHARACTERISTICS OF THE LM 317:

The LM 317 will provide a regulated output current of upto 1.5A,Provided

that if is not subjected to a power dissipation of more than about 15W.This means it
should be electrically isolated from, and fastened to, a large heat sink such as the
metal chassis of the power supply.
The LM 317 requires a minimum “dropout” voltage of 3v across its input and
output terminals or it will drop out of regulation. Thus the upper limit of Vo is 3V
below the minimum input voltage from the unregulated supply.
It is good practice to connect bypass capacitors .This reduces the ripple
voltage from the rectifier.
The LM 317 protects itself against over heating, too much internal power
dissipation and too much current. When the chip temperature reaches 175 degrees, the
LM 317 shuts down. If the product of output current and input-to-output voltage
exceeds 15 to 20W, or if currents greater than about 1.5A are required the LM 317
also shuts down. When the overload condition is removed the Operation is resumed.
All these features are made possible by the remarkable internal circuitry of LM 317.
53
 Along with the simple 3 pin fixed regulators; a number of adjustable or
programmable devices are available. Some devices also include features such as
programmable current limiting. It is also possible to configure multiple regulators so
that they track or follow each other.

54
PIN DIAGRAM:

CIRCUIT DIAGRAM - (LM317):

MODEL GRAPH:

55
TABULATION:

INPUT VOLTAGE OUTPUT VOLTAGE

S.NO
(Volts) (Volts)
1. 5 3.7

2. 6 4.7

3. 7 5.7

4. 8 6.6

5. 9 6.9

6. 10 6.9

7. 11 6.9

8. 12 6.9

9. 14 6.9

10 15 6.9

DESIGN PROCEDURE:
Assume R1 = 220Ω, R2 = 1K
VO = 1.25(1+ (R2/R1))
VO = 6.93V

PROCEDURE:
1) Connections are made as per the circuit diagram.
2) The input voltage is varied between 0 to 30 v
3) The corresponding output is taken using voltmeter.
4) The readings are tabulated and the graph is plotted.

EXERCISE:

1. Using LM317,design an adjustable voltage regulator to satisfy the following

specifications: output voltage Vo = 12 to 15 V and output current Io = 0.50 A.
Comment on the difference between calculated and experimental results

RESULT:
Thus the 317 voltage regulators are designed and tested successfully.

56
PIN DETAILS:

PIN NO. FUNCTION

1 Inverting input
2 Non Inverting input
3 Oscillator output
4 (+)CL sense
5 (-)CL sense
6 RT
7 CT
8 Ground(-ve supply voltage)
9 Compensation
10 Shutdown
11 Emitter-A
12 Collector-A
13 Collector-B
14 Emitter-B
15 Vin
16 Vref

TECHNICAL INFROMATION:

TEMPERATURE
DESCRIPTION
RANGE
SG3524N(16-pin plastic DIP) 0C to 70C
SG3524F(16-pin cerdip) 0C to 70C
SG3524D(16-pin SO) 0C to 70C

57
 STUDY OF SMPS

EXP.NO: 11
AIM:
To study the control of SMPS.
THEORY:
The switching regulator is also called as switched mode regulator. In
this case, the pass transistor is used as a controlled switch and is operated at either
cutoff or saturated state. Hence the power transmitted across the pass device is in
discrete pulses rather than as a steady current flow. Greater efficiency is achieved
since the pass device is operated as a low impedance switch. When the pass device is
at cutoff, there is no current and dissipated power. Again when the pass device is in
saturation, a negligible voltage drop appears across it and thus dissipates only a small
amount of average power, providing maximum current to the load. The efficiency is
switched mode power supply is in the range of 70-90%.
A switching power supply is shown in figure. The bridge rectifier and
capacitor filters are connected directly to the ac line to give unregulated dc input. The
reference regulator is a series pass regulator. Its output serves as a power supply
voltage for all other circuits. The transistors Q1, Q2 are alternatively switched ‘on’ &;
off, these transistors are either fully ‘on’ or ‘cut-off, so they dissipate very little
power. These transistors drive the primary of the main transformer. The secondary is
centre tapped and full wave rectification is achieved by diodes D1 and D2. This
unidirectional square wave is next filtered through a two stage LC filter to produce
output voltage Vo.

SG 3524:
FUNCTION:
Switched Mode Power Supply Control Circuit
FEATURES:
 Complete PWM Power Controlled circuitry.
 Single ended or push-pull outputs.
 Line and Load regulation of 0.2%.
 1% maximum temperature variation.
 Total Supply current is less than 10mA
 Operation beyond 100KHz

58
59
RESULT:
Thus the control of SMPS IC SG3524 had been studied.

60
 R-2R LADDER TYPE D-A CONVERTER USING OP-
AMP

EXP.NO: 12

AIM:

To design a 4-bit R-2R ladder type DAC using OP-AMP.

APPARATUS REQUIRED:

SL.NO ITEMS RANGE QUANTITY

1 IC 741 - 1
2 DIGITAL MULTIMETER METER (0-15)V 1
3 DUAL POWER SUPPLY (0-30)V 1
4 RESISTOR 22K, 10K 5,4
5 BREAD BOARD - 1

THEORY:

In R-2R ladder network only two values of resistors are required. Consider 4
bit DAC, where switch position d1, d2, d3, d4 corresponding to binary words.

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. The inputs are given through b0, b1, b2, b3.
3. The inputs are given from (0-15)V and observe the outputs in voltmeter.
4. The graph is drawn.

PIN DIAGRAM:

61
CIRCUIT DIAGRAM:

DESIGN PROCEDURE:

Vo = -Rf (b3/2R + b2/4R + b1/8R + b0/16R)Vref

Rf = R

Vo = -Vref (b3/2 + b2/4 + b1/8 + b0/16)

Assume R = 10K

2R = 22K
OUTPUT:

62
TABULATION:

Equivalent Binary
Practical Theoretical
Decimal Voltage Voltage
(V) (V)
b3 b2 b1 b0

0 0 0 0 0 0 0

1 0 0 0 1 -0.3 -0.3

2 0 0 1 0 -0.6 -0.6

3 0 0 1 1 -0.9 -0.9

4 0 1 0 0 -1.2V -1.2V

5 0 1 0 1 -1.6V -1.6V

6 0 1 1 0 -1.9V -1.9V

7 0 1 1 1 -2.2V -2.2V

8 1 0 0 0 -2.5V -2.5V

9 1 0 0 1 -2.8V -2.8V

10 1 0 1 0 -3.1V -3.1V

11 1 0 1 1 -3.4V -3.4V

12 1 1 0 0 -3.7V -3.7V

13 1 1 0 1 -4.1V -4.1V

14 1 1 1 0 -4.4V -4.4V

15 1 1 1 1 -4.7V -4.7V

RESULT:

Thus the 4-bit R-2R ladder type DAC is designed and its outputs are verified.

63