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SEMICONDUCTOR TECHNICAL DATA by MC145483/D


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DW SUFFIX

 20

1
SOG PACKAGE
CASE 751D
The MC145483 is a 13–bit linear PCM Codec–Filter with 2s complement data
format, and is offered in 20–pin SOG and SSOP packages. This device
performs the voice digitization and reconstruction as well as the band limiting SD SUFFIX
and smoothing required for the voice coding in digital communication systems. SSOP
20
This device is designed to operate in both synchronous and asynchronous CASE 940C
applications and contains an on–chip precision reference voltage. 1
This device has an input operational amplifier whose output is the input to the
encoder section. The encoder section immediately low–pass filters the analog ORDERING INFORMATION
signal with an active R–C filter to eliminate very high frequency noise from being MC145483DW SOG Package
modulated down to the passband by the switched capacitor filter. From the MC145483SD SSOP
active R–C filter, the analog signal is converted to a differential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and PIN ASSIGNMENT
non–inverted signal paths. Another advantage of this differential design is that
VAG Ref 1 20 VAG
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This RO– 2 19 TI+
dramatically improves the power supply rejection ratio. PI 3 18 TI–
After the differential converter, a differential switched capacitor filter band–
PO– 4 17 TG
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential 13–bit linear A/D converter. The digital output is 2s PO+ 5 16 HB
complement format. VDD 6 15 VSS
The decoder digital input accepts 2s complement data and reconstructs it
using a differential 13–bit linear D/A converter. The output of the D/A is FSR 7 14 FST
low–pass filtered at 3400 Hz and sinX/X compensated by a differential switched DR 8 13 DT
capacitor filter. The signal is then filtered by an active R–C filter to eliminate the BCLKR 9 12 BCLKT
out–of–band energy of the switched capacitor filter.
The MC145483 PCM Codec–Filter has a high impedance VAG reference pin PDI 10 11 MCLK
which allows for decoupling of the internal circuitry that generates the
mid–supply VAG reference voltage to the VSS power supply ground. This
reduces clock noise on the analog circuitry when external analog signals are
referenced to the power supply ground.
The MC145483 13–bit linear PCM Codec–Filter accepts both Short Frame
Sync and Long Frame Sync clock formats, and utilizes CMOS due to its reliable
low–power performance and proven capability for complex analog/digital VLSI
functions.
• Single 3 V Power Supply
• 13–Bit Linear ADC/DAC Conversions with 2s Complement Data Format
• Typical Power Dissipation of 8 mW, Power–Down of 0.01 mW
• Fully–Differential Analog Circuit Design for Lowest Noise
• Transmit Band–Pass and Receive Low–Pass Filters On–Chip
• Transmit High–Pass Filter May be Bypassed by Pin Selection
• Active R–C Pre–Filtering and Post–Filtering
• On–Chip Precision Reference Voltage of 0.886 V for a – 5 dBm TLP
@ 600 Ω
• 3–Terminal Input Op Amp Can be Used, or a 2–Channel Input Multiplexer
• Receive Gain Control from 0 dB to – 21 dB in 3 dB Steps in Synchronous
Operation
• Push–Pull 300 Ω Power Drivers with External Gain Adjust
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
3/97 TN97033100

 Motorola, Inc. 1997

MOTOROLA MC145483
1
 RECEIVE
SHIFT DR
REGISTER
RO – DAC
FREQ
PI

– FSR
PO –
+
BCLKR
SHARED
DAC
PDI
PO + –1 SEQUENCE
AND
VDD VDD CONTROL MCLK

VSS R*
BCLKT
0.886 V
VAG Ref REF
FST
1 R*
VAG
VSS

TG

TI – –
ADC
TI + +
FREQ TRANSMIT
SHIFT DT
HB REGISTER

Figure 1. MC145483 13–Bit Linear PCM Codec–Filter Block Diagram

DEVICE DESCRIPTION its absence is not detrimental to intelligibility. To reduce the

digital data rate, which is proportional to the sampling rate, a
A PCM Codec–Filter is used for digitizing and reconstruct- sample rate of 8 kHz was adopted, consistent with a band-
ing the human voice. These devices are used primarily for width of 3 kHz. This sampling requires a low–pass filter to
the telephone network to facilitate voice switching and trans- limit the high frequency energy above 3 kHz from distorting
mission. Once the voice is digitized, it may be switched by the in–band signal. The telephone line is also subject to
digital switching methods or transmitted long distance (T1, 50/60 Hz power line coupling, which must be attenuated
microwave, satellites, etc.) without degradation. The name from the signal by a high–pass filter before the analog–to–
codec is an acronym from ‘‘COder’’ for the analog–to–digital digital converter. The MC145483 includes a high–pass filter
converter (ADC) used to digitize voice, and ‘‘DECoder’’ for for compatibility with existing telephone applications, but it
the digital–to–analog converter (DAC) used for reconstruct- may be removed from the analog input signal path by the
ing voice. A codec is a single device that does both the ADC high–pass bypass pin.
and DAC conversions. The digital–to–analog conversion process reconstructs a
To digitize intelligible voice requires a signal–to–distortion staircase version of the desired in–band signal, which has
ratio of about 30 dB over a dynamic range of about 40 dB. spectral images of the in–band signal modulated about the
This may be accomplished with a linear 13–bit ADC and sample frequency and its harmonics. These spectral images
DAC. The MC145483 satisfies these requirements and may are called aliasing components, which need to be attenuated
be used as the analog front–end for voice coders using DSP to obtain the desired signal. The low–pass filter used to at-
technology to further compress the digital data stream. tenuate these aliasing components is typically called a re-
In a sampling environment, Nyquist theory says that to construction or smoothing filter.
properly sample a continuous signal, it must be sampled at a The MC145483 PCM Codec–Filter has the codec, both
frequency higher than twice the signal’s highest frequency presampling and reconstruction filters, and a precision volt-
component. Voice contains spectral energy above 3 kHz, but age reference on–chip.

MC145483 MOTOROLA
2
 PIN DESCRIPTIONS when a logic 1 is applied to this pin. The device goes through
a power–up sequence when this pin is taken to a logic 1
POWER SUPPLY state, which prevents the DT PCM output from going low im-
VDD pedance for at least two FST cycles. The VAG and VAG Ref
Positive Power Supply (Pin 6) circuits and the signal processing filters must settle out be-
fore the DT PCM output or the RO– receive analog output
This is the most positive power supply and is typically con-
will represent a valid analog signal.
nected to + 3 V. This pin should be decoupled to VSS with a
0.1 µF ceramic capacitor. ANALOG INTERFACE
VSS TI+
Negative Power Supply (Pin 15) Transmit Analog Input (Non–Inverting) (Pin 19)
This is the most negative power supply and is typically This is the non–inverting input of the transmit input gain
connected to 0 V. setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
VAG amp. This allows input signals that are referenced to the V SS
Analog Ground Output (Pin 20) pin to be level shifted to the VAG pin with minimum noise.
This output pin provides a mid–supply analog ground. This This pin may be connected to the VAG pin for an inverting
pin should be decoupled to VSS with a 0.01 µF ceramic ca- amplifier configuration if the input signal is already refer-
pacitor. All analog signal processing within this device is ref- enced to the VAG pin. The common mode range of the TI+
erenced to this pin. If the audio signals to be processed are and TI– pins is from 1.2 V, to V DD minus 1.2 V. This is an FET
referenced to V SS, then special precautions must be utilized gate input.
to avoid noise between V SS and the VAG pin. Refer to the ap- The TI+ pin also serves as a digital input control for the
plications information in this document for more information. transmit input multiplexer. Connecting the TI+ pin to V DD will
The VAG pin becomes high impedance when this device is in place this amplifier’s output (TG) into a high–impedance
the powered–down mode. state, and selects the TG pin to serve as a high–impedance
input to the transmit filter. Connecting the TI+ pin to VSS will
VAG Ref also place this amplifier’s output (TG) into a high–impedance
Analog Ground Reference Bypass (Pin 1) state, and selects the TI– pin to serve as a high–impedance
input to the transmit filter.
This pin is used to capacitively bypass the on–chip circuit-
ry that generates the mid–supply voltage for the VAG output TI–
pin. This pin should be bypassed to VSS with a 0.1 µF ceram- Transmit Analog Input (Inverting) (Pin 18)
ic capacitor using short, low inductance traces. The VAG Ref
pin is only used for generating the reference voltage for the This is the inverting input of the transmit gain setting op-
VAG pin. Nothing is to be connected to this pin in addition to erational amplifier. Gain setting resistors are usually con-
the bypass capacitor. All analog signal processing within this nected from this pin to TG and from this pin to the analog
device is referenced to the VAG pin. If the audio signals to be signal source. The common mode range of the TI+ and TI–
processed are referenced to VSS, then special precautions pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input.
must be utilized to avoid noise between VSS and the VAG pin. The TI– pin also serves as one of the transmit input mulit-
Refer to the applications information in this document for plexer pins when the TI+ pin is connected to VSS. When TI+
more information. When this device is in the powered–down is connected to VDD, this pin is ignored. See the pin descrip-
mode, the VAG Ref pin is pulled to the VDD power supply with tions for the TI+ and the TG pins for more information.
a non–linear, high–impedance circuit.
TG
CONTROL Transmit Gain (Pin 17)
HB This is the output of the transmit gain setting operational
Transmit High–Pass Filter Bypass (Pin 16) amplifier and the input to the transmit band–pass filter. This
This pin selects whether the transmit high–pass filter will op amp is capable of driving a 2 kΩ load. Connecting the TI+
be used or bypassed, which allows frequencies below pin to VDD will place the TG pin into a high–impedance state,
200 Hz to appear at the input of the ADC to be digitized. This and selects the TG pin to serve as a high–impedance input to
high–pass filter is a third order filter for attenuating power line the transmit filter. All signals at this pin are referenced to the
frequencies, typically 50/60 Hz. A logic low selects this filter. VAG pin. When TI+ is connected to VSS, this pin is ignored.
A logic high deselects or bypasses this filter. When the filter See the pin descriptions for TI+ and TI– pins for more in-
is bypassed, the transmit frequency response extends down formation. This pin is high impedance when the device is in
to dc. the powered–down mode.

PDI RO–
Power–Down Input (Pin 10) Receive Analog Output (Inverting) (Pin 2)
This pin puts the device into a low power dissipation mode This is the inverting output of the receive smoothing filter
when a logic 0 is applied. When this device is powered down, from the digital–to–analog converter. This output is capable
all of the clocks are gated off and all bias currents are turned of driving a 2 kΩ load to 0.886 V peak referenced to the VAG
off, which causes RO–, PO–, PO+, TG, VAG, and DT to be- pin. If the device is operated half–channel with the FST pin
come high impedance. The device will operate normally clocking and FSR pin held low, the receive filter input will be

MOTOROLA MC145483
3
connected to the VAG voltage. This minimizes transients at chronous and approximately rising edge aligned to FST. For
the RO– pin when full–channel operation is resumed by optimum performance at frequencies of 1.536 MHz and
clocking the FSR pin. This pin is high impedance when the higher, MCLK should be synchronous and approximately ris-
device is in the powered–down mode. ing edge aligned to the rising edge of FST. In many ap-
plications, MCLK may be tied to the BCLKT pin.
PI
Power Amplifier Input (Pin 3) FST
Frame Sync, Transmit (Pin 14)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier is internally tied to the This pin accepts an 8 kHz clock that synchronizes the out-
VAG pin. The PI and PO– pins are used with external resis- put of the serial PCM data at the DT pin. This input is com-
tors in an inverting op amp gain circuit to set the gain of the patible with both Long Frame Sync and Short Frame Sync. If
PO+ and PO– push–pull power amplifier outputs. Connect- both FST and FSR are held low for several 8 kHz frames, the
ing PI to VDD will power down the power driver amplifiers and device will power down. FST must be clocking for the device
the PO+ and PO– outputs will be high impedance. to power up affter being powered down by the frame syncs.

PO– BCLKT
Power Amplifier Output (Inverting) (Pin 4) Bit Clock, Transmit (Pin 12)
This pin controls the transfer rate of transmit PCM data. In
This is the inverting power amplifier output, which is used the synchronous modes of sign–bit extended and receive
to provide a feedback signal to the PI pin to set the gain of gain adjust, the BCLKT also controls the transfer rate of the
the push–pull power amplifier outputs. This pin is capable of receive PCM data. This pin can accept any bit clock frequen-
driving a 300 Ω load to PO+. The PO+ and PO– outputs are cy from 256 to 4096 kHz for Long Frame Sync and Short
differential (push–pull) and capable of driving a 300 Ω load to Frame Sync timing.
1.772 V peak, which is 3.544 V peak–to–peak. The bias volt-
age and signal reference of this output is the VAG pin. The DT
VAG pin cannot source or sink as much current as this pin, Data, Transmit (Pin 13)
and therefore low impedance loads must be between PO+
This pin is controlled by FST and BCLKT and is high im-
and PO–. The PO+ and PO– differential drivers are also ca-
pedance except when outputting PCM data. This pin is high
pable of driving a 100 Ω resistive load or a 100 nF Piezoelec-
impedance when the device is in the powered–down mode.
tric transducer in series with a 20 Ω resister with a smalll
increase in distortion. These drivers may be used to drive re- FSR
sistive loads of ≥ 32 Ω when the gain of PO– is set to 1/4 or Frame Sync, Receive (Pin 7)
less. Connecting PI to VDD will power down the power driver
amplifiers, and the PO+ and PO– outputs will be high imped- This pin accepts an 8 kHz clock, which synchronizes the
input of the serial PCM data at the DR pin. FSR can be
ance. This pin is also high impedance when the device is
powered down by the PDI pin. asynchronous to FST in the Long Frame Sync or Short
Frame Sync modes.
PO+
BCLKR
Power Amplifier Output (Non–Inverting) (Pin 5)
Bit Clock, Receive (Pin 9)
This is the non–inverting power amplifier output, which is
This pin accepts any bit clock frequency from 256 to 4096
an inverted version of the signal at PO–. This pin is capable
kHz. The BCLKR pin is also used as a mode select pin when
of driving a 300 Ω load to PO–. Connecting PI to VDD will
not being clocked for several 8 kHz frames. The BCKLT pin
power down the power driver amplifiers and the PO+ and
is used to clock the receive PCM data transfers when the
PO– outputs will be high impedance. This pin is also high im-
BCLKR pin is not being clocked. When the BCLKR pinis a
pedance when the device is powered down by the PDI pin.
logic 0, the sign–bit extended synchronous mode is selected,
See PI and PO– for more information.
which uses 16–bit transfers with the first four bits being the
DIGITAL INTERFACE sign bit. When the BCLKR pin is a logic 1, the receive gain
adjust synchronous mode is selected, which uses a 13–bit
MCLK transfer for the transmit PCM data, but uses a 16–bit transfer
Master Clock (Pin 11) for the receive side, with the 13–bit voice data being first, fol-
This is the master clock input pin. The clock signal applied lowed by three bits which control the attenuation of the re-
to this pin is used to generate the internal 256 kHz clock and ceive analog output.
sequencing signals for the switched–capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on DR
this pin to the clock at FST (8 kHz) and will automatically Data, Receive (Pin 8)
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For This pin is the PCM data input. See the pin descriptions for
MCLK frequencies of 256 and 512 kHz, MCLK must be syn- FSR, BCLKR, and BCKLT for more information.

MC145483 MOTOROLA
4
 FUNCTIONAL DESCRIPTION same bit voltage weighting about the zero crossing. This re-
sults in the 0 dBm0 calibration level being 3.20 dB below the
ANALOG INTERFACE AND SIGNAL PATH peak sinusoidal level before clipping. Based on the reference
The transmit portion of this device includes a low–noise, voltage of 0.886 V, the calibration level is 0.436 Vrms or
three–terminal op amp capable of driving a 2 kΩ load. This – 5 dBm at 600 Ω.
op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its The MC145483 has the ability to attenuate the receive
output is TG (Pin 17). This op amp is intended to be confi- analog output when used in the receive gain adjust mode.
gured in an inverting gain circuit. The analog signal may be This mode is accessed by applying a logic high to the
applied directly to the TG pin if this transmit op amp is inde- BCLKR pin while the rest of the clock pins are clocked nor-
pendently powered down by connecting the TI+ input to the mally. This allows three additional bits that will be used to
VDD power supply. The TG pin becomes high impedance control the gain of the analog output to be clocked into the
when the transmit op amp is powered down. The TG pin is DR pin following the 13 bits of voice data. Table 1 shows the
internally connected to a 3–pole anti–aliasing pre–filter. This attenuation values and the corresponding digital codes.
pre–filter incorporates a 2–pole Butterworth active low–pass
filter, followed by a single passive pole. This pre–filter is fol- Table 1. Receive Gain Adjust Mode
lowed by a single–ended to differential converter that is Coefficients and Attenuation Weightings
clocked at 512 kHz. All subsequent analog processing uti-
Coefficient Attenuation in dB
lizes fully–differential circuitry. The next section is a fully–dif-
ferential, 5–pole switched–capacitor low–pass filter with a 000 0
3.4 kHz frequency cutoff. After this filter is a 3–pole 001 –3
switched–capacitor high–pass filter having a cutoff fre-
quency of about 200 Hz. This high–pass stage has a trans- 010 –6
mission zero at dc that eliminates any dc coming from the 011 –9
analog input or from accumulated op amp offsets in the pre-
100 – 12
ceding filter stages. The high–pass filter may be bypassed or
removed from the signal path by the HB pin. When the high– 101 – 15
pass filter is bypassed, the frequency response extends 110 – 18
down to include dc. The last stage of the high–pass filter is
an autozeroed sample and hold amplifier. 111 – 21
One bandgap voltage reference generator and digital–to–
analog converter (DAC) are shared by the transmit and re-
ceive sections. The autozeroed, switched–capacitor POWER–DOWN
bandgap reference generates precise positive and negative
There are two methods of putting this device into a low
reference voltages that are virtually independent of tempera-
power consumption mode, which makes the device nonfunc-
ture and power supply voltage. A capacitor array (CDAC) is
tional and consumes virtually no power. PDI is the power–
combined with a resistor string (RDAC) to implement the
down input pin which, when taken low, powers down the
13–bit linear DAC structure. The encode process uses the
device. Another way to power the device down is to hold both
DAC, the voltage reference, and a frame–by–frame auto-
the FST and FSR pins low while the BCLKT and MCLK pins
zeroed comparator to implement a successive approxima-
are clocked. When the chip is powered down, the VAG, TG,
tion conversion algorithm. All of the analog circuitry involved
RO–, PO+, PO–, and DT outputs are high impedance and
in the data conversion (the voltage reference, RDAC, CDAC,
the VAG Ref pin is pulled to the VDD power supply with a non–
and comparator) are implemented with a differential architec-
linear, high–impedance circuit. To return the chip to the pow-
ture.
er–up state, PDI must be high and the FST frame sync pulse
The receive section includes the DAC described above, a
must be present while the BCLKT and MCLK pins are
sample and hold amplifier, a 5–pole, 3400 Hz switched ca-
clocked. The DT output will remain in a high–impedance
pacitor low–pass filter with sinX/X correction, and a 2–pole
state for at least two 8 kHz FST pulses after power–up.
active smoothing filter to reduce the spectral components of
the switched capacitor filter. The output of the smoothing fil- MASTER CLOCK
ter is buffered by an amplifier, which is output at the RO– pin.
This output is capable of driving a 2 kΩ load to the VAG pin. Since this codec–filter design has a single DAC architec-
The MC145483 also has a pair of power amplifiers that are ture, the MCLK pin is used as the master clock for all analog
connected in a push–pull configuration. The PI pin is the in- signal processing including analog–to–digital conversion,
verting input to the PO– power amplifier. The non–inverting digital–to–analog conversion, and for transmit and receive fil-
input is internally tied to the VAG pin. This allows this amplifier tering functions of this device. The clock frequency applied to
to be used in an inverting gain circuit with two external resis- the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,
tors. The PO+ amplifier has a gain of minus one, and is in- 1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-
ternally connected to the PO– output. This complete power vice has a prescaler that automatically determines the proper
amplifier circuit is a differential (push–pull) amplifier with ad- divide ratio to use for the MCLK input, which achieves the re-
justable gain. The power amplifier may be powered down in- quired 256 kHz internal sequencing clock. The clocking re-
dependently of the rest of the chip by connecting the PI pin to quirements of the MCLK input are independent of the PCM
VDD. data transfer mode (i.e., Long Frame Sync, Short Frame
The calibration level for both ADC and DAC of this 13–bit Sync, whether the device is used in the synchronous modes
linear PCM Codec–Filter is referenced to Mu–Law with the or not).

MOTOROLA MC145483
5
DIGITAL I/O Table 2. PCM Codes for Zero and Full–Scale
The MC145483 is a 13–bit linear device using 2s comple- Level Sign Bit Magnitude Bits
ment data format. Table 2 shows the 13–bit data word format + Full Scale 0 1111 1111 1111
for the maximum positive code and negative zero and full–
scale. + One Step 0 0000 0000 0001
Table 3 shows the series of eight 13–bit PCM words that Zero 0 0000 0000 0000
correspond to a digital milliwatt. The digital milliwatt is the
– One Step 1 1111 1111 1111
1 kHz calibration signal reconstructed by the DAC that de-
fines the absolute gain or 0 dBm0 transmission level point – Full Scale 1 0000 0000 0000
(TLP) of the DAC. The calibration level for this 13–bit linear
ADC and DAC is referenced to Mu–Law with the same bit Table 3. PCM Codes for 1 kHz Digital Milliwatt
voltage weighting about the zero crossing. This results in the
0 dBm0 calibration level being 3.20 dB below the peak sinu- Level Sign Bit Magnitude Bits
soidal level before clipping. Refer to Figures 2a–2d for a π/8
summary and comparison of the four PCM data interface
3π/8
modes of this device.
5π/8
7π/8
9π/8
11π/8
13π/8
15π/8

MC145483 MOTOROLA
6
 FST (FSR)

BCLKT (BCLKR)

DT 1 2 3 4 5 6 7 8 9 10 11 12 13

DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 DON’T CARE

Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking)

FST (FSR)

BCLKT (BCLKR)

DT 1 2 3 4 5 6 7 8 9 10 11 12 13

DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 DON’T CARE

Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking)

FST (FSR)
SHORT OR
LONG FRAME
SYNC

BCLKT

DT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON’T CARE

Figure 2c. Sign–Extended (BCLKR = 0)

Transmit and receive both use BCLKT, and the first four data bits are the sign bit.
FST may occur at a different time than FSR.

FST (FSR)
SHORT OR
LONG FRAME
SYNC

BCLKT

DT 1 2 3 4 5 6 7 8 9 10 11 12 13

DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON’T CARE

Figure 2d. Receive Gain Adjust (BCLKR = 1)

Transmit and receive both use BCLKT. FST may occur at a different time than FSR.
Bits 14, 15, and 16, clocked into DR, are used for attenuation control for the receive analog output.

Figure 2. Digital Timing Modes for the PCM Data Interface

MOTOROLA MC145483
7
 PRINTED CIRCUIT BOARD LAYOUT 5. Bypass capacitors should be connected from the VDD,
CONSIDERATIONS VAG Ref, and VAG pins to VSS with minimal trace length.
Ceramic monolithic capacitors of about 0.1 µF are
The MC145483 is manufactured using high–speed CMOS acceptable for the VDD and VAG Ref pins to decouple the
VLSI technology to implement the complex analog signal device from its own noise. The VDD capacitor helps
processing functions of a PCM Codec–Filter. The fully–differ- supply the instantaneous currents of the digital circuitry
ential analog circuit design techniques used for this device in addition to decoupling the noise which may be
result in superior performance for the switched capacitor fil- generated by other sections of the device or other
ters, the analog–to–digital converter (ADC) and the digital– circuitry on the power supply. The VAG Ref decoupling
to–analog converter (DAC). Special attention was given to capacitor is effecting a low–pass filter to isolate the
the design of this device to reduce the sensitivities of noise, mid–supply voltage from the power supply noise gener-
including power supply rejection and susceptibility to radio ated on–chip, as well as external to the device. The VAG
frequency noise. This special attention to design includes a decoupling capacitor should be about 0.01 µF. This
fifth order low–pass filter, followed by a third order high–pass helps to reduce the impedance of the VAG pin to VSS at
filter whose output is converted to a digital signal with greater frequencies above the bandwidth of the VAG generator,
than 75 dB of dynamic range, all operating on a single 3 V which reduces the susceptiblility to RF noise.
power supply. This results in an LSB size for small audio sig-
6. Use a short, wide, low inductance trace to connect the
nals of about 216 µV. The typical idle channel noise level of
VSS ground pin to the power supply ground. The VSS pin
this device is less than one LSB. In addition to the dynamic
is the digital ground and the most negative power supply
range of the codec–filter function of this device, the input
pin for the analog circuitry. All analog signal processing
gain–setting op amp has the capability of greater than 30 dB
is referenced to the VAG pin, but because digital and RF
of gain intended for an electret microphone interface.
circuitry will probably be powered by this same ground,
This device was designed for ease of implementation, but
care must be taken to minimize high frequency noise in
due to the large dynamic range and the noisy nature of the
the VSS trace. Depending on the application, a double–
environment for this device (digital switches, radio tele-
sided PCB with a VSS ground plane connecting all of the
phones, DSP front–end, etc.) special care must be taken to
digital and analog VSS pins together would be a good
assure optimum analog transmission performance.
grounding method. A multilayer PC board with a ground
plane connecting all of the digital and analog VSS pins
PC BOARD MOUNTING
together would be the optimal ground configuration.
It is recommended that the device be soldered to the PC These methods will result in the lowest resistance and
board for optimum noise performance. If the device is to be the lowest inductance in the ground circuit. This is
used in a socket, it should be placed in a low parasitic pin important to reduce voltage spikes in the ground circuit
inductance (generally, low–profile) socket. resulting from the high speed digital current spikes. The
magnitude of digitally induced voltage spikes may be
POWER SUPPLY, GROUND, AND NOISE hundreds of times larger than the analog signal the
CONSIDERATIONS device is required to digitize.
This device is intended to be used in switching applica- 7. Use a short, wide, low inductance trace to connect the
tions which often require plugging the PC board into a rack V DD power supply pin to the 3 V power supply.
with power applied. This is known as ‘‘hot–rack insertion.’’ In Depending on the application, a double–sided PCB with
these applications care should be taken to limit the voltage VDD bypass capacitors to the VSS ground plane, as
on any pin from going positive of the VDD pins, or negative of described above, may complete the low impedance
the VSS pins. One method is to extend the ground and power coupling for the power supply. For a multilayer PC board
contacts of the PCB connector. The device has input protec- with a power plane, connecting all of the V DD pins to the
tion on all pins and may source or sink a limited amount of power plane would be the optimal power distribution
current without damage. Current limiting may be accom- method. The integrated circuit layout and packaging
plished by series resistors between the signal pins and the considerations for the 3 V V DD power circuit are
connector contacts. essentially the same as for the VSS ground circuit.
The most important considerations for PCB layout deal 8. The VAG pin is the reference for all analog signal
with noise. This includes noise on the power supply, noise processing. In some applications the audio signal to be
generated by the digital circuitry on the device, and cross digitized may be referenced to the VSS ground. To
coupling digital or radio frequency signals into the audio sig- reduce the susceptibility to noise at the input of the ADC
nals of this device. The best way to prevent noise is to: section, the three–terminal op amp may be used in a
1. Keep digital signals as far away from audio signals as differential to single–ended circuit to provide level
possible. conversion from the VSS ground to the VAG ground with
noise cancellation. The op amp may be used for more
2. Keep radio frequency signals as far away from the audio
than 30 dB of gain in microphone interface circuits, which
signals as possible.
will require a compact layout with minimum trace lengths
3. Use short, low inductance traces for the audio circuitry as well as isolation from noise sources. It is recom-
to reduce inductive, capacitive, and radio frequency mended that the layout be as symmetrical as possible to
noise sensitivities. avoid any imbalances which would reduce the noise
4. Use short, low inductance traces for digital and RF cancelling benefits of this differential op amp circuit.
circuitry to reduce inductive, capacitive, and radio Refer to the application schematics for examples of this
frequency radiated noise. circuitry.

MC145483 MOTOROLA
8
 If possible, reference audio signals to the VAG pin fer to the application schematics for examples of this
instead of to the VSS pin. Handset receivers and tele- circuitry. The VAG pin cannot be used for ESD or line
phone line interface circuits using transformers may be protection.
audio signal referenced completely to the VAG pin. Re-

MOTOROLA MC145483
9
MAXIMUM RATINGS (Voltages Referenced to VSS Pin)
Rating Symbol Value Unit
DC Supply Voltage VDD – 0.5 to 6 V
Voltage on Any Analog Input or Output Pin VSS – 0.3 to VDD + 0.3 V
Voltage on Any Digital Input or Output Pin VSS – 0.3 to VDD + 0.3 V
Operating Temperature Range TA – 40 to + 85 °C
Storage Temperature Range Tstg – 85 to +150 °C

POWER SUPPLY (TA = – 40 to + 85°C)

Characteristics Min Typ Max Unit
DC Supply Voltage 2.7 3.0 5.25 V
Active Current Dissipation (VDD = 3 V) (No Load, PI ≥ VDD – 0.5 V) — 2.3 — mA
(No Load, PI ≤ VDD – 1.0 V) — 2.5 —
Power–Down Current (VIH for Logic Levels PDI = VSS — 0.001 — mA
Must be ≥ VDD – 0.5 V) FST and FSR = VSS, PDI = VDD — 0.01 —

DIGITAL LEVELS (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = – 40 to + 85°C)

Characteristics Symbol Min Max Unit
Input Low Voltage VIL — 0.6 V
Input High Voltage VIH 2.2 — V
Output Low Voltage (DT Pin, IOL= 1.6 mA) VOL — 0.4 V
Output High Voltage (DT Pin, IOH = – 1.6 mA) VOH VDD – 0.5 — V
Input Low Current (VSS ≤ Vin ≤ VDD) IIL – 10 + 10 µA
Input High Current (VSS ≤ Vin ≤ VDD) IIH – 10 + 10 µA
Output Current in High Impedance State (VSS ≤ DT ≤ VDD) IOZ – 10 + 10 µA
Input Capacitance of Digital Pins (Except DT) Cin — 10 pF
Input Capacitance of DT Pin when High–Z Cout — 15 pF

MC145483 MOTOROLA
10
ANALOG ELECTRICAL CHARACTERISTICS (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = – 40 to + 85°C)
Characteristics Min Typ Max Unit
Input Current TI+, TI– — ± 0.1 ± 1.0 µA
Input Resistance to VAG (VAG – 0.3 V ≤ Vin ≤ VAG + 0.3 V) TI+, TI– 10 — — MΩ
Input Capacitance TI+, TI– — — 10 pF
Input Offset Voltage of TG Op Amp TI+, TI– — — ±5 mV
Input Common Mode Voltage Range TI+, TI– 1.2 VDD – 1.2 V
Input Common Mode Rejection Ratio TI+, TI– — TBD — dB
Gain Bandwidth Product (10 kHz) of TG Op Amp (RL ≥ 10 kΩ) — 3000 — kHz
DC Open Loop Gain of TG Op Amp (RL ≥ 10 kΩ) — 95 — dB
Equivalent Input Noise (C–Message) Between TI+ and TI– at TG — TBD — dBrnC
Output Load Capacitance for TG Op Amp 0 — 100 pF
Output Voltage Range for TG (RL = 2 kΩ to VAG) 0.4 — VDD – 0.4 V
Output Current (0.5 V ≤ Vout ≤ VDD – 0.5 V) TG, RO– TBD — — mA
Output Load Resistance to VAG TG, RO– 2 — — kΩ
Output Impedance RO– — 1 — Ω
Output Load Capacitance RO– 0 — 200 pF
DC Output Offset Voltage of RO– Referenced to VAG — — ± 25 mV
VAG Output Voltage Referenced to VSS (No Load) VDD/2 – 0.05 VDD/2 VDD/2 + 0.05 V
VAG Output Current with ± 25 mV Change in Output Voltage ± 2.0 ± 10 — mA
Power Supply Rejection Ratio Transmit TBD TBD — dBC
(0 to 100 kHz @100 mVrms Applied to VDD, Receive TBD TBD —
C–Message Weighting, All Analog Signals
Referenced to VAG Pin)
Power Drivers PI, PO+, PO–
Input Current (VAG – 0.3 V ≤ PI ≤ VAG + 0.3 V) PI — ± 0.05 ± 1.0 µA
Input Resistance (VAG – 0.3 V ≤ PI ≤ VAG + 0.3 V) PI 10 — — MΩ
Input Offset Voltage PI — — ± 20 mV
Output Offset Voltage of PO+ Relative to PO– (Inverted Unity Gain for PO–) — — ± 50 mV
Output Current (VSS + 0.4 V ≤ PO+ or PO– ≤ VDD – 0.4 V) TBD — — mA
PO+ or PO– Output Resistance (Inverted Unity Gain for PO–) — 1 — Ω
Gain Bandwidth Product (10 kHz, Open Loop for PO–) — 1000 — kHz
Load Capacitance (PO+ or PO– to VAG, or PO+ to PO–) 0 — 1000 pF
Gain of PO+ Relative to PO– (RL = 300 Ω, + 3 dBm0, 1 kHz) – 0.2 0 + 0.2 dB
Total Signal to Distortion at PO+ and PO– with a Differential Load of: 300 Ω 45 60 — dBC
100 nF in series with ≥ 20 Ω — 40 —
≥ 100 Ω — 40 —
Power Supply Rejection Ratio 0 to 4 kHz TBD TBD — dB
(0 to 25 kHz @ 50 mVrms Applied to VDD. 4 to 25 kHz — TBD —
PO– Connected to PI. Differential or Measured
Referenced to VAG Pin.)

MOTOROLA MC145483
11
ANALOG TRANSMISSION PERFORMANCE
(VDD = 2.7 to 3.6 V, VSS = 0 V, All Analog Signals Referenced to VAG, 0 dBm0 = 0.436 Vrms = – 5 dBm @ 600 Ω, FST = FSR = 8 kHz,
BCLKT = MCLK = 2.048 MHz Synchronous Operation, TA = – 40 to + 85°C, Unless Otherwise Noted)
A/D D/A
Characteristics
Ch i i Min Typ Max Min Typ Max Units
U i
Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25°C, VDD = 5.0 V) – 0.25 — + 0.25 – 0.25 — + 0.25 dB
Absolute Gain Variation with Temperature 0 to + 70°C — TBD — — TBD — dB
– 40 to + 85°C — TBD — — TBD —
Absolute Gain Variation with Power Supply (TA = 25°C) — TBD — — TBD — dB
Total Distortion, 1.02 kHz Tone (C–Message Weighting)
+ 3 dBm0 — 55 — — 60 — dBC
0 dBm0 — 58 — — 60 —
– 10 dBm0 — 58 — — 60 —
– 20 dBm0 — 53 — — 55 —
– 30 dBm0 — 44 — — 46 —
–40 dBm0 — 34 — — 36 —
–50 dBm0 — 24 — — 26 —
–60 dBm0 — 14 — — 16 —
Idle Channel Noise (For End–to–End and A/D, See Note 1)
(C–Message Weighted) — — 19 — — 14 dBr nc0
(Psophometric Weighted) — — – 68 — — – 76 dBm0p
Frequency Response 15 Hz — — – 40 – 0.5 — 0 dB
(Relative to 1.02 kHz @ 0 dBm0) (HB = 0) 50 Hz — — – 30 – 0.5 — 0
60 Hz — — – 26 – 0.5 — 0
165 Hz — –3 — – 0.5 — 0
200 Hz – 1.0 — – 0.4 – 0.5 — 0
300 to 3000 Hz – 0.20 — + 0.20 – 0.20 — + 0.20
3300 Hz – 0.35 — + 0.20 – 0.35 — + 0.20
3400 Hz – 0.9 — 0 – 0.9 — 0
3600 Hz — –3 — — –3 —
4000 Hz — — – 14 — — – 14
4600 Hz to 100 kHz — — – 32 — — – 30
Out–of–Band Spurious at VAG Ref (300 to 3400 Hz @ 0 dBm0 in)
4600 to 7600 Hz — — — — — – 30 dB
7600 to 8400 Hz — — — — — – 40
8400 to 100,000 Hz — — — — — – 30
Idle Channel Noise Selective (8 kHz, Input = VAG, 30 Hz Bandwidth) — — — — — – 70 dBm0
Absolute Delay (1600 Hz) (HB = 0) — — 315 — — 205 µs
Group Delay Referenced to 1600 Hz 500 to 600 Hz — — 210 – 40 — — µs
600 to 800 Hz — — 130 – 40 — —
800 to 1000 Hz — — 70 – 40 — —
1000 to 1600 Hz — — 35 – 30 — —
1600 to 2600 Hz — — 70 — — 85
2600 to 2800 Hz — — 95 — — 110
2800 to 3000 Hz — — 145 — — 175
Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2) — — – 75 — — – 75 dB

NOTES:
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while stimulated with 2667 Hz @ – 50 dBm0.

MC145483 MOTOROLA
12
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(VDD = 2.7 to 3.6 V, VSS = 0 V, All Digital Signals Referenced to VSS, TA = – 40 to + 85°C, CL = 150 pF, Unless Otherwise Noted)
Ref.
No. Characteristics Min Typ Max Unit
1 Master Clock Frequency for MCLK — 256 — kHz
— 512 —
— 1536 —
— 1544 —
— 2048 —
— 2560 —
— 4096 —

1 MCLK Duty Cycle for 256 kHz Operation 45 — 55 %

2 Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater) 50 — — ns
3 Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater) 50 — — ns
4 Rise Time for All Digital Signals — — 50 ns
5 Fall Time for All Digital Signals — — 50 ns
6 Setup Time from MCLK Low to FST High 50 — — ns
7 Setup Time from FST High to MCLK Low 50 — — ns
8 Bit Clock Data Rate for BCLKT or BCLKR 256 — 4096 kHz
9 Minimum Pulse Width High for BCLKT or BCLKR 50 — — ns
10 Minimum Pulse Width Low for BCLKT or BCLKR 50 — — ns
11 Hold Time from BCLKT (BCLKR) Low to FST (FSR) High 20 — — ns
12 Setup Time for FST (FSR) High to BCLKT (BCLKR) Low 80 — — ns
13 Setup Time from DR Valid to BCLKR Low 0 — — ns
14 Hold Time from BCLKR Low to DR Invalid 50 — — ns
LONG FRAME SPECIFIC TIMING
15 Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low 50 — — ns
16 Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data — — 60 ns
17 Delay Time from BCLKT High to DT for Valid Data — — 60 ns
18 Delay Time from the Later of the 13th (16th for Sign–Extended Mode) BCLKT 10 — 60 ns
Falling Edge, or the Falling Edge of FST to DT Output High Impedance
19 Minimum Pulse Width Low for FST or FSR 50 — — ns
SHORT FRAME SPECIFIC TIMING
20 Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low 50 — — ns
21 Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low 50 — — ns
22 Delay Time from BCLKT High to DT Data Valid 10 — 60 ns
23 Delay Time from the 13th (16th for Sign–Extended Mode) BCLKT Low to DT 10 — 60 ns
Output High Impedance

MOTOROLA MC145483
13
 1
7 4
3
6 2 5

MCLK
8

BCLKT 1 2 3 4 5 6 7 13 14
12
9
11
15 10

FST

16 18
17
16 18

DT 1 2 3 4 5 6 13

BCLKR 1 2 3 4 5 6 7 13 14
(BCLKT)
11 15 9
12 10

FSR

14
13

DR 1 2 3 4 5 6 13

Figure 3. Long Frame Sync Timing

MC145483 MOTOROLA
14
 1
7 4
3
6 2 5

MCLK

12 8

BCLKT 1 2 3 4 5 6 7 13 14

20 9
21 10
11

FST

23
22
22

DT 1 2 3 4 5 6 13

BCLKR 1 2 3 4 5 6 7 13 14

20 9
11 21 10
12

FSR

14
13

DR 1 2 3 4 5 6 13

Figure 4. Short Frame Sync Timing

MOTOROLA MC145483
15
 0.01 µF
1 20
VAG Ref VAG 10 kΩ
10 kΩ 1.0 µF ANALOG IN
2 19
0.1 µF RO– TI+

2X20 k
3
PI TI–
18
10 kΩ 10 kΩ
Y
4 17
– PO– TG
AUDIO OUT + 1.0 µF
5 HB 16
PO+
6 15
+3V VDD VSS
7 14
FSR FST 8 kHz
0.1 µF
8 13
DR DT PCM OUT
9 12
BCLKR BCLKT 2.048 MHz
10 11
PDI MCLK

PCM IN

Figure 5. MC145483 Test Circuit — Signals Referenced to VAG Pin

0.1 µF 0.01 µF
1 20
VAG Ref VAG 10 kΩ
AUDIO OUT 10 kΩ 1.0 µF
2 19
RL ≥ 2 kΩ RO– TI+
3 18
2X20 k PI TI–
AUDIO OUT 68 µF
+ 4 17 10 kΩ 10 kΩ ANALOG IN
RL ≥ 150 Ω PO– TG

10 kΩ
5
PO+ HB 16
1.0 µF
Y
6 15
+3V VDD VSS
7 14
FSR FST 8 kHz
0.1 µF
8 13 PCM OUT
DR DT
9 12
BCLKR BCLKT 2.048 MHz
10 11
PDI MCLK

PCM IN

Figure 6. MC145483 Test Circuit — Signals Referenced to VSS

MC145483 MOTOROLA
16
 +3 V

1 kΩ
SIDETONE

0.1 µF 0.01 µF 68 µF
1 kΩ
420 pF

1 20
VAG Ref VAG 75 kΩ
2 1 kΩ 0.1 µF
19
RO– TI+
3 1 kΩ MIC
18
PI TI–
4 17 0.1 µF
PO– TG 75 kΩ
REC 5 16
PO+ HB
420 pF
6 15
+3V VDD VSS
7 14
FSR FST 8 kHz
0.1 µF
8 13
DR DT PCM OUT
9 12
BCLKR BCLKT 2.048 MHz
10 11
PDI MCLK

PCM IN

Figure 7. MC145483 Handset Interface

1.0 µF 10 kΩ

R0 = 600 Ω TIP 0.1 µF 1 20

VAG Ref VAG
2X20 k 2 19
N = 0.5 RO– TI+
1/4 R0 3 18
PI TI– 0.1 µF
20 kΩ
4 17
N = 0.5 PO– TG
5 16
– 48 V PO+ HB
6 15
N = 0.5 +3V VDD VSS
7 14
FSR FST 8 kHz
RING 0.1 µF 8 13
DR DT PCM OUT
9 12
BCLKR BCLKT 2.048 MHz
10 11
PDI MCLK

PCM IN

Figure 8. MC145483 Step–Up Transformer Line Interface

MOTOROLA MC145483
17
 PACKAGE DIMENSIONS

DW SUFFIX
SOG PACKAGE
CASE 751D–04

–A– NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
20 11 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
–B– 10X P (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.010 (0.25) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
1 10 (0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

20X D MILLIMETERS INCHES

J DIM MIN MAX MIN MAX
0.010 (0.25) M T A S B S A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
F D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
R X 45 _ J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 10.05 10.55 0.395 0.415
C R 0.25 0.75 0.010 0.029

–T– SEATING
PLANE
18X G M
K

SD SUFFIX
SSOP
CASE 940C–02

20 11 NOTES:
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ANSI
B Y14.5M, 1982.
–R– 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
C MEASURED AT THE PARTING LINE. MOLD
1 10 FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.15MM PER SIDE.
4. DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
5. TERMINAL POSITIONS ARE SHOWN FOR
A 0.076 (0.003) REFERENCE ONLY.
–P– N 6. THE LEAD WIDTH DIMENSION DOES NOT
INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL
BE 0.08MM TOTAL IN EXCESS OF THE LEAD
WIDTH DIMENSION.

MILLIMETERS INCHES
0.25 (0.010) M R M DIM MIN MAX MIN MAX
A 7.10 7.30 0.280 0.287
L
B 5.20 5.38 0.205 0.212
C 1.75 1.99 0.069 0.078
D 0.25 0.38 0.010 0.015
J M F 0.65 1.00 0.026 0.039
G 0.65 BSC 0.026 BSC
H 0.59 0.75 0.023 0.030
J 0.10 0.20 0.004 0.008
G L 7.65 7.90 0.301 0.311
F M 0_ 8_ 0_ 8_
H D NOTE 4 N 0.05 0.21 0.002 0.008
0.120 (0.005) M T P S

MC145483 MOTOROLA
18
 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MOTOROLA ◊ MC145483/D
MC145483
19
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.